1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * x86 SMP booting functions
4 *
5 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
6 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Copyright 2001 Andi Kleen, SuSE Labs.
8 *
9 * Much of the core SMP work is based on previous work by Thomas Radke, to
10 * whom a great many thanks are extended.
11 *
12 * Thanks to Intel for making available several different Pentium,
13 * Pentium Pro and Pentium-II/Xeon MP machines.
14 * Original development of Linux SMP code supported by Caldera.
15 *
16 * Fixes
17 * Felix Koop : NR_CPUS used properly
18 * Jose Renau : Handle single CPU case.
19 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
20 * Greg Wright : Fix for kernel stacks panic.
21 * Erich Boleyn : MP v1.4 and additional changes.
22 * Matthias Sattler : Changes for 2.1 kernel map.
23 * Michel Lespinasse : Changes for 2.1 kernel map.
24 * Michael Chastain : Change trampoline.S to gnu as.
25 * Alan Cox : Dumb bug: 'B' step PPro's are fine
26 * Ingo Molnar : Added APIC timers, based on code
27 * from Jose Renau
28 * Ingo Molnar : various cleanups and rewrites
29 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
30 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
31 * Andi Kleen : Changed for SMP boot into long mode.
32 * Martin J. Bligh : Added support for multi-quad systems
33 * Dave Jones : Report invalid combinations of Athlon CPUs.
34 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
35 * Andi Kleen : Converted to new state machine.
36 * Ashok Raj : CPU hotplug support
37 * Glauber Costa : i386 and x86_64 integration
38 */
39
40 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
41
42 #include <linux/init.h>
43 #include <linux/smp.h>
44 #include <linux/export.h>
45 #include <linux/sched.h>
46 #include <linux/sched/topology.h>
47 #include <linux/sched/hotplug.h>
48 #include <linux/sched/task_stack.h>
49 #include <linux/percpu.h>
50 #include <linux/memblock.h>
51 #include <linux/err.h>
52 #include <linux/nmi.h>
53 #include <linux/tboot.h>
54 #include <linux/stackprotector.h>
55 #include <linux/gfp.h>
56 #include <linux/cpuidle.h>
57 #include <linux/numa.h>
58
59 #include <asm/acpi.h>
60 #include <asm/desc.h>
61 #include <asm/nmi.h>
62 #include <asm/irq.h>
63 #include <asm/realmode.h>
64 #include <asm/cpu.h>
65 #include <asm/numa.h>
66 #include <asm/pgtable.h>
67 #include <asm/tlbflush.h>
68 #include <asm/mtrr.h>
69 #include <asm/mwait.h>
70 #include <asm/apic.h>
71 #include <asm/io_apic.h>
72 #include <asm/fpu/internal.h>
73 #include <asm/setup.h>
74 #include <asm/uv/uv.h>
75 #include <linux/mc146818rtc.h>
76 #include <asm/i8259.h>
77 #include <asm/misc.h>
78 #include <asm/qspinlock.h>
79 #include <asm/intel-family.h>
80 #include <asm/cpu_device_id.h>
81 #include <asm/spec-ctrl.h>
82 #include <asm/hw_irq.h>
83
84 /* representing HT siblings of each logical CPU */
85 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
86 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
87
88 /* representing HT and core siblings of each logical CPU */
89 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map);
90 EXPORT_PER_CPU_SYMBOL(cpu_core_map);
91
92 /* representing HT, core, and die siblings of each logical CPU */
93 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_die_map);
94 EXPORT_PER_CPU_SYMBOL(cpu_die_map);
95
96 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map);
97
98 /* Per CPU bogomips and other parameters */
99 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
100 EXPORT_PER_CPU_SYMBOL(cpu_info);
101
102 struct mwait_cpu_dead {
103 unsigned int control;
104 unsigned int status;
105 };
106
107 /*
108 * Cache line aligned data for mwait_play_dead(). Separate on purpose so
109 * that it's unlikely to be touched by other CPUs.
110 */
111 static DEFINE_PER_CPU_ALIGNED(struct mwait_cpu_dead, mwait_cpu_dead);
112
113 /* Logical package management. We might want to allocate that dynamically */
114 unsigned int __max_logical_packages __read_mostly;
115 EXPORT_SYMBOL(__max_logical_packages);
116 static unsigned int logical_packages __read_mostly;
117 static unsigned int logical_die __read_mostly;
118
119 /* Maximum number of SMT threads on any online core */
120 int __read_mostly __max_smt_threads = 1;
121
122 /* Flag to indicate if a complete sched domain rebuild is required */
123 bool x86_topology_update;
124
arch_update_cpu_topology(void)125 int arch_update_cpu_topology(void)
126 {
127 int retval = x86_topology_update;
128
129 x86_topology_update = false;
130 return retval;
131 }
132
smpboot_setup_warm_reset_vector(unsigned long start_eip)133 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
134 {
135 unsigned long flags;
136
137 spin_lock_irqsave(&rtc_lock, flags);
138 CMOS_WRITE(0xa, 0xf);
139 spin_unlock_irqrestore(&rtc_lock, flags);
140 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) =
141 start_eip >> 4;
142 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) =
143 start_eip & 0xf;
144 }
145
smpboot_restore_warm_reset_vector(void)146 static inline void smpboot_restore_warm_reset_vector(void)
147 {
148 unsigned long flags;
149
150 /*
151 * Paranoid: Set warm reset code and vector here back
152 * to default values.
153 */
154 spin_lock_irqsave(&rtc_lock, flags);
155 CMOS_WRITE(0, 0xf);
156 spin_unlock_irqrestore(&rtc_lock, flags);
157
158 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0;
159 }
160
161 /*
162 * Report back to the Boot Processor during boot time or to the caller processor
163 * during CPU online.
164 */
smp_callin(void)165 static void smp_callin(void)
166 {
167 int cpuid;
168
169 /*
170 * If waken up by an INIT in an 82489DX configuration
171 * cpu_callout_mask guarantees we don't get here before
172 * an INIT_deassert IPI reaches our local APIC, so it is
173 * now safe to touch our local APIC.
174 */
175 cpuid = smp_processor_id();
176
177 /*
178 * the boot CPU has finished the init stage and is spinning
179 * on callin_map until we finish. We are free to set up this
180 * CPU, first the APIC. (this is probably redundant on most
181 * boards)
182 */
183 apic_ap_setup();
184
185 /*
186 * Save our processor parameters. Note: this information
187 * is needed for clock calibration.
188 */
189 smp_store_cpu_info(cpuid);
190
191 /*
192 * The topology information must be up to date before
193 * calibrate_delay() and notify_cpu_starting().
194 */
195 set_cpu_sibling_map(raw_smp_processor_id());
196
197 /*
198 * Get our bogomips.
199 * Update loops_per_jiffy in cpu_data. Previous call to
200 * smp_store_cpu_info() stored a value that is close but not as
201 * accurate as the value just calculated.
202 */
203 calibrate_delay();
204 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy;
205 pr_debug("Stack at about %p\n", &cpuid);
206
207 wmb();
208
209 notify_cpu_starting(cpuid);
210
211 /*
212 * Allow the master to continue.
213 */
214 cpumask_set_cpu(cpuid, cpu_callin_mask);
215 }
216
217 static int cpu0_logical_apicid;
218 static int enable_start_cpu0;
219 /*
220 * Activate a secondary processor.
221 */
start_secondary(void * unused)222 static void notrace start_secondary(void *unused)
223 {
224 /*
225 * Don't put *anything* except direct CPU state initialization
226 * before cpu_init(), SMP booting is too fragile that we want to
227 * limit the things done here to the most necessary things.
228 */
229 cr4_init();
230
231 #ifdef CONFIG_X86_32
232 /* switch away from the initial page table */
233 load_cr3(swapper_pg_dir);
234 __flush_tlb_all();
235 #endif
236 load_current_idt();
237 cpu_init();
238 fpu__init_cpu();
239 rcu_cpu_starting(raw_smp_processor_id());
240 x86_cpuinit.early_percpu_clock_init();
241 preempt_disable();
242 smp_callin();
243
244 enable_start_cpu0 = 0;
245
246 /* otherwise gcc will move up smp_processor_id before the cpu_init */
247 barrier();
248 /*
249 * Check TSC synchronization with the boot CPU:
250 */
251 check_tsc_sync_target();
252
253 speculative_store_bypass_ht_init();
254
255 /*
256 * Lock vector_lock, set CPU online and bring the vector
257 * allocator online. Online must be set with vector_lock held
258 * to prevent a concurrent irq setup/teardown from seeing a
259 * half valid vector space.
260 */
261 lock_vector_lock();
262 set_cpu_online(smp_processor_id(), true);
263 lapic_online();
264 unlock_vector_lock();
265 cpu_set_state_online(smp_processor_id());
266 x86_platform.nmi_init();
267
268 /* enable local interrupts */
269 local_irq_enable();
270
271 /* to prevent fake stack check failure in clock setup */
272 boot_init_stack_canary();
273
274 x86_cpuinit.setup_percpu_clockev();
275
276 wmb();
277 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
278
279 /*
280 * Prevent tail call to cpu_startup_entry() because the stack protector
281 * guard has been changed a couple of function calls up, in
282 * boot_init_stack_canary() and must not be checked before tail calling
283 * another function.
284 */
285 prevent_tail_call_optimization();
286 }
287
288 /**
289 * topology_is_primary_thread - Check whether CPU is the primary SMT thread
290 * @cpu: CPU to check
291 */
topology_is_primary_thread(unsigned int cpu)292 bool topology_is_primary_thread(unsigned int cpu)
293 {
294 return apic_id_is_primary_thread(per_cpu(x86_cpu_to_apicid, cpu));
295 }
296
297 /**
298 * topology_smt_supported - Check whether SMT is supported by the CPUs
299 */
topology_smt_supported(void)300 bool topology_smt_supported(void)
301 {
302 return smp_num_siblings > 1;
303 }
304
305 /**
306 * topology_phys_to_logical_pkg - Map a physical package id to a logical
307 *
308 * Returns logical package id or -1 if not found
309 */
topology_phys_to_logical_pkg(unsigned int phys_pkg)310 int topology_phys_to_logical_pkg(unsigned int phys_pkg)
311 {
312 int cpu;
313
314 for_each_possible_cpu(cpu) {
315 struct cpuinfo_x86 *c = &cpu_data(cpu);
316
317 if (c->initialized && c->phys_proc_id == phys_pkg)
318 return c->logical_proc_id;
319 }
320 return -1;
321 }
322 EXPORT_SYMBOL(topology_phys_to_logical_pkg);
323 /**
324 * topology_phys_to_logical_die - Map a physical die id to logical
325 *
326 * Returns logical die id or -1 if not found
327 */
topology_phys_to_logical_die(unsigned int die_id,unsigned int cur_cpu)328 int topology_phys_to_logical_die(unsigned int die_id, unsigned int cur_cpu)
329 {
330 int cpu;
331 int proc_id = cpu_data(cur_cpu).phys_proc_id;
332
333 for_each_possible_cpu(cpu) {
334 struct cpuinfo_x86 *c = &cpu_data(cpu);
335
336 if (c->initialized && c->cpu_die_id == die_id &&
337 c->phys_proc_id == proc_id)
338 return c->logical_die_id;
339 }
340 return -1;
341 }
342 EXPORT_SYMBOL(topology_phys_to_logical_die);
343
344 /**
345 * topology_update_package_map - Update the physical to logical package map
346 * @pkg: The physical package id as retrieved via CPUID
347 * @cpu: The cpu for which this is updated
348 */
topology_update_package_map(unsigned int pkg,unsigned int cpu)349 int topology_update_package_map(unsigned int pkg, unsigned int cpu)
350 {
351 int new;
352
353 /* Already available somewhere? */
354 new = topology_phys_to_logical_pkg(pkg);
355 if (new >= 0)
356 goto found;
357
358 new = logical_packages++;
359 if (new != pkg) {
360 pr_info("CPU %u Converting physical %u to logical package %u\n",
361 cpu, pkg, new);
362 }
363 found:
364 cpu_data(cpu).logical_proc_id = new;
365 return 0;
366 }
367 /**
368 * topology_update_die_map - Update the physical to logical die map
369 * @die: The die id as retrieved via CPUID
370 * @cpu: The cpu for which this is updated
371 */
topology_update_die_map(unsigned int die,unsigned int cpu)372 int topology_update_die_map(unsigned int die, unsigned int cpu)
373 {
374 int new;
375
376 /* Already available somewhere? */
377 new = topology_phys_to_logical_die(die, cpu);
378 if (new >= 0)
379 goto found;
380
381 new = logical_die++;
382 if (new != die) {
383 pr_info("CPU %u Converting physical %u to logical die %u\n",
384 cpu, die, new);
385 }
386 found:
387 cpu_data(cpu).logical_die_id = new;
388 return 0;
389 }
390
smp_store_boot_cpu_info(void)391 void __init smp_store_boot_cpu_info(void)
392 {
393 int id = 0; /* CPU 0 */
394 struct cpuinfo_x86 *c = &cpu_data(id);
395
396 *c = boot_cpu_data;
397 c->cpu_index = id;
398 topology_update_package_map(c->phys_proc_id, id);
399 topology_update_die_map(c->cpu_die_id, id);
400 c->initialized = true;
401 }
402
403 /*
404 * The bootstrap kernel entry code has set these up. Save them for
405 * a given CPU
406 */
smp_store_cpu_info(int id)407 void smp_store_cpu_info(int id)
408 {
409 struct cpuinfo_x86 *c = &cpu_data(id);
410
411 /* Copy boot_cpu_data only on the first bringup */
412 if (!c->initialized)
413 *c = boot_cpu_data;
414 c->cpu_index = id;
415 /*
416 * During boot time, CPU0 has this setup already. Save the info when
417 * bringing up AP or offlined CPU0.
418 */
419 identify_secondary_cpu(c);
420 c->initialized = true;
421 }
422
423 static bool
topology_same_node(struct cpuinfo_x86 * c,struct cpuinfo_x86 * o)424 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
425 {
426 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
427
428 return (cpu_to_node(cpu1) == cpu_to_node(cpu2));
429 }
430
431 static bool
topology_sane(struct cpuinfo_x86 * c,struct cpuinfo_x86 * o,const char * name)432 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
433 {
434 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
435
436 return !WARN_ONCE(!topology_same_node(c, o),
437 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
438 "[node: %d != %d]. Ignoring dependency.\n",
439 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
440 }
441
442 #define link_mask(mfunc, c1, c2) \
443 do { \
444 cpumask_set_cpu((c1), mfunc(c2)); \
445 cpumask_set_cpu((c2), mfunc(c1)); \
446 } while (0)
447
match_smt(struct cpuinfo_x86 * c,struct cpuinfo_x86 * o)448 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
449 {
450 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
451 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
452
453 if (c->phys_proc_id == o->phys_proc_id &&
454 c->cpu_die_id == o->cpu_die_id &&
455 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) {
456 if (c->cpu_core_id == o->cpu_core_id)
457 return topology_sane(c, o, "smt");
458
459 if ((c->cu_id != 0xff) &&
460 (o->cu_id != 0xff) &&
461 (c->cu_id == o->cu_id))
462 return topology_sane(c, o, "smt");
463 }
464
465 } else if (c->phys_proc_id == o->phys_proc_id &&
466 c->cpu_die_id == o->cpu_die_id &&
467 c->cpu_core_id == o->cpu_core_id) {
468 return topology_sane(c, o, "smt");
469 }
470
471 return false;
472 }
473
474 /*
475 * Define snc_cpu[] for SNC (Sub-NUMA Cluster) CPUs.
476 *
477 * These are Intel CPUs that enumerate an LLC that is shared by
478 * multiple NUMA nodes. The LLC on these systems is shared for
479 * off-package data access but private to the NUMA node (half
480 * of the package) for on-package access.
481 *
482 * CPUID (the source of the information about the LLC) can only
483 * enumerate the cache as being shared *or* unshared, but not
484 * this particular configuration. The CPU in this case enumerates
485 * the cache to be shared across the entire package (spanning both
486 * NUMA nodes).
487 */
488
489 static const struct x86_cpu_id snc_cpu[] = {
490 { X86_VENDOR_INTEL, 6, INTEL_FAM6_SKYLAKE_X },
491 {}
492 };
493
match_llc(struct cpuinfo_x86 * c,struct cpuinfo_x86 * o)494 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
495 {
496 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
497
498 /* Do not match if we do not have a valid APICID for cpu: */
499 if (per_cpu(cpu_llc_id, cpu1) == BAD_APICID)
500 return false;
501
502 /* Do not match if LLC id does not match: */
503 if (per_cpu(cpu_llc_id, cpu1) != per_cpu(cpu_llc_id, cpu2))
504 return false;
505
506 /*
507 * Allow the SNC topology without warning. Return of false
508 * means 'c' does not share the LLC of 'o'. This will be
509 * reflected to userspace.
510 */
511 if (!topology_same_node(c, o) && x86_match_cpu(snc_cpu))
512 return false;
513
514 return topology_sane(c, o, "llc");
515 }
516
517 /*
518 * Unlike the other levels, we do not enforce keeping a
519 * multicore group inside a NUMA node. If this happens, we will
520 * discard the MC level of the topology later.
521 */
match_pkg(struct cpuinfo_x86 * c,struct cpuinfo_x86 * o)522 static bool match_pkg(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
523 {
524 if (c->phys_proc_id == o->phys_proc_id)
525 return true;
526 return false;
527 }
528
match_die(struct cpuinfo_x86 * c,struct cpuinfo_x86 * o)529 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
530 {
531 if ((c->phys_proc_id == o->phys_proc_id) &&
532 (c->cpu_die_id == o->cpu_die_id))
533 return true;
534 return false;
535 }
536
537
538 #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_MC)
x86_sched_itmt_flags(void)539 static inline int x86_sched_itmt_flags(void)
540 {
541 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0;
542 }
543
544 #ifdef CONFIG_SCHED_MC
x86_core_flags(void)545 static int x86_core_flags(void)
546 {
547 return cpu_core_flags() | x86_sched_itmt_flags();
548 }
549 #endif
550 #ifdef CONFIG_SCHED_SMT
x86_smt_flags(void)551 static int x86_smt_flags(void)
552 {
553 return cpu_smt_flags() | x86_sched_itmt_flags();
554 }
555 #endif
556 #endif
557
558 static struct sched_domain_topology_level x86_numa_in_package_topology[] = {
559 #ifdef CONFIG_SCHED_SMT
560 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
561 #endif
562 #ifdef CONFIG_SCHED_MC
563 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
564 #endif
565 { NULL, },
566 };
567
568 static struct sched_domain_topology_level x86_topology[] = {
569 #ifdef CONFIG_SCHED_SMT
570 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
571 #endif
572 #ifdef CONFIG_SCHED_MC
573 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
574 #endif
575 { cpu_cpu_mask, SD_INIT_NAME(DIE) },
576 { NULL, },
577 };
578
579 /*
580 * Set if a package/die has multiple NUMA nodes inside.
581 * AMD Magny-Cours, Intel Cluster-on-Die, and Intel
582 * Sub-NUMA Clustering have this.
583 */
584 static bool x86_has_numa_in_package;
585
set_cpu_sibling_map(int cpu)586 void set_cpu_sibling_map(int cpu)
587 {
588 bool has_smt = smp_num_siblings > 1;
589 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1;
590 struct cpuinfo_x86 *c = &cpu_data(cpu);
591 struct cpuinfo_x86 *o;
592 int i, threads;
593
594 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
595
596 if (!has_mp) {
597 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu));
598 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
599 cpumask_set_cpu(cpu, topology_core_cpumask(cpu));
600 cpumask_set_cpu(cpu, topology_die_cpumask(cpu));
601 c->booted_cores = 1;
602 return;
603 }
604
605 for_each_cpu(i, cpu_sibling_setup_mask) {
606 o = &cpu_data(i);
607
608 if ((i == cpu) || (has_smt && match_smt(c, o)))
609 link_mask(topology_sibling_cpumask, cpu, i);
610
611 if ((i == cpu) || (has_mp && match_llc(c, o)))
612 link_mask(cpu_llc_shared_mask, cpu, i);
613
614 }
615
616 /*
617 * This needs a separate iteration over the cpus because we rely on all
618 * topology_sibling_cpumask links to be set-up.
619 */
620 for_each_cpu(i, cpu_sibling_setup_mask) {
621 o = &cpu_data(i);
622
623 if ((i == cpu) || (has_mp && match_pkg(c, o))) {
624 link_mask(topology_core_cpumask, cpu, i);
625
626 /*
627 * Does this new cpu bringup a new core?
628 */
629 if (cpumask_weight(
630 topology_sibling_cpumask(cpu)) == 1) {
631 /*
632 * for each core in package, increment
633 * the booted_cores for this new cpu
634 */
635 if (cpumask_first(
636 topology_sibling_cpumask(i)) == i)
637 c->booted_cores++;
638 /*
639 * increment the core count for all
640 * the other cpus in this package
641 */
642 if (i != cpu)
643 cpu_data(i).booted_cores++;
644 } else if (i != cpu && !c->booted_cores)
645 c->booted_cores = cpu_data(i).booted_cores;
646 }
647 if (match_pkg(c, o) && !topology_same_node(c, o))
648 x86_has_numa_in_package = true;
649
650 if ((i == cpu) || (has_mp && match_die(c, o)))
651 link_mask(topology_die_cpumask, cpu, i);
652 }
653
654 threads = cpumask_weight(topology_sibling_cpumask(cpu));
655 if (threads > __max_smt_threads)
656 __max_smt_threads = threads;
657 }
658
659 /* maps the cpu to the sched domain representing multi-core */
cpu_coregroup_mask(int cpu)660 const struct cpumask *cpu_coregroup_mask(int cpu)
661 {
662 return cpu_llc_shared_mask(cpu);
663 }
664
impress_friends(void)665 static void impress_friends(void)
666 {
667 int cpu;
668 unsigned long bogosum = 0;
669 /*
670 * Allow the user to impress friends.
671 */
672 pr_debug("Before bogomips\n");
673 for_each_possible_cpu(cpu)
674 if (cpumask_test_cpu(cpu, cpu_callout_mask))
675 bogosum += cpu_data(cpu).loops_per_jiffy;
676 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
677 num_online_cpus(),
678 bogosum/(500000/HZ),
679 (bogosum/(5000/HZ))%100);
680
681 pr_debug("Before bogocount - setting activated=1\n");
682 }
683
__inquire_remote_apic(int apicid)684 void __inquire_remote_apic(int apicid)
685 {
686 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
687 const char * const names[] = { "ID", "VERSION", "SPIV" };
688 int timeout;
689 u32 status;
690
691 pr_info("Inquiring remote APIC 0x%x...\n", apicid);
692
693 for (i = 0; i < ARRAY_SIZE(regs); i++) {
694 pr_info("... APIC 0x%x %s: ", apicid, names[i]);
695
696 /*
697 * Wait for idle.
698 */
699 status = safe_apic_wait_icr_idle();
700 if (status)
701 pr_cont("a previous APIC delivery may have failed\n");
702
703 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
704
705 timeout = 0;
706 do {
707 udelay(100);
708 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
709 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
710
711 switch (status) {
712 case APIC_ICR_RR_VALID:
713 status = apic_read(APIC_RRR);
714 pr_cont("%08x\n", status);
715 break;
716 default:
717 pr_cont("failed\n");
718 }
719 }
720 }
721
722 /*
723 * The Multiprocessor Specification 1.4 (1997) example code suggests
724 * that there should be a 10ms delay between the BSP asserting INIT
725 * and de-asserting INIT, when starting a remote processor.
726 * But that slows boot and resume on modern processors, which include
727 * many cores and don't require that delay.
728 *
729 * Cmdline "init_cpu_udelay=" is available to over-ride this delay.
730 * Modern processor families are quirked to remove the delay entirely.
731 */
732 #define UDELAY_10MS_DEFAULT 10000
733
734 static unsigned int init_udelay = UINT_MAX;
735
cpu_init_udelay(char * str)736 static int __init cpu_init_udelay(char *str)
737 {
738 get_option(&str, &init_udelay);
739
740 return 0;
741 }
742 early_param("cpu_init_udelay", cpu_init_udelay);
743
smp_quirk_init_udelay(void)744 static void __init smp_quirk_init_udelay(void)
745 {
746 /* if cmdline changed it from default, leave it alone */
747 if (init_udelay != UINT_MAX)
748 return;
749
750 /* if modern processor, use no delay */
751 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) ||
752 ((boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) && (boot_cpu_data.x86 >= 0x18)) ||
753 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) {
754 init_udelay = 0;
755 return;
756 }
757 /* else, use legacy delay */
758 init_udelay = UDELAY_10MS_DEFAULT;
759 }
760
761 /*
762 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
763 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
764 * won't ... remember to clear down the APIC, etc later.
765 */
766 int
wakeup_secondary_cpu_via_nmi(int apicid,unsigned long start_eip)767 wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip)
768 {
769 unsigned long send_status, accept_status = 0;
770 int maxlvt;
771
772 /* Target chip */
773 /* Boot on the stack */
774 /* Kick the second */
775 apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid);
776
777 pr_debug("Waiting for send to finish...\n");
778 send_status = safe_apic_wait_icr_idle();
779
780 /*
781 * Give the other CPU some time to accept the IPI.
782 */
783 udelay(200);
784 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
785 maxlvt = lapic_get_maxlvt();
786 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
787 apic_write(APIC_ESR, 0);
788 accept_status = (apic_read(APIC_ESR) & 0xEF);
789 }
790 pr_debug("NMI sent\n");
791
792 if (send_status)
793 pr_err("APIC never delivered???\n");
794 if (accept_status)
795 pr_err("APIC delivery error (%lx)\n", accept_status);
796
797 return (send_status | accept_status);
798 }
799
800 static int
wakeup_secondary_cpu_via_init(int phys_apicid,unsigned long start_eip)801 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
802 {
803 unsigned long send_status = 0, accept_status = 0;
804 int maxlvt, num_starts, j;
805
806 maxlvt = lapic_get_maxlvt();
807
808 /*
809 * Be paranoid about clearing APIC errors.
810 */
811 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
812 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
813 apic_write(APIC_ESR, 0);
814 apic_read(APIC_ESR);
815 }
816
817 pr_debug("Asserting INIT\n");
818
819 /*
820 * Turn INIT on target chip
821 */
822 /*
823 * Send IPI
824 */
825 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
826 phys_apicid);
827
828 pr_debug("Waiting for send to finish...\n");
829 send_status = safe_apic_wait_icr_idle();
830
831 udelay(init_udelay);
832
833 pr_debug("Deasserting INIT\n");
834
835 /* Target chip */
836 /* Send IPI */
837 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
838
839 pr_debug("Waiting for send to finish...\n");
840 send_status = safe_apic_wait_icr_idle();
841
842 mb();
843
844 /*
845 * Should we send STARTUP IPIs ?
846 *
847 * Determine this based on the APIC version.
848 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
849 */
850 if (APIC_INTEGRATED(boot_cpu_apic_version))
851 num_starts = 2;
852 else
853 num_starts = 0;
854
855 /*
856 * Run STARTUP IPI loop.
857 */
858 pr_debug("#startup loops: %d\n", num_starts);
859
860 for (j = 1; j <= num_starts; j++) {
861 pr_debug("Sending STARTUP #%d\n", j);
862 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
863 apic_write(APIC_ESR, 0);
864 apic_read(APIC_ESR);
865 pr_debug("After apic_write\n");
866
867 /*
868 * STARTUP IPI
869 */
870
871 /* Target chip */
872 /* Boot on the stack */
873 /* Kick the second */
874 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
875 phys_apicid);
876
877 /*
878 * Give the other CPU some time to accept the IPI.
879 */
880 if (init_udelay == 0)
881 udelay(10);
882 else
883 udelay(300);
884
885 pr_debug("Startup point 1\n");
886
887 pr_debug("Waiting for send to finish...\n");
888 send_status = safe_apic_wait_icr_idle();
889
890 /*
891 * Give the other CPU some time to accept the IPI.
892 */
893 if (init_udelay == 0)
894 udelay(10);
895 else
896 udelay(200);
897
898 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
899 apic_write(APIC_ESR, 0);
900 accept_status = (apic_read(APIC_ESR) & 0xEF);
901 if (send_status || accept_status)
902 break;
903 }
904 pr_debug("After Startup\n");
905
906 if (send_status)
907 pr_err("APIC never delivered???\n");
908 if (accept_status)
909 pr_err("APIC delivery error (%lx)\n", accept_status);
910
911 return (send_status | accept_status);
912 }
913
914 /* reduce the number of lines printed when booting a large cpu count system */
announce_cpu(int cpu,int apicid)915 static void announce_cpu(int cpu, int apicid)
916 {
917 static int current_node = NUMA_NO_NODE;
918 int node = early_cpu_to_node(cpu);
919 static int width, node_width;
920
921 if (!width)
922 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */
923
924 if (!node_width)
925 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */
926
927 if (cpu == 1)
928 printk(KERN_INFO "x86: Booting SMP configuration:\n");
929
930 if (system_state < SYSTEM_RUNNING) {
931 if (node != current_node) {
932 if (current_node > (-1))
933 pr_cont("\n");
934 current_node = node;
935
936 printk(KERN_INFO ".... node %*s#%d, CPUs: ",
937 node_width - num_digits(node), " ", node);
938 }
939
940 /* Add padding for the BSP */
941 if (cpu == 1)
942 pr_cont("%*s", width + 1, " ");
943
944 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu);
945
946 } else
947 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
948 node, cpu, apicid);
949 }
950
wakeup_cpu0_nmi(unsigned int cmd,struct pt_regs * regs)951 static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs)
952 {
953 int cpu;
954
955 cpu = smp_processor_id();
956 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0)
957 return NMI_HANDLED;
958
959 return NMI_DONE;
960 }
961
962 /*
963 * Wake up AP by INIT, INIT, STARTUP sequence.
964 *
965 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
966 * boot-strap code which is not a desired behavior for waking up BSP. To
967 * void the boot-strap code, wake up CPU0 by NMI instead.
968 *
969 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
970 * (i.e. physically hot removed and then hot added), NMI won't wake it up.
971 * We'll change this code in the future to wake up hard offlined CPU0 if
972 * real platform and request are available.
973 */
974 static int
wakeup_cpu_via_init_nmi(int cpu,unsigned long start_ip,int apicid,int * cpu0_nmi_registered)975 wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid,
976 int *cpu0_nmi_registered)
977 {
978 int id;
979 int boot_error;
980
981 preempt_disable();
982
983 /*
984 * Wake up AP by INIT, INIT, STARTUP sequence.
985 */
986 if (cpu) {
987 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
988 goto out;
989 }
990
991 /*
992 * Wake up BSP by nmi.
993 *
994 * Register a NMI handler to help wake up CPU0.
995 */
996 boot_error = register_nmi_handler(NMI_LOCAL,
997 wakeup_cpu0_nmi, 0, "wake_cpu0");
998
999 if (!boot_error) {
1000 enable_start_cpu0 = 1;
1001 *cpu0_nmi_registered = 1;
1002 if (apic->dest_logical == APIC_DEST_LOGICAL)
1003 id = cpu0_logical_apicid;
1004 else
1005 id = apicid;
1006 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip);
1007 }
1008
1009 out:
1010 preempt_enable();
1011
1012 return boot_error;
1013 }
1014
common_cpu_up(unsigned int cpu,struct task_struct * idle)1015 int common_cpu_up(unsigned int cpu, struct task_struct *idle)
1016 {
1017 int ret;
1018
1019 /* Just in case we booted with a single CPU. */
1020 alternatives_enable_smp();
1021
1022 per_cpu(current_task, cpu) = idle;
1023
1024 /* Initialize the interrupt stack(s) */
1025 ret = irq_init_percpu_irqstack(cpu);
1026 if (ret)
1027 return ret;
1028
1029 #ifdef CONFIG_X86_32
1030 /* Stack for startup_32 can be just as for start_secondary onwards */
1031 per_cpu(cpu_current_top_of_stack, cpu) = task_top_of_stack(idle);
1032 #else
1033 initial_gs = per_cpu_offset(cpu);
1034 #endif
1035 return 0;
1036 }
1037
1038 /*
1039 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
1040 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
1041 * Returns zero if CPU booted OK, else error code from
1042 * ->wakeup_secondary_cpu.
1043 */
do_boot_cpu(int apicid,int cpu,struct task_struct * idle,int * cpu0_nmi_registered)1044 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle,
1045 int *cpu0_nmi_registered)
1046 {
1047 /* start_ip had better be page-aligned! */
1048 unsigned long start_ip = real_mode_header->trampoline_start;
1049
1050 unsigned long boot_error = 0;
1051 unsigned long timeout;
1052
1053 idle->thread.sp = (unsigned long)task_pt_regs(idle);
1054 early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu);
1055 initial_code = (unsigned long)start_secondary;
1056 initial_stack = idle->thread.sp;
1057
1058 /* Enable the espfix hack for this CPU */
1059 init_espfix_ap(cpu);
1060
1061 /* So we see what's up */
1062 announce_cpu(cpu, apicid);
1063
1064 /*
1065 * This grunge runs the startup process for
1066 * the targeted processor.
1067 */
1068
1069 if (x86_platform.legacy.warm_reset) {
1070
1071 pr_debug("Setting warm reset code and vector.\n");
1072
1073 smpboot_setup_warm_reset_vector(start_ip);
1074 /*
1075 * Be paranoid about clearing APIC errors.
1076 */
1077 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
1078 apic_write(APIC_ESR, 0);
1079 apic_read(APIC_ESR);
1080 }
1081 }
1082
1083 /*
1084 * AP might wait on cpu_callout_mask in cpu_init() with
1085 * cpu_initialized_mask set if previous attempt to online
1086 * it timed-out. Clear cpu_initialized_mask so that after
1087 * INIT/SIPI it could start with a clean state.
1088 */
1089 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1090 smp_mb();
1091
1092 /*
1093 * Wake up a CPU in difference cases:
1094 * - Use the method in the APIC driver if it's defined
1095 * Otherwise,
1096 * - Use an INIT boot APIC message for APs or NMI for BSP.
1097 */
1098 if (apic->wakeup_secondary_cpu)
1099 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
1100 else
1101 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid,
1102 cpu0_nmi_registered);
1103
1104 if (!boot_error) {
1105 /*
1106 * Wait 10s total for first sign of life from AP
1107 */
1108 boot_error = -1;
1109 timeout = jiffies + 10*HZ;
1110 while (time_before(jiffies, timeout)) {
1111 if (cpumask_test_cpu(cpu, cpu_initialized_mask)) {
1112 /*
1113 * Tell AP to proceed with initialization
1114 */
1115 cpumask_set_cpu(cpu, cpu_callout_mask);
1116 boot_error = 0;
1117 break;
1118 }
1119 schedule();
1120 }
1121 }
1122
1123 if (!boot_error) {
1124 /*
1125 * Wait till AP completes initial initialization
1126 */
1127 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) {
1128 /*
1129 * Allow other tasks to run while we wait for the
1130 * AP to come online. This also gives a chance
1131 * for the MTRR work(triggered by the AP coming online)
1132 * to be completed in the stop machine context.
1133 */
1134 schedule();
1135 }
1136 }
1137
1138 if (x86_platform.legacy.warm_reset) {
1139 /*
1140 * Cleanup possible dangling ends...
1141 */
1142 smpboot_restore_warm_reset_vector();
1143 }
1144
1145 return boot_error;
1146 }
1147
native_cpu_up(unsigned int cpu,struct task_struct * tidle)1148 int native_cpu_up(unsigned int cpu, struct task_struct *tidle)
1149 {
1150 int apicid = apic->cpu_present_to_apicid(cpu);
1151 int cpu0_nmi_registered = 0;
1152 unsigned long flags;
1153 int err, ret = 0;
1154
1155 lockdep_assert_irqs_enabled();
1156
1157 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
1158
1159 if (apicid == BAD_APICID ||
1160 !physid_isset(apicid, phys_cpu_present_map) ||
1161 !apic->apic_id_valid(apicid)) {
1162 pr_err("%s: bad cpu %d\n", __func__, cpu);
1163 return -EINVAL;
1164 }
1165
1166 /*
1167 * Already booted CPU?
1168 */
1169 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
1170 pr_debug("do_boot_cpu %d Already started\n", cpu);
1171 return -ENOSYS;
1172 }
1173
1174 /*
1175 * Save current MTRR state in case it was changed since early boot
1176 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
1177 */
1178 mtrr_save_state();
1179
1180 /* x86 CPUs take themselves offline, so delayed offline is OK. */
1181 err = cpu_check_up_prepare(cpu);
1182 if (err && err != -EBUSY)
1183 return err;
1184
1185 /* the FPU context is blank, nobody can own it */
1186 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL;
1187
1188 err = common_cpu_up(cpu, tidle);
1189 if (err)
1190 return err;
1191
1192 err = do_boot_cpu(apicid, cpu, tidle, &cpu0_nmi_registered);
1193 if (err) {
1194 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu);
1195 ret = -EIO;
1196 goto unreg_nmi;
1197 }
1198
1199 /*
1200 * Check TSC synchronization with the AP (keep irqs disabled
1201 * while doing so):
1202 */
1203 local_irq_save(flags);
1204 check_tsc_sync_source(cpu);
1205 local_irq_restore(flags);
1206
1207 while (!cpu_online(cpu)) {
1208 cpu_relax();
1209 touch_nmi_watchdog();
1210 }
1211
1212 unreg_nmi:
1213 /*
1214 * Clean up the nmi handler. Do this after the callin and callout sync
1215 * to avoid impact of possible long unregister time.
1216 */
1217 if (cpu0_nmi_registered)
1218 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0");
1219
1220 return ret;
1221 }
1222
1223 /**
1224 * arch_disable_smp_support() - disables SMP support for x86 at runtime
1225 */
arch_disable_smp_support(void)1226 void arch_disable_smp_support(void)
1227 {
1228 disable_ioapic_support();
1229 }
1230
1231 /*
1232 * Fall back to non SMP mode after errors.
1233 *
1234 * RED-PEN audit/test this more. I bet there is more state messed up here.
1235 */
disable_smp(void)1236 static __init void disable_smp(void)
1237 {
1238 pr_info("SMP disabled\n");
1239
1240 disable_ioapic_support();
1241
1242 init_cpu_present(cpumask_of(0));
1243 init_cpu_possible(cpumask_of(0));
1244
1245 if (smp_found_config)
1246 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1247 else
1248 physid_set_mask_of_physid(0, &phys_cpu_present_map);
1249 cpumask_set_cpu(0, topology_sibling_cpumask(0));
1250 cpumask_set_cpu(0, topology_core_cpumask(0));
1251 cpumask_set_cpu(0, topology_die_cpumask(0));
1252 }
1253
1254 /*
1255 * Various sanity checks.
1256 */
smp_sanity_check(void)1257 static void __init smp_sanity_check(void)
1258 {
1259 preempt_disable();
1260
1261 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
1262 if (def_to_bigsmp && nr_cpu_ids > 8) {
1263 unsigned int cpu;
1264 unsigned nr;
1265
1266 pr_warn("More than 8 CPUs detected - skipping them\n"
1267 "Use CONFIG_X86_BIGSMP\n");
1268
1269 nr = 0;
1270 for_each_present_cpu(cpu) {
1271 if (nr >= 8)
1272 set_cpu_present(cpu, false);
1273 nr++;
1274 }
1275
1276 nr = 0;
1277 for_each_possible_cpu(cpu) {
1278 if (nr >= 8)
1279 set_cpu_possible(cpu, false);
1280 nr++;
1281 }
1282
1283 nr_cpu_ids = 8;
1284 }
1285 #endif
1286
1287 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
1288 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
1289 hard_smp_processor_id());
1290
1291 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1292 }
1293
1294 /*
1295 * Should not be necessary because the MP table should list the boot
1296 * CPU too, but we do it for the sake of robustness anyway.
1297 */
1298 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
1299 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
1300 boot_cpu_physical_apicid);
1301 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1302 }
1303 preempt_enable();
1304 }
1305
smp_cpu_index_default(void)1306 static void __init smp_cpu_index_default(void)
1307 {
1308 int i;
1309 struct cpuinfo_x86 *c;
1310
1311 for_each_possible_cpu(i) {
1312 c = &cpu_data(i);
1313 /* mark all to hotplug */
1314 c->cpu_index = nr_cpu_ids;
1315 }
1316 }
1317
smp_get_logical_apicid(void)1318 static void __init smp_get_logical_apicid(void)
1319 {
1320 if (x2apic_mode)
1321 cpu0_logical_apicid = apic_read(APIC_LDR);
1322 else
1323 cpu0_logical_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
1324 }
1325
1326 /*
1327 * Prepare for SMP bootup.
1328 * @max_cpus: configured maximum number of CPUs, It is a legacy parameter
1329 * for common interface support.
1330 */
native_smp_prepare_cpus(unsigned int max_cpus)1331 void __init native_smp_prepare_cpus(unsigned int max_cpus)
1332 {
1333 unsigned int i;
1334
1335 smp_cpu_index_default();
1336
1337 /*
1338 * Setup boot CPU information
1339 */
1340 smp_store_boot_cpu_info(); /* Final full version of the data */
1341 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1342 mb();
1343
1344 for_each_possible_cpu(i) {
1345 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1346 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1347 zalloc_cpumask_var(&per_cpu(cpu_die_map, i), GFP_KERNEL);
1348 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1349 }
1350
1351 /*
1352 * Set 'default' x86 topology, this matches default_topology() in that
1353 * it has NUMA nodes as a topology level. See also
1354 * native_smp_cpus_done().
1355 *
1356 * Must be done before set_cpus_sibling_map() is ran.
1357 */
1358 set_sched_topology(x86_topology);
1359
1360 set_cpu_sibling_map(0);
1361
1362 smp_sanity_check();
1363
1364 switch (apic_intr_mode) {
1365 case APIC_PIC:
1366 case APIC_VIRTUAL_WIRE_NO_CONFIG:
1367 disable_smp();
1368 return;
1369 case APIC_SYMMETRIC_IO_NO_ROUTING:
1370 disable_smp();
1371 /* Setup local timer */
1372 x86_init.timers.setup_percpu_clockev();
1373 return;
1374 case APIC_VIRTUAL_WIRE:
1375 case APIC_SYMMETRIC_IO:
1376 break;
1377 }
1378
1379 /* Setup local timer */
1380 x86_init.timers.setup_percpu_clockev();
1381
1382 smp_get_logical_apicid();
1383
1384 pr_info("CPU0: ");
1385 print_cpu_info(&cpu_data(0));
1386
1387 uv_system_init();
1388
1389 set_mtrr_aps_delayed_init();
1390
1391 smp_quirk_init_udelay();
1392
1393 speculative_store_bypass_ht_init();
1394 }
1395
arch_enable_nonboot_cpus_begin(void)1396 void arch_enable_nonboot_cpus_begin(void)
1397 {
1398 set_mtrr_aps_delayed_init();
1399 }
1400
arch_enable_nonboot_cpus_end(void)1401 void arch_enable_nonboot_cpus_end(void)
1402 {
1403 mtrr_aps_init();
1404 }
1405
1406 /*
1407 * Early setup to make printk work.
1408 */
native_smp_prepare_boot_cpu(void)1409 void __init native_smp_prepare_boot_cpu(void)
1410 {
1411 int me = smp_processor_id();
1412 switch_to_new_gdt(me);
1413 /* already set me in cpu_online_mask in boot_cpu_init() */
1414 cpumask_set_cpu(me, cpu_callout_mask);
1415 cpu_set_state_online(me);
1416 native_pv_lock_init();
1417 }
1418
calculate_max_logical_packages(void)1419 void __init calculate_max_logical_packages(void)
1420 {
1421 int ncpus;
1422
1423 /*
1424 * Today neither Intel nor AMD support heterogenous systems so
1425 * extrapolate the boot cpu's data to all packages.
1426 */
1427 ncpus = cpu_data(0).booted_cores * topology_max_smt_threads();
1428 __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus);
1429 pr_info("Max logical packages: %u\n", __max_logical_packages);
1430 }
1431
native_smp_cpus_done(unsigned int max_cpus)1432 void __init native_smp_cpus_done(unsigned int max_cpus)
1433 {
1434 pr_debug("Boot done\n");
1435
1436 calculate_max_logical_packages();
1437
1438 if (x86_has_numa_in_package)
1439 set_sched_topology(x86_numa_in_package_topology);
1440
1441 nmi_selftest();
1442 impress_friends();
1443 mtrr_aps_init();
1444 }
1445
1446 static int __initdata setup_possible_cpus = -1;
_setup_possible_cpus(char * str)1447 static int __init _setup_possible_cpus(char *str)
1448 {
1449 get_option(&str, &setup_possible_cpus);
1450 return 0;
1451 }
1452 early_param("possible_cpus", _setup_possible_cpus);
1453
1454
1455 /*
1456 * cpu_possible_mask should be static, it cannot change as cpu's
1457 * are onlined, or offlined. The reason is per-cpu data-structures
1458 * are allocated by some modules at init time, and dont expect to
1459 * do this dynamically on cpu arrival/departure.
1460 * cpu_present_mask on the other hand can change dynamically.
1461 * In case when cpu_hotplug is not compiled, then we resort to current
1462 * behaviour, which is cpu_possible == cpu_present.
1463 * - Ashok Raj
1464 *
1465 * Three ways to find out the number of additional hotplug CPUs:
1466 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1467 * - The user can overwrite it with possible_cpus=NUM
1468 * - Otherwise don't reserve additional CPUs.
1469 * We do this because additional CPUs waste a lot of memory.
1470 * -AK
1471 */
prefill_possible_map(void)1472 __init void prefill_possible_map(void)
1473 {
1474 int i, possible;
1475
1476 /* No boot processor was found in mptable or ACPI MADT */
1477 if (!num_processors) {
1478 if (boot_cpu_has(X86_FEATURE_APIC)) {
1479 int apicid = boot_cpu_physical_apicid;
1480 int cpu = hard_smp_processor_id();
1481
1482 pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu);
1483
1484 /* Make sure boot cpu is enumerated */
1485 if (apic->cpu_present_to_apicid(0) == BAD_APICID &&
1486 apic->apic_id_valid(apicid))
1487 generic_processor_info(apicid, boot_cpu_apic_version);
1488 }
1489
1490 if (!num_processors)
1491 num_processors = 1;
1492 }
1493
1494 i = setup_max_cpus ?: 1;
1495 if (setup_possible_cpus == -1) {
1496 possible = num_processors;
1497 #ifdef CONFIG_HOTPLUG_CPU
1498 if (setup_max_cpus)
1499 possible += disabled_cpus;
1500 #else
1501 if (possible > i)
1502 possible = i;
1503 #endif
1504 } else
1505 possible = setup_possible_cpus;
1506
1507 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1508
1509 /* nr_cpu_ids could be reduced via nr_cpus= */
1510 if (possible > nr_cpu_ids) {
1511 pr_warn("%d Processors exceeds NR_CPUS limit of %u\n",
1512 possible, nr_cpu_ids);
1513 possible = nr_cpu_ids;
1514 }
1515
1516 #ifdef CONFIG_HOTPLUG_CPU
1517 if (!setup_max_cpus)
1518 #endif
1519 if (possible > i) {
1520 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1521 possible, setup_max_cpus);
1522 possible = i;
1523 }
1524
1525 nr_cpu_ids = possible;
1526
1527 pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1528 possible, max_t(int, possible - num_processors, 0));
1529
1530 reset_cpu_possible_mask();
1531
1532 for (i = 0; i < possible; i++)
1533 set_cpu_possible(i, true);
1534 }
1535
1536 #ifdef CONFIG_HOTPLUG_CPU
1537
1538 /* Recompute SMT state for all CPUs on offline */
recompute_smt_state(void)1539 static void recompute_smt_state(void)
1540 {
1541 int max_threads, cpu;
1542
1543 max_threads = 0;
1544 for_each_online_cpu (cpu) {
1545 int threads = cpumask_weight(topology_sibling_cpumask(cpu));
1546
1547 if (threads > max_threads)
1548 max_threads = threads;
1549 }
1550 __max_smt_threads = max_threads;
1551 }
1552
remove_siblinginfo(int cpu)1553 static void remove_siblinginfo(int cpu)
1554 {
1555 int sibling;
1556 struct cpuinfo_x86 *c = &cpu_data(cpu);
1557
1558 for_each_cpu(sibling, topology_core_cpumask(cpu)) {
1559 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling));
1560 /*/
1561 * last thread sibling in this cpu core going down
1562 */
1563 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1)
1564 cpu_data(sibling).booted_cores--;
1565 }
1566
1567 for_each_cpu(sibling, topology_die_cpumask(cpu))
1568 cpumask_clear_cpu(cpu, topology_die_cpumask(sibling));
1569 for_each_cpu(sibling, topology_sibling_cpumask(cpu))
1570 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling));
1571 for_each_cpu(sibling, cpu_llc_shared_mask(cpu))
1572 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling));
1573 cpumask_clear(cpu_llc_shared_mask(cpu));
1574 cpumask_clear(topology_sibling_cpumask(cpu));
1575 cpumask_clear(topology_core_cpumask(cpu));
1576 cpumask_clear(topology_die_cpumask(cpu));
1577 c->cpu_core_id = 0;
1578 c->booted_cores = 0;
1579 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1580 recompute_smt_state();
1581 }
1582
remove_cpu_from_maps(int cpu)1583 static void remove_cpu_from_maps(int cpu)
1584 {
1585 set_cpu_online(cpu, false);
1586 cpumask_clear_cpu(cpu, cpu_callout_mask);
1587 cpumask_clear_cpu(cpu, cpu_callin_mask);
1588 /* was set by cpu_init() */
1589 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1590 numa_remove_cpu(cpu);
1591 }
1592
cpu_disable_common(void)1593 void cpu_disable_common(void)
1594 {
1595 int cpu = smp_processor_id();
1596
1597 remove_siblinginfo(cpu);
1598
1599 /* It's now safe to remove this processor from the online map */
1600 lock_vector_lock();
1601 remove_cpu_from_maps(cpu);
1602 unlock_vector_lock();
1603 fixup_irqs();
1604 lapic_offline();
1605 }
1606
native_cpu_disable(void)1607 int native_cpu_disable(void)
1608 {
1609 int ret;
1610
1611 ret = lapic_can_unplug_cpu();
1612 if (ret)
1613 return ret;
1614
1615 cpu_disable_common();
1616
1617 /*
1618 * Disable the local APIC. Otherwise IPI broadcasts will reach
1619 * it. It still responds normally to INIT, NMI, SMI, and SIPI
1620 * messages.
1621 *
1622 * Disabling the APIC must happen after cpu_disable_common()
1623 * which invokes fixup_irqs().
1624 *
1625 * Disabling the APIC preserves already set bits in IRR, but
1626 * an interrupt arriving after disabling the local APIC does not
1627 * set the corresponding IRR bit.
1628 *
1629 * fixup_irqs() scans IRR for set bits so it can raise a not
1630 * yet handled interrupt on the new destination CPU via an IPI
1631 * but obviously it can't do so for IRR bits which are not set.
1632 * IOW, interrupts arriving after disabling the local APIC will
1633 * be lost.
1634 */
1635 apic_soft_disable();
1636
1637 return 0;
1638 }
1639
common_cpu_die(unsigned int cpu)1640 int common_cpu_die(unsigned int cpu)
1641 {
1642 int ret = 0;
1643
1644 /* We don't do anything here: idle task is faking death itself. */
1645
1646 /* They ack this in play_dead() by setting CPU_DEAD */
1647 if (cpu_wait_death(cpu, 5)) {
1648 if (system_state == SYSTEM_RUNNING)
1649 pr_info("CPU %u is now offline\n", cpu);
1650 } else {
1651 pr_err("CPU %u didn't die...\n", cpu);
1652 ret = -1;
1653 }
1654
1655 return ret;
1656 }
1657
native_cpu_die(unsigned int cpu)1658 void native_cpu_die(unsigned int cpu)
1659 {
1660 common_cpu_die(cpu);
1661 }
1662
play_dead_common(void)1663 void play_dead_common(void)
1664 {
1665 idle_task_exit();
1666
1667 /* Ack it */
1668 (void)cpu_report_death();
1669
1670 /*
1671 * With physical CPU hotplug, we should halt the cpu
1672 */
1673 local_irq_disable();
1674 }
1675
wakeup_cpu0(void)1676 static bool wakeup_cpu0(void)
1677 {
1678 if (smp_processor_id() == 0 && enable_start_cpu0)
1679 return true;
1680
1681 return false;
1682 }
1683
1684 /*
1685 * We need to flush the caches before going to sleep, lest we have
1686 * dirty data in our caches when we come back up.
1687 */
mwait_play_dead(void)1688 static inline void mwait_play_dead(void)
1689 {
1690 struct mwait_cpu_dead *md = this_cpu_ptr(&mwait_cpu_dead);
1691 unsigned int eax, ebx, ecx, edx;
1692 unsigned int highest_cstate = 0;
1693 unsigned int highest_subcstate = 0;
1694 int i;
1695
1696 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
1697 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
1698 return;
1699 if (!this_cpu_has(X86_FEATURE_MWAIT))
1700 return;
1701 if (!this_cpu_has(X86_FEATURE_CLFLUSH))
1702 return;
1703 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1704 return;
1705
1706 eax = CPUID_MWAIT_LEAF;
1707 ecx = 0;
1708 native_cpuid(&eax, &ebx, &ecx, &edx);
1709
1710 /*
1711 * eax will be 0 if EDX enumeration is not valid.
1712 * Initialized below to cstate, sub_cstate value when EDX is valid.
1713 */
1714 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1715 eax = 0;
1716 } else {
1717 edx >>= MWAIT_SUBSTATE_SIZE;
1718 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1719 if (edx & MWAIT_SUBSTATE_MASK) {
1720 highest_cstate = i;
1721 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1722 }
1723 }
1724 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1725 (highest_subcstate - 1);
1726 }
1727
1728 wbinvd();
1729
1730 while (1) {
1731 /*
1732 * The CLFLUSH is a workaround for erratum AAI65 for
1733 * the Xeon 7400 series. It's not clear it is actually
1734 * needed, but it should be harmless in either case.
1735 * The WBINVD is insufficient due to the spurious-wakeup
1736 * case where we return around the loop.
1737 */
1738 mb();
1739 clflush(md);
1740 mb();
1741 __monitor(md, 0, 0);
1742 mb();
1743 __mwait(eax, 0);
1744 /*
1745 * If NMI wants to wake up CPU0, start CPU0.
1746 */
1747 if (wakeup_cpu0())
1748 start_cpu0();
1749 }
1750 }
1751
hlt_play_dead(void)1752 void hlt_play_dead(void)
1753 {
1754 if (__this_cpu_read(cpu_info.x86) >= 4)
1755 wbinvd();
1756
1757 while (1) {
1758 native_halt();
1759 /*
1760 * If NMI wants to wake up CPU0, start CPU0.
1761 */
1762 if (wakeup_cpu0())
1763 start_cpu0();
1764 }
1765 }
1766
native_play_dead(void)1767 void native_play_dead(void)
1768 {
1769 play_dead_common();
1770 tboot_shutdown(TB_SHUTDOWN_WFS);
1771
1772 mwait_play_dead(); /* Only returns on failure */
1773 if (cpuidle_play_dead())
1774 hlt_play_dead();
1775 }
1776
1777 #else /* ... !CONFIG_HOTPLUG_CPU */
native_cpu_disable(void)1778 int native_cpu_disable(void)
1779 {
1780 return -ENOSYS;
1781 }
1782
native_cpu_die(unsigned int cpu)1783 void native_cpu_die(unsigned int cpu)
1784 {
1785 /* We said "no" in __cpu_disable */
1786 BUG();
1787 }
1788
native_play_dead(void)1789 void native_play_dead(void)
1790 {
1791 BUG();
1792 }
1793
1794 #endif
1795