1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2003, 2004 Ralf Baechle 7 * Copyright (C) 2004 Maciej W. Rozycki 8 */ 9 #ifndef __ASM_CPU_FEATURES_H 10 #define __ASM_CPU_FEATURES_H 11 12 #include <asm/cpu.h> 13 #include <asm/cpu-info.h> 14 #include <asm/isa-rev.h> 15 #include <cpu-feature-overrides.h> 16 17 #define __ase(ase) (cpu_data[0].ases & (ase)) 18 #define __isa(isa) (cpu_data[0].isa_level & (isa)) 19 #define __opt(opt) (cpu_data[0].options & (opt)) 20 21 /* 22 * Check if MIPS_ISA_REV is >= isa *and* an option or ASE is detected during 23 * boot (typically by cpu_probe()). 24 * 25 * Note that these should only be used in cases where a kernel built for an 26 * older ISA *cannot* run on a CPU which supports the feature in question. For 27 * example this may be used for features introduced with MIPSr6, since a kernel 28 * built for an older ISA cannot run on a MIPSr6 CPU. This should not be used 29 * for MIPSr2 features however, since a MIPSr1 or earlier kernel might run on a 30 * MIPSr2 CPU. 31 */ 32 #define __isa_ge_and_ase(isa, ase) ((MIPS_ISA_REV >= (isa)) && __ase(ase)) 33 #define __isa_ge_and_opt(isa, opt) ((MIPS_ISA_REV >= (isa)) && __opt(opt)) 34 35 /* 36 * Check if MIPS_ISA_REV is >= isa *or* an option or ASE is detected during 37 * boot (typically by cpu_probe()). 38 * 39 * These are for use with features that are optional up until a particular ISA 40 * revision & then become required. 41 */ 42 #define __isa_ge_or_ase(isa, ase) ((MIPS_ISA_REV >= (isa)) || __ase(ase)) 43 #define __isa_ge_or_opt(isa, opt) ((MIPS_ISA_REV >= (isa)) || __opt(opt)) 44 45 /* 46 * Check if MIPS_ISA_REV is < isa *and* an option or ASE is detected during 47 * boot (typically by cpu_probe()). 48 * 49 * These are for use with features that are optional up until a particular ISA 50 * revision & are then removed - ie. no longer present in any CPU implementing 51 * the given ISA revision. 52 */ 53 #define __isa_lt_and_ase(isa, ase) ((MIPS_ISA_REV < (isa)) && __ase(ase)) 54 #define __isa_lt_and_opt(isa, opt) ((MIPS_ISA_REV < (isa)) && __opt(opt)) 55 56 /* 57 * Similarly allow for ISA level checks that take into account knowledge of the 58 * ISA targeted by the kernel build, provided by MIPS_ISA_REV. 59 */ 60 #define __isa_ge_and_flag(isa, flag) ((MIPS_ISA_REV >= (isa)) && __isa(flag)) 61 #define __isa_ge_or_flag(isa, flag) ((MIPS_ISA_REV >= (isa)) || __isa(flag)) 62 #define __isa_lt_and_flag(isa, flag) ((MIPS_ISA_REV < (isa)) && __isa(flag)) 63 #define __isa_range(ge, lt) \ 64 ((MIPS_ISA_REV >= (ge)) && (MIPS_ISA_REV < (lt))) 65 #define __isa_range_or_flag(ge, lt, flag) \ 66 (__isa_range(ge, lt) || ((MIPS_ISA_REV < (lt)) && __isa(flag))) 67 68 /* 69 * SMP assumption: Options of CPU 0 are a superset of all processors. 70 * This is true for all known MIPS systems. 71 */ 72 #ifndef cpu_has_tlb 73 #define cpu_has_tlb __opt(MIPS_CPU_TLB) 74 #endif 75 #ifndef cpu_has_ftlb 76 #define cpu_has_ftlb __opt(MIPS_CPU_FTLB) 77 #endif 78 #ifndef cpu_has_tlbinv 79 #define cpu_has_tlbinv __opt(MIPS_CPU_TLBINV) 80 #endif 81 #ifndef cpu_has_segments 82 #define cpu_has_segments __opt(MIPS_CPU_SEGMENTS) 83 #endif 84 #ifndef cpu_has_eva 85 #define cpu_has_eva __opt(MIPS_CPU_EVA) 86 #endif 87 #ifndef cpu_has_htw 88 #define cpu_has_htw __opt(MIPS_CPU_HTW) 89 #endif 90 #ifndef cpu_has_ldpte 91 #define cpu_has_ldpte __opt(MIPS_CPU_LDPTE) 92 #endif 93 #ifndef cpu_has_rixiex 94 #define cpu_has_rixiex __isa_ge_or_opt(6, MIPS_CPU_RIXIEX) 95 #endif 96 #ifndef cpu_has_maar 97 #define cpu_has_maar __opt(MIPS_CPU_MAAR) 98 #endif 99 #ifndef cpu_has_rw_llb 100 #define cpu_has_rw_llb __isa_ge_or_opt(6, MIPS_CPU_RW_LLB) 101 #endif 102 103 /* 104 * For the moment we don't consider R6000 and R8000 so we can assume that 105 * anything that doesn't support R4000-style exceptions and interrupts is 106 * R3000-like. Users should still treat these two macro definitions as 107 * opaque. 108 */ 109 #ifndef cpu_has_3kex 110 #define cpu_has_3kex (!cpu_has_4kex) 111 #endif 112 #ifndef cpu_has_4kex 113 #define cpu_has_4kex __isa_ge_or_opt(1, MIPS_CPU_4KEX) 114 #endif 115 #ifndef cpu_has_3k_cache 116 #define cpu_has_3k_cache __isa_lt_and_opt(1, MIPS_CPU_3K_CACHE) 117 #endif 118 #define cpu_has_6k_cache 0 119 #define cpu_has_8k_cache 0 120 #ifndef cpu_has_4k_cache 121 #define cpu_has_4k_cache __isa_ge_or_opt(1, MIPS_CPU_4K_CACHE) 122 #endif 123 #ifndef cpu_has_tx39_cache 124 #define cpu_has_tx39_cache __opt(MIPS_CPU_TX39_CACHE) 125 #endif 126 #ifndef cpu_has_octeon_cache 127 #define cpu_has_octeon_cache \ 128 ({ \ 129 int __res; \ 130 \ 131 switch (boot_cpu_type()) { \ 132 case CPU_CAVIUM_OCTEON: \ 133 case CPU_CAVIUM_OCTEON_PLUS: \ 134 case CPU_CAVIUM_OCTEON2: \ 135 case CPU_CAVIUM_OCTEON3: \ 136 __res = 1; \ 137 break; \ 138 \ 139 default: \ 140 __res = 0; \ 141 } \ 142 \ 143 __res; \ 144 }) 145 #endif 146 /* Don't override `cpu_has_fpu' to 1 or the "nofpu" option won't work. */ 147 #ifndef cpu_has_fpu 148 # ifdef CONFIG_MIPS_FP_SUPPORT 149 # define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU) 150 # define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU) 151 # else 152 # define cpu_has_fpu 0 153 # define raw_cpu_has_fpu 0 154 # endif 155 #else 156 # define raw_cpu_has_fpu cpu_has_fpu 157 #endif 158 #ifndef cpu_has_32fpr 159 #define cpu_has_32fpr __isa_ge_or_opt(1, MIPS_CPU_32FPR) 160 #endif 161 #ifndef cpu_has_counter 162 #define cpu_has_counter __opt(MIPS_CPU_COUNTER) 163 #endif 164 #ifndef cpu_has_watch 165 #define cpu_has_watch __opt(MIPS_CPU_WATCH) 166 #endif 167 #ifndef cpu_has_divec 168 #define cpu_has_divec __isa_ge_or_opt(1, MIPS_CPU_DIVEC) 169 #endif 170 #ifndef cpu_has_vce 171 #define cpu_has_vce __opt(MIPS_CPU_VCE) 172 #endif 173 #ifndef cpu_has_cache_cdex_p 174 #define cpu_has_cache_cdex_p __opt(MIPS_CPU_CACHE_CDEX_P) 175 #endif 176 #ifndef cpu_has_cache_cdex_s 177 #define cpu_has_cache_cdex_s __opt(MIPS_CPU_CACHE_CDEX_S) 178 #endif 179 #ifndef cpu_has_prefetch 180 #define cpu_has_prefetch __isa_ge_or_opt(1, MIPS_CPU_PREFETCH) 181 #endif 182 #ifndef cpu_has_mcheck 183 #define cpu_has_mcheck __isa_ge_or_opt(1, MIPS_CPU_MCHECK) 184 #endif 185 #ifndef cpu_has_ejtag 186 #define cpu_has_ejtag __opt(MIPS_CPU_EJTAG) 187 #endif 188 #ifndef cpu_has_llsc 189 #define cpu_has_llsc __isa_ge_or_opt(1, MIPS_CPU_LLSC) 190 #endif 191 #ifndef cpu_has_bp_ghist 192 #define cpu_has_bp_ghist __opt(MIPS_CPU_BP_GHIST) 193 #endif 194 #ifndef kernel_uses_llsc 195 #define kernel_uses_llsc cpu_has_llsc 196 #endif 197 #ifndef cpu_has_guestctl0ext 198 #define cpu_has_guestctl0ext __opt(MIPS_CPU_GUESTCTL0EXT) 199 #endif 200 #ifndef cpu_has_guestctl1 201 #define cpu_has_guestctl1 __opt(MIPS_CPU_GUESTCTL1) 202 #endif 203 #ifndef cpu_has_guestctl2 204 #define cpu_has_guestctl2 __opt(MIPS_CPU_GUESTCTL2) 205 #endif 206 #ifndef cpu_has_guestid 207 #define cpu_has_guestid __opt(MIPS_CPU_GUESTID) 208 #endif 209 #ifndef cpu_has_drg 210 #define cpu_has_drg __opt(MIPS_CPU_DRG) 211 #endif 212 #ifndef cpu_has_mips16 213 #define cpu_has_mips16 __isa_lt_and_ase(6, MIPS_ASE_MIPS16) 214 #endif 215 #ifndef cpu_has_mips16e2 216 #define cpu_has_mips16e2 __isa_lt_and_ase(6, MIPS_ASE_MIPS16E2) 217 #endif 218 #ifndef cpu_has_mdmx 219 #define cpu_has_mdmx __isa_lt_and_ase(6, MIPS_ASE_MDMX) 220 #endif 221 #ifndef cpu_has_mips3d 222 #define cpu_has_mips3d __isa_lt_and_ase(6, MIPS_ASE_MIPS3D) 223 #endif 224 #ifndef cpu_has_smartmips 225 #define cpu_has_smartmips __isa_lt_and_ase(6, MIPS_ASE_SMARTMIPS) 226 #endif 227 228 #ifndef cpu_has_rixi 229 #define cpu_has_rixi __isa_ge_or_opt(6, MIPS_CPU_RIXI) 230 #endif 231 232 #ifndef cpu_has_mmips 233 # if defined(__mips_micromips) 234 # define cpu_has_mmips 1 235 # elif defined(CONFIG_SYS_SUPPORTS_MICROMIPS) 236 # define cpu_has_mmips __opt(MIPS_CPU_MICROMIPS) 237 # else 238 # define cpu_has_mmips 0 239 # endif 240 #endif 241 242 #ifndef cpu_has_lpa 243 #define cpu_has_lpa __opt(MIPS_CPU_LPA) 244 #endif 245 #ifndef cpu_has_mvh 246 #define cpu_has_mvh __opt(MIPS_CPU_MVH) 247 #endif 248 #ifndef cpu_has_xpa 249 #define cpu_has_xpa (cpu_has_lpa && cpu_has_mvh) 250 #endif 251 #ifndef cpu_has_vtag_icache 252 #define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG) 253 #endif 254 #ifndef cpu_has_dc_aliases 255 #define cpu_has_dc_aliases (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES) 256 #endif 257 #ifndef cpu_has_ic_fills_f_dc 258 #define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC) 259 #endif 260 #ifndef cpu_has_pindexed_dcache 261 #define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX) 262 #endif 263 264 /* 265 * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors 266 * such as the R10000 have I-Caches that snoop local stores; the embedded ones 267 * don't. For maintaining I-cache coherency this means we need to flush the 268 * D-cache all the way back to whever the I-cache does refills from, so the 269 * I-cache has a chance to see the new data at all. Then we have to flush the 270 * I-cache also. 271 * Note we may have been rescheduled and may no longer be running on the CPU 272 * that did the store so we can't optimize this into only doing the flush on 273 * the local CPU. 274 */ 275 #ifndef cpu_icache_snoops_remote_store 276 #ifdef CONFIG_SMP 277 #define cpu_icache_snoops_remote_store (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE) 278 #else 279 #define cpu_icache_snoops_remote_store 1 280 #endif 281 #endif 282 283 #ifndef cpu_has_mips_1 284 # define cpu_has_mips_1 (MIPS_ISA_REV < 6) 285 #endif 286 #ifndef cpu_has_mips_2 287 # define cpu_has_mips_2 __isa_lt_and_flag(6, MIPS_CPU_ISA_II) 288 #endif 289 #ifndef cpu_has_mips_3 290 # define cpu_has_mips_3 __isa_lt_and_flag(6, MIPS_CPU_ISA_III) 291 #endif 292 #ifndef cpu_has_mips_4 293 # define cpu_has_mips_4 __isa_lt_and_flag(6, MIPS_CPU_ISA_IV) 294 #endif 295 #ifndef cpu_has_mips_5 296 # define cpu_has_mips_5 __isa_lt_and_flag(6, MIPS_CPU_ISA_V) 297 #endif 298 #ifndef cpu_has_mips32r1 299 # define cpu_has_mips32r1 __isa_range_or_flag(1, 6, MIPS_CPU_ISA_M32R1) 300 #endif 301 #ifndef cpu_has_mips32r2 302 # define cpu_has_mips32r2 __isa_range_or_flag(2, 6, MIPS_CPU_ISA_M32R2) 303 #endif 304 #ifndef cpu_has_mips32r6 305 # define cpu_has_mips32r6 __isa_ge_or_flag(6, MIPS_CPU_ISA_M32R6) 306 #endif 307 #ifndef cpu_has_mips64r1 308 # define cpu_has_mips64r1 (cpu_has_64bits && \ 309 __isa_range_or_flag(1, 6, MIPS_CPU_ISA_M64R1)) 310 #endif 311 #ifndef cpu_has_mips64r2 312 # define cpu_has_mips64r2 (cpu_has_64bits && \ 313 __isa_range_or_flag(2, 6, MIPS_CPU_ISA_M64R2)) 314 #endif 315 #ifndef cpu_has_mips64r6 316 # define cpu_has_mips64r6 __isa_ge_and_flag(6, MIPS_CPU_ISA_M64R6) 317 #endif 318 319 /* 320 * Shortcuts ... 321 */ 322 #define cpu_has_mips_2_3_4_5 (cpu_has_mips_2 | cpu_has_mips_3_4_5) 323 #define cpu_has_mips_3_4_5 (cpu_has_mips_3 | cpu_has_mips_4_5) 324 #define cpu_has_mips_4_5 (cpu_has_mips_4 | cpu_has_mips_5) 325 326 #define cpu_has_mips_2_3_4_5_r (cpu_has_mips_2 | cpu_has_mips_3_4_5_r) 327 #define cpu_has_mips_3_4_5_r (cpu_has_mips_3 | cpu_has_mips_4_5_r) 328 #define cpu_has_mips_4_5_r (cpu_has_mips_4 | cpu_has_mips_5_r) 329 #define cpu_has_mips_5_r (cpu_has_mips_5 | cpu_has_mips_r) 330 331 #define cpu_has_mips_3_4_5_64_r2_r6 \ 332 (cpu_has_mips_3 | cpu_has_mips_4_5_64_r2_r6) 333 #define cpu_has_mips_4_5_64_r2_r6 \ 334 (cpu_has_mips_4_5 | cpu_has_mips64r1 | \ 335 cpu_has_mips_r2 | cpu_has_mips_r6) 336 337 #define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2 | cpu_has_mips32r6) 338 #define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2 | cpu_has_mips64r6) 339 #define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1) 340 #define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2) 341 #define cpu_has_mips_r6 (cpu_has_mips32r6 | cpu_has_mips64r6) 342 #define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \ 343 cpu_has_mips32r6 | cpu_has_mips64r1 | \ 344 cpu_has_mips64r2 | cpu_has_mips64r6) 345 346 /* MIPSR2 and MIPSR6 have a lot of similarities */ 347 #define cpu_has_mips_r2_r6 (cpu_has_mips_r2 | cpu_has_mips_r6) 348 349 /* 350 * cpu_has_mips_r2_exec_hazard - return if IHB is required on current processor 351 * 352 * Returns non-zero value if the current processor implementation requires 353 * an IHB instruction to deal with an instruction hazard as per MIPS R2 354 * architecture specification, zero otherwise. 355 */ 356 #ifndef cpu_has_mips_r2_exec_hazard 357 #define cpu_has_mips_r2_exec_hazard \ 358 ({ \ 359 int __res; \ 360 \ 361 switch (boot_cpu_type()) { \ 362 case CPU_M14KC: \ 363 case CPU_74K: \ 364 case CPU_1074K: \ 365 case CPU_PROAPTIV: \ 366 case CPU_P5600: \ 367 case CPU_M5150: \ 368 case CPU_QEMU_GENERIC: \ 369 case CPU_CAVIUM_OCTEON: \ 370 case CPU_CAVIUM_OCTEON_PLUS: \ 371 case CPU_CAVIUM_OCTEON2: \ 372 case CPU_CAVIUM_OCTEON3: \ 373 __res = 0; \ 374 break; \ 375 \ 376 default: \ 377 __res = 1; \ 378 } \ 379 \ 380 __res; \ 381 }) 382 #endif 383 384 /* 385 * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other 386 * pre-MIPS32/MIPS64 processors have CLO, CLZ. The IDT RC64574 is 64-bit and 387 * has CLO and CLZ but not DCLO nor DCLZ. For 64-bit kernels 388 * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ. 389 */ 390 #ifndef cpu_has_clo_clz 391 #define cpu_has_clo_clz cpu_has_mips_r 392 #endif 393 394 /* 395 * MIPS32 R2, MIPS64 R2, Loongson 3A and Octeon have WSBH. 396 * MIPS64 R2, Loongson 3A and Octeon have WSBH, DSBH and DSHD. 397 * This indicates the availability of WSBH and in case of 64 bit CPUs also 398 * DSBH and DSHD. 399 */ 400 #ifndef cpu_has_wsbh 401 #define cpu_has_wsbh cpu_has_mips_r2 402 #endif 403 404 #ifndef cpu_has_dsp 405 #define cpu_has_dsp __ase(MIPS_ASE_DSP) 406 #endif 407 408 #ifndef cpu_has_dsp2 409 #define cpu_has_dsp2 __ase(MIPS_ASE_DSP2P) 410 #endif 411 412 #ifndef cpu_has_dsp3 413 #define cpu_has_dsp3 __ase(MIPS_ASE_DSP3) 414 #endif 415 416 #ifndef cpu_has_loongson_mmi 417 #define cpu_has_loongson_mmi __ase(MIPS_ASE_LOONGSON_MMI) 418 #endif 419 420 #ifndef cpu_has_loongson_cam 421 #define cpu_has_loongson_cam __ase(MIPS_ASE_LOONGSON_CAM) 422 #endif 423 424 #ifndef cpu_has_loongson_ext 425 #define cpu_has_loongson_ext __ase(MIPS_ASE_LOONGSON_EXT) 426 #endif 427 428 #ifndef cpu_has_loongson_ext2 429 #define cpu_has_loongson_ext2 __ase(MIPS_ASE_LOONGSON_EXT2) 430 #endif 431 432 #ifndef cpu_has_mipsmt 433 #define cpu_has_mipsmt __isa_lt_and_ase(6, MIPS_ASE_MIPSMT) 434 #endif 435 436 #ifndef cpu_has_vp 437 #define cpu_has_vp __isa_ge_and_opt(6, MIPS_CPU_VP) 438 #endif 439 440 #ifndef cpu_has_userlocal 441 #define cpu_has_userlocal __isa_ge_or_opt(6, MIPS_CPU_ULRI) 442 #endif 443 444 #ifdef CONFIG_32BIT 445 # ifndef cpu_has_nofpuex 446 # define cpu_has_nofpuex __isa_lt_and_opt(1, MIPS_CPU_NOFPUEX) 447 # endif 448 # ifndef cpu_has_64bits 449 # define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT) 450 # endif 451 # ifndef cpu_has_64bit_zero_reg 452 # define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT) 453 # endif 454 # ifndef cpu_has_64bit_gp_regs 455 # define cpu_has_64bit_gp_regs 0 456 # endif 457 # ifndef cpu_has_64bit_addresses 458 # define cpu_has_64bit_addresses 0 459 # endif 460 # ifndef cpu_vmbits 461 # define cpu_vmbits 31 462 # endif 463 #endif 464 465 #ifdef CONFIG_64BIT 466 # ifndef cpu_has_nofpuex 467 # define cpu_has_nofpuex 0 468 # endif 469 # ifndef cpu_has_64bits 470 # define cpu_has_64bits 1 471 # endif 472 # ifndef cpu_has_64bit_zero_reg 473 # define cpu_has_64bit_zero_reg 1 474 # endif 475 # ifndef cpu_has_64bit_gp_regs 476 # define cpu_has_64bit_gp_regs 1 477 # endif 478 # ifndef cpu_has_64bit_addresses 479 # define cpu_has_64bit_addresses 1 480 # endif 481 # ifndef cpu_vmbits 482 # define cpu_vmbits cpu_data[0].vmbits 483 # define __NEED_VMBITS_PROBE 484 # endif 485 #endif 486 487 #if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint) 488 # define cpu_has_vint __opt(MIPS_CPU_VINT) 489 #elif !defined(cpu_has_vint) 490 # define cpu_has_vint 0 491 #endif 492 493 #if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic) 494 # define cpu_has_veic __opt(MIPS_CPU_VEIC) 495 #elif !defined(cpu_has_veic) 496 # define cpu_has_veic 0 497 #endif 498 499 #ifndef cpu_has_inclusive_pcaches 500 #define cpu_has_inclusive_pcaches __opt(MIPS_CPU_INCLUSIVE_CACHES) 501 #endif 502 503 #ifndef cpu_dcache_line_size 504 #define cpu_dcache_line_size() cpu_data[0].dcache.linesz 505 #endif 506 #ifndef cpu_icache_line_size 507 #define cpu_icache_line_size() cpu_data[0].icache.linesz 508 #endif 509 #ifndef cpu_scache_line_size 510 #define cpu_scache_line_size() cpu_data[0].scache.linesz 511 #endif 512 #ifndef cpu_tcache_line_size 513 #define cpu_tcache_line_size() cpu_data[0].tcache.linesz 514 #endif 515 516 #ifndef cpu_hwrena_impl_bits 517 #define cpu_hwrena_impl_bits 0 518 #endif 519 520 #ifndef cpu_has_perf_cntr_intr_bit 521 #define cpu_has_perf_cntr_intr_bit __opt(MIPS_CPU_PCI) 522 #endif 523 524 #ifndef cpu_has_vz 525 #define cpu_has_vz __ase(MIPS_ASE_VZ) 526 #endif 527 528 #if defined(CONFIG_CPU_HAS_MSA) && !defined(cpu_has_msa) 529 # define cpu_has_msa __ase(MIPS_ASE_MSA) 530 #elif !defined(cpu_has_msa) 531 # define cpu_has_msa 0 532 #endif 533 534 #ifndef cpu_has_ufr 535 # define cpu_has_ufr __opt(MIPS_CPU_UFR) 536 #endif 537 538 #ifndef cpu_has_fre 539 # define cpu_has_fre __opt(MIPS_CPU_FRE) 540 #endif 541 542 #ifndef cpu_has_cdmm 543 # define cpu_has_cdmm __opt(MIPS_CPU_CDMM) 544 #endif 545 546 #ifndef cpu_has_small_pages 547 # define cpu_has_small_pages __opt(MIPS_CPU_SP) 548 #endif 549 550 #ifndef cpu_has_nan_legacy 551 #define cpu_has_nan_legacy __isa_lt_and_opt(6, MIPS_CPU_NAN_LEGACY) 552 #endif 553 #ifndef cpu_has_nan_2008 554 #define cpu_has_nan_2008 __isa_ge_or_opt(6, MIPS_CPU_NAN_2008) 555 #endif 556 557 #ifndef cpu_has_ebase_wg 558 # define cpu_has_ebase_wg __opt(MIPS_CPU_EBASE_WG) 559 #endif 560 561 #ifndef cpu_has_badinstr 562 # define cpu_has_badinstr __isa_ge_or_opt(6, MIPS_CPU_BADINSTR) 563 #endif 564 565 #ifndef cpu_has_badinstrp 566 # define cpu_has_badinstrp __isa_ge_or_opt(6, MIPS_CPU_BADINSTRP) 567 #endif 568 569 #ifndef cpu_has_contextconfig 570 # define cpu_has_contextconfig __opt(MIPS_CPU_CTXTC) 571 #endif 572 573 #ifndef cpu_has_perf 574 # define cpu_has_perf __opt(MIPS_CPU_PERF) 575 #endif 576 577 #ifdef CONFIG_SMP 578 /* 579 * Some systems share FTLB RAMs between threads within a core (siblings in 580 * kernel parlance). This means that FTLB entries may become invalid at almost 581 * any point when an entry is evicted due to a sibling thread writing an entry 582 * to the shared FTLB RAM. 583 * 584 * This is only relevant to SMP systems, and the only systems that exhibit this 585 * property implement MIPSr6 or higher so we constrain support for this to 586 * kernels that will run on such systems. 587 */ 588 # ifndef cpu_has_shared_ftlb_ram 589 # define cpu_has_shared_ftlb_ram \ 590 __isa_ge_and_opt(6, MIPS_CPU_SHARED_FTLB_RAM) 591 # endif 592 593 /* 594 * Some systems take this a step further & share FTLB entries between siblings. 595 * This is implemented as TLB writes happening as usual, but if an entry 596 * written by a sibling exists in the shared FTLB for a translation which would 597 * otherwise cause a TLB refill exception then the CPU will use the entry 598 * written by its sibling rather than triggering a refill & writing a matching 599 * TLB entry for itself. 600 * 601 * This is naturally only valid if a TLB entry is known to be suitable for use 602 * on all siblings in a CPU, and so it only takes effect when MMIDs are in use 603 * rather than ASIDs or when a TLB entry is marked global. 604 */ 605 # ifndef cpu_has_shared_ftlb_entries 606 # define cpu_has_shared_ftlb_entries \ 607 __isa_ge_and_opt(6, MIPS_CPU_SHARED_FTLB_ENTRIES) 608 # endif 609 #endif /* SMP */ 610 611 #ifndef cpu_has_shared_ftlb_ram 612 # define cpu_has_shared_ftlb_ram 0 613 #endif 614 #ifndef cpu_has_shared_ftlb_entries 615 # define cpu_has_shared_ftlb_entries 0 616 #endif 617 618 #ifdef CONFIG_MIPS_MT_SMP 619 # define cpu_has_mipsmt_pertccounters \ 620 __isa_lt_and_opt(6, MIPS_CPU_MT_PER_TC_PERF_COUNTERS) 621 #else 622 # define cpu_has_mipsmt_pertccounters 0 623 #endif /* CONFIG_MIPS_MT_SMP */ 624 625 /* 626 * We only enable MMID support for configurations which natively support 64 bit 627 * atomics because getting good performance from the allocator relies upon 628 * efficient atomic64_*() functions. 629 */ 630 #ifndef cpu_has_mmid 631 # ifdef CONFIG_GENERIC_ATOMIC64 632 # define cpu_has_mmid 0 633 # else 634 # define cpu_has_mmid __isa_ge_and_opt(6, MIPS_CPU_MMID) 635 # endif 636 #endif 637 638 /* 639 * Guest capabilities 640 */ 641 #ifndef cpu_guest_has_conf1 642 #define cpu_guest_has_conf1 (cpu_data[0].guest.conf & (1 << 1)) 643 #endif 644 #ifndef cpu_guest_has_conf2 645 #define cpu_guest_has_conf2 (cpu_data[0].guest.conf & (1 << 2)) 646 #endif 647 #ifndef cpu_guest_has_conf3 648 #define cpu_guest_has_conf3 (cpu_data[0].guest.conf & (1 << 3)) 649 #endif 650 #ifndef cpu_guest_has_conf4 651 #define cpu_guest_has_conf4 (cpu_data[0].guest.conf & (1 << 4)) 652 #endif 653 #ifndef cpu_guest_has_conf5 654 #define cpu_guest_has_conf5 (cpu_data[0].guest.conf & (1 << 5)) 655 #endif 656 #ifndef cpu_guest_has_conf6 657 #define cpu_guest_has_conf6 (cpu_data[0].guest.conf & (1 << 6)) 658 #endif 659 #ifndef cpu_guest_has_conf7 660 #define cpu_guest_has_conf7 (cpu_data[0].guest.conf & (1 << 7)) 661 #endif 662 #ifndef cpu_guest_has_fpu 663 #define cpu_guest_has_fpu (cpu_data[0].guest.options & MIPS_CPU_FPU) 664 #endif 665 #ifndef cpu_guest_has_watch 666 #define cpu_guest_has_watch (cpu_data[0].guest.options & MIPS_CPU_WATCH) 667 #endif 668 #ifndef cpu_guest_has_contextconfig 669 #define cpu_guest_has_contextconfig (cpu_data[0].guest.options & MIPS_CPU_CTXTC) 670 #endif 671 #ifndef cpu_guest_has_segments 672 #define cpu_guest_has_segments (cpu_data[0].guest.options & MIPS_CPU_SEGMENTS) 673 #endif 674 #ifndef cpu_guest_has_badinstr 675 #define cpu_guest_has_badinstr (cpu_data[0].guest.options & MIPS_CPU_BADINSTR) 676 #endif 677 #ifndef cpu_guest_has_badinstrp 678 #define cpu_guest_has_badinstrp (cpu_data[0].guest.options & MIPS_CPU_BADINSTRP) 679 #endif 680 #ifndef cpu_guest_has_htw 681 #define cpu_guest_has_htw (cpu_data[0].guest.options & MIPS_CPU_HTW) 682 #endif 683 #ifndef cpu_guest_has_mvh 684 #define cpu_guest_has_mvh (cpu_data[0].guest.options & MIPS_CPU_MVH) 685 #endif 686 #ifndef cpu_guest_has_msa 687 #define cpu_guest_has_msa (cpu_data[0].guest.ases & MIPS_ASE_MSA) 688 #endif 689 #ifndef cpu_guest_has_kscr 690 #define cpu_guest_has_kscr(n) (cpu_data[0].guest.kscratch_mask & (1u << (n))) 691 #endif 692 #ifndef cpu_guest_has_rw_llb 693 #define cpu_guest_has_rw_llb (cpu_has_mips_r6 || (cpu_data[0].guest.options & MIPS_CPU_RW_LLB)) 694 #endif 695 #ifndef cpu_guest_has_perf 696 #define cpu_guest_has_perf (cpu_data[0].guest.options & MIPS_CPU_PERF) 697 #endif 698 #ifndef cpu_guest_has_maar 699 #define cpu_guest_has_maar (cpu_data[0].guest.options & MIPS_CPU_MAAR) 700 #endif 701 #ifndef cpu_guest_has_userlocal 702 #define cpu_guest_has_userlocal (cpu_data[0].guest.options & MIPS_CPU_ULRI) 703 #endif 704 705 /* 706 * Guest dynamic capabilities 707 */ 708 #ifndef cpu_guest_has_dyn_fpu 709 #define cpu_guest_has_dyn_fpu (cpu_data[0].guest.options_dyn & MIPS_CPU_FPU) 710 #endif 711 #ifndef cpu_guest_has_dyn_watch 712 #define cpu_guest_has_dyn_watch (cpu_data[0].guest.options_dyn & MIPS_CPU_WATCH) 713 #endif 714 #ifndef cpu_guest_has_dyn_contextconfig 715 #define cpu_guest_has_dyn_contextconfig (cpu_data[0].guest.options_dyn & MIPS_CPU_CTXTC) 716 #endif 717 #ifndef cpu_guest_has_dyn_perf 718 #define cpu_guest_has_dyn_perf (cpu_data[0].guest.options_dyn & MIPS_CPU_PERF) 719 #endif 720 #ifndef cpu_guest_has_dyn_msa 721 #define cpu_guest_has_dyn_msa (cpu_data[0].guest.ases_dyn & MIPS_ASE_MSA) 722 #endif 723 #ifndef cpu_guest_has_dyn_maar 724 #define cpu_guest_has_dyn_maar (cpu_data[0].guest.options_dyn & MIPS_CPU_MAAR) 725 #endif 726 727 #endif /* __ASM_CPU_FEATURES_H */ 728