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1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Contains CPU feature definitions
4  *
5  * Copyright (C) 2015 ARM Ltd.
6  */
7 
8 #define pr_fmt(fmt) "CPU features: " fmt
9 
10 #include <linux/bsearch.h>
11 #include <linux/cpumask.h>
12 #include <linux/crash_dump.h>
13 #include <linux/percpu.h>
14 #include <linux/sort.h>
15 #include <linux/stop_machine.h>
16 #include <linux/types.h>
17 #include <linux/mm.h>
18 #include <linux/cpu.h>
19 
20 #include <asm/cpu.h>
21 #include <asm/cpufeature.h>
22 #include <asm/cpu_ops.h>
23 #include <asm/fpsimd.h>
24 #include <asm/hwcap.h>
25 #include <asm/mmu_context.h>
26 #include <asm/processor.h>
27 #include <asm/sysreg.h>
28 #include <asm/traps.h>
29 #include <asm/vectors.h>
30 #include <asm/virt.h>
31 
32 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */
33 static unsigned long elf_hwcap __read_mostly;
34 
35 #ifdef CONFIG_COMPAT
36 #define COMPAT_ELF_HWCAP_DEFAULT	\
37 				(COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
38 				 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
39 				 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\
40 				 COMPAT_HWCAP_LPAE)
41 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
42 unsigned int compat_elf_hwcap2 __read_mostly;
43 #endif
44 
45 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
46 EXPORT_SYMBOL(cpu_hwcaps);
47 static struct arm64_cpu_capabilities const __ro_after_init *cpu_hwcaps_ptrs[ARM64_NCAPS];
48 
49 /* Need also bit for ARM64_CB_PATCH */
50 DECLARE_BITMAP(boot_capabilities, ARM64_NPATCHABLE);
51 
52 DEFINE_PER_CPU_READ_MOSTLY(const char *, this_cpu_vector) = vectors;
53 
54 /*
55  * Flag to indicate if we have computed the system wide
56  * capabilities based on the boot time active CPUs. This
57  * will be used to determine if a new booting CPU should
58  * go through the verification process to make sure that it
59  * supports the system capabilities, without using a hotplug
60  * notifier.
61  */
62 static bool sys_caps_initialised;
63 
set_sys_caps_initialised(void)64 static inline void set_sys_caps_initialised(void)
65 {
66 	sys_caps_initialised = true;
67 }
68 
dump_cpu_hwcaps(struct notifier_block * self,unsigned long v,void * p)69 static int dump_cpu_hwcaps(struct notifier_block *self, unsigned long v, void *p)
70 {
71 	/* file-wide pr_fmt adds "CPU features: " prefix */
72 	pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps);
73 	return 0;
74 }
75 
76 static struct notifier_block cpu_hwcaps_notifier = {
77 	.notifier_call = dump_cpu_hwcaps
78 };
79 
register_cpu_hwcaps_dumper(void)80 static int __init register_cpu_hwcaps_dumper(void)
81 {
82 	atomic_notifier_chain_register(&panic_notifier_list,
83 				       &cpu_hwcaps_notifier);
84 	return 0;
85 }
86 __initcall(register_cpu_hwcaps_dumper);
87 
88 DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS);
89 EXPORT_SYMBOL(cpu_hwcap_keys);
90 
91 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
92 	{						\
93 		.sign = SIGNED,				\
94 		.visible = VISIBLE,			\
95 		.strict = STRICT,			\
96 		.type = TYPE,				\
97 		.shift = SHIFT,				\
98 		.width = WIDTH,				\
99 		.safe_val = SAFE_VAL,			\
100 	}
101 
102 /* Define a feature with unsigned values */
103 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
104 	__ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
105 
106 /* Define a feature with a signed value */
107 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
108 	__ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
109 
110 #define ARM64_FTR_END					\
111 	{						\
112 		.width = 0,				\
113 	}
114 
115 /* meta feature for alternatives */
116 static bool __maybe_unused
117 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused);
118 
119 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap);
120 
121 /*
122  * NOTE: Any changes to the visibility of features should be kept in
123  * sync with the documentation of the CPU feature register ABI.
124  */
125 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
126 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0),
127 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0),
128 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0),
129 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0),
130 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0),
131 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0),
132 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
133 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
134 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
135 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
136 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
137 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
138 	ARM64_FTR_END,
139 };
140 
141 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
142 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SB_SHIFT, 4, 0),
143 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FRINTTS_SHIFT, 4, 0),
144 	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
145 		       FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPI_SHIFT, 4, 0),
146 	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
147 		       FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPA_SHIFT, 4, 0),
148 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0),
149 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0),
150 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0),
151 	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
152 		       FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_API_SHIFT, 4, 0),
153 	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
154 		       FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_APA_SHIFT, 4, 0),
155 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0),
156 	ARM64_FTR_END,
157 };
158 
159 static const struct arm64_ftr_bits ftr_id_aa64isar2[] = {
160 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_CLEARBHB_SHIFT, 4, 0),
161 	ARM64_FTR_END,
162 };
163 
164 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
165 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0),
166 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0),
167 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0),
168 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_AMU_SHIFT, 4, 0),
169 	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
170 				   FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0),
171 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0),
172 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0),
173 	S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
174 	S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
175 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0),
176 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0),
177 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
178 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
179 	ARM64_FTR_END,
180 };
181 
182 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = {
183 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI),
184 	ARM64_FTR_END,
185 };
186 
187 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = {
188 	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
189 		       FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0),
190 	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
191 		       FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0),
192 	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
193 		       FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0),
194 	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
195 		       FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0),
196 	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
197 		       FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0),
198 	ARM64_FTR_END,
199 };
200 
201 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
202 	/*
203 	 * We already refuse to boot CPUs that don't support our configured
204 	 * page size, so we can only detect mismatches for a page size other
205 	 * than the one we're currently using. Unfortunately, SoCs like this
206 	 * exist in the wild so, even though we don't like it, we'll have to go
207 	 * along with it and treat them as non-strict.
208 	 */
209 	S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
210 	S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
211 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
212 
213 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
214 	/* Linux shouldn't care about secure memory */
215 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
216 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
217 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
218 	/*
219 	 * Differing PARange is fine as long as all peripherals and memory are mapped
220 	 * within the minimum PARange of all CPUs
221 	 */
222 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
223 	ARM64_FTR_END,
224 };
225 
226 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
227 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
228 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
229 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
230 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
231 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
232 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
233 	ARM64_FTR_END,
234 };
235 
236 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
237 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0),
238 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0),
239 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
240 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0),
241 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0),
242 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
243 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0),
244 	ARM64_FTR_END,
245 };
246 
247 static const struct arm64_ftr_bits ftr_ctr[] = {
248 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */
249 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1),
250 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1),
251 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_CWG_SHIFT, 4, 0),
252 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_ERG_SHIFT, 4, 0),
253 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1),
254 	/*
255 	 * Linux can handle differing I-cache policies. Userspace JITs will
256 	 * make use of *minLine.
257 	 * If we have differing I-cache policies, report it as the weakest - VIPT.
258 	 */
259 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, 14, 2, ICACHE_POLICY_VIPT),	/* L1Ip */
260 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0),
261 	ARM64_FTR_END,
262 };
263 
264 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
265 	.name		= "SYS_CTR_EL0",
266 	.ftr_bits	= ftr_ctr
267 };
268 
269 static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
270 	S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0xf),	/* InnerShr */
271 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),	/* FCSE */
272 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0),	/* AuxReg */
273 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),	/* TCM */
274 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),	/* ShareLvl */
275 	S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0xf),	/* OuterShr */
276 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),	/* PMSA */
277 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),	/* VMSA */
278 	ARM64_FTR_END,
279 };
280 
281 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
282 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 36, 28, 0),
283 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0),
284 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
285 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
286 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
287 	/*
288 	 * We can instantiate multiple PMU instances with different levels
289 	 * of support.
290 	 */
291 	S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
292 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
293 	ARM64_FTR_END,
294 };
295 
296 static const struct arm64_ftr_bits ftr_mvfr2[] = {
297 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),		/* FPMisc */
298 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),		/* SIMDMisc */
299 	ARM64_FTR_END,
300 };
301 
302 static const struct arm64_ftr_bits ftr_dczid[] = {
303 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 4, 1, 1),		/* DZP */
304 	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),	/* BS */
305 	ARM64_FTR_END,
306 };
307 
308 
309 static const struct arm64_ftr_bits ftr_id_isar5[] = {
310 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0),
311 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),
312 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),
313 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),
314 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),
315 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0),
316 	ARM64_FTR_END,
317 };
318 
319 static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
320 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),	/* ac2 */
321 	ARM64_FTR_END,
322 };
323 
324 static const struct arm64_ftr_bits ftr_id_pfr0[] = {
325 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),		/* State3 */
326 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),		/* State2 */
327 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),		/* State1 */
328 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),		/* State0 */
329 	ARM64_FTR_END,
330 };
331 
332 static const struct arm64_ftr_bits ftr_id_dfr0[] = {
333 	/* [31:28] TraceFilt */
334 	S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf),	/* PerfMon */
335 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
336 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
337 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
338 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
339 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
340 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
341 	ARM64_FTR_END,
342 };
343 
344 static const struct arm64_ftr_bits ftr_zcr[] = {
345 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,
346 		ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0),	/* LEN */
347 	ARM64_FTR_END,
348 };
349 
350 /*
351  * Common ftr bits for a 32bit register with all hidden, strict
352  * attributes, with 4bit feature fields and a default safe value of
353  * 0. Covers the following 32bit registers:
354  * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
355  */
356 static const struct arm64_ftr_bits ftr_generic_32bits[] = {
357 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
358 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
359 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
360 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
361 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
362 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
363 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
364 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
365 	ARM64_FTR_END,
366 };
367 
368 /* Table for a single 32bit feature value */
369 static const struct arm64_ftr_bits ftr_single32[] = {
370 	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0),
371 	ARM64_FTR_END,
372 };
373 
374 static const struct arm64_ftr_bits ftr_raz[] = {
375 	ARM64_FTR_END,
376 };
377 
378 #define ARM64_FTR_REG(id, table) {		\
379 	.sys_id = id,				\
380 	.reg = 	&(struct arm64_ftr_reg){	\
381 		.name = #id,			\
382 		.ftr_bits = &((table)[0]),	\
383 	}}
384 
385 static const struct __ftr_reg_entry {
386 	u32			sys_id;
387 	struct arm64_ftr_reg 	*reg;
388 } arm64_ftr_regs[] = {
389 
390 	/* Op1 = 0, CRn = 0, CRm = 1 */
391 	ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
392 	ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits),
393 	ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
394 	ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
395 	ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
396 	ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
397 	ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
398 
399 	/* Op1 = 0, CRn = 0, CRm = 2 */
400 	ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits),
401 	ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
402 	ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
403 	ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
404 	ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits),
405 	ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
406 	ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
407 
408 	/* Op1 = 0, CRn = 0, CRm = 3 */
409 	ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
410 	ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
411 	ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
412 
413 	/* Op1 = 0, CRn = 0, CRm = 4 */
414 	ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
415 	ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1),
416 	ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0),
417 
418 	/* Op1 = 0, CRn = 0, CRm = 5 */
419 	ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
420 	ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz),
421 
422 	/* Op1 = 0, CRn = 0, CRm = 6 */
423 	ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
424 	ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1),
425 	ARM64_FTR_REG(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2),
426 
427 	/* Op1 = 0, CRn = 0, CRm = 7 */
428 	ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
429 	ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
430 	ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
431 
432 	/* Op1 = 0, CRn = 1, CRm = 2 */
433 	ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr),
434 
435 	/* Op1 = 3, CRn = 0, CRm = 0 */
436 	{ SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
437 	ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
438 
439 	/* Op1 = 3, CRn = 14, CRm = 0 */
440 	ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32),
441 };
442 
search_cmp_ftr_reg(const void * id,const void * regp)443 static int search_cmp_ftr_reg(const void *id, const void *regp)
444 {
445 	return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id;
446 }
447 
448 /*
449  * get_arm64_ftr_reg - Lookup a feature register entry using its
450  * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
451  * ascending order of sys_id , we use binary search to find a matching
452  * entry.
453  *
454  * returns - Upon success,  matching ftr_reg entry for id.
455  *         - NULL on failure. It is upto the caller to decide
456  *	     the impact of a failure.
457  */
get_arm64_ftr_reg(u32 sys_id)458 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
459 {
460 	const struct __ftr_reg_entry *ret;
461 
462 	ret = bsearch((const void *)(unsigned long)sys_id,
463 			arm64_ftr_regs,
464 			ARRAY_SIZE(arm64_ftr_regs),
465 			sizeof(arm64_ftr_regs[0]),
466 			search_cmp_ftr_reg);
467 	if (ret)
468 		return ret->reg;
469 	return NULL;
470 }
471 
arm64_ftr_set_value(const struct arm64_ftr_bits * ftrp,s64 reg,s64 ftr_val)472 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
473 			       s64 ftr_val)
474 {
475 	u64 mask = arm64_ftr_mask(ftrp);
476 
477 	reg &= ~mask;
478 	reg |= (ftr_val << ftrp->shift) & mask;
479 	return reg;
480 }
481 
arm64_ftr_safe_value(const struct arm64_ftr_bits * ftrp,s64 new,s64 cur)482 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
483 				s64 cur)
484 {
485 	s64 ret = 0;
486 
487 	switch (ftrp->type) {
488 	case FTR_EXACT:
489 		ret = ftrp->safe_val;
490 		break;
491 	case FTR_LOWER_SAFE:
492 		ret = new < cur ? new : cur;
493 		break;
494 	case FTR_HIGHER_OR_ZERO_SAFE:
495 		if (!cur || !new)
496 			break;
497 		/* Fallthrough */
498 	case FTR_HIGHER_SAFE:
499 		ret = new > cur ? new : cur;
500 		break;
501 	default:
502 		BUG();
503 	}
504 
505 	return ret;
506 }
507 
sort_ftr_regs(void)508 static void __init sort_ftr_regs(void)
509 {
510 	int i;
511 
512 	/* Check that the array is sorted so that we can do the binary search */
513 	for (i = 1; i < ARRAY_SIZE(arm64_ftr_regs); i++)
514 		BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id);
515 }
516 
517 /*
518  * Initialise the CPU feature register from Boot CPU values.
519  * Also initiliases the strict_mask for the register.
520  * Any bits that are not covered by an arm64_ftr_bits entry are considered
521  * RES0 for the system-wide value, and must strictly match.
522  */
init_cpu_ftr_reg(u32 sys_reg,u64 new)523 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
524 {
525 	u64 val = 0;
526 	u64 strict_mask = ~0x0ULL;
527 	u64 user_mask = 0;
528 	u64 valid_mask = 0;
529 
530 	const struct arm64_ftr_bits *ftrp;
531 	struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
532 
533 	BUG_ON(!reg);
534 
535 	for (ftrp  = reg->ftr_bits; ftrp->width; ftrp++) {
536 		u64 ftr_mask = arm64_ftr_mask(ftrp);
537 		s64 ftr_new = arm64_ftr_value(ftrp, new);
538 
539 		val = arm64_ftr_set_value(ftrp, val, ftr_new);
540 
541 		valid_mask |= ftr_mask;
542 		if (!ftrp->strict)
543 			strict_mask &= ~ftr_mask;
544 		if (ftrp->visible)
545 			user_mask |= ftr_mask;
546 		else
547 			reg->user_val = arm64_ftr_set_value(ftrp,
548 							    reg->user_val,
549 							    ftrp->safe_val);
550 	}
551 
552 	val &= valid_mask;
553 
554 	reg->sys_val = val;
555 	reg->strict_mask = strict_mask;
556 	reg->user_mask = user_mask;
557 }
558 
559 extern const struct arm64_cpu_capabilities arm64_errata[];
560 static const struct arm64_cpu_capabilities arm64_features[];
561 
562 static void __init
init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities * caps)563 init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities *caps)
564 {
565 	for (; caps->matches; caps++) {
566 		if (WARN(caps->capability >= ARM64_NCAPS,
567 			"Invalid capability %d\n", caps->capability))
568 			continue;
569 		if (WARN(cpu_hwcaps_ptrs[caps->capability],
570 			"Duplicate entry for capability %d\n",
571 			caps->capability))
572 			continue;
573 		cpu_hwcaps_ptrs[caps->capability] = caps;
574 	}
575 }
576 
init_cpu_hwcaps_indirect_list(void)577 static void __init init_cpu_hwcaps_indirect_list(void)
578 {
579 	init_cpu_hwcaps_indirect_list_from_array(arm64_features);
580 	init_cpu_hwcaps_indirect_list_from_array(arm64_errata);
581 }
582 
583 static void __init setup_boot_cpu_capabilities(void);
584 
init_cpu_features(struct cpuinfo_arm64 * info)585 void __init init_cpu_features(struct cpuinfo_arm64 *info)
586 {
587 	/* Before we start using the tables, make sure it is sorted */
588 	sort_ftr_regs();
589 
590 	init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
591 	init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
592 	init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
593 	init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
594 	init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
595 	init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
596 	init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
597 	init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2);
598 	init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
599 	init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
600 	init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
601 	init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
602 	init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
603 	init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0);
604 
605 	if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
606 		init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
607 		init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
608 		init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
609 		init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
610 		init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
611 		init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
612 		init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
613 		init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
614 		init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
615 		init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
616 		init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
617 		init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
618 		init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
619 		init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
620 		init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
621 		init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
622 	}
623 
624 	if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
625 		init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr);
626 		sve_init_vq_map();
627 	}
628 
629 	/*
630 	 * Initialize the indirect array of CPU hwcaps capabilities pointers
631 	 * before we handle the boot CPU below.
632 	 */
633 	init_cpu_hwcaps_indirect_list();
634 
635 	/*
636 	 * Detect and enable early CPU capabilities based on the boot CPU,
637 	 * after we have initialised the CPU feature infrastructure.
638 	 */
639 	setup_boot_cpu_capabilities();
640 }
641 
update_cpu_ftr_reg(struct arm64_ftr_reg * reg,u64 new)642 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
643 {
644 	const struct arm64_ftr_bits *ftrp;
645 
646 	for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
647 		s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
648 		s64 ftr_new = arm64_ftr_value(ftrp, new);
649 
650 		if (ftr_cur == ftr_new)
651 			continue;
652 		/* Find a safe value */
653 		ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
654 		reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
655 	}
656 
657 }
658 
check_update_ftr_reg(u32 sys_id,int cpu,u64 val,u64 boot)659 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
660 {
661 	struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
662 
663 	BUG_ON(!regp);
664 	update_cpu_ftr_reg(regp, val);
665 	if ((boot & regp->strict_mask) == (val & regp->strict_mask))
666 		return 0;
667 	pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
668 			regp->name, boot, cpu, val);
669 	return 1;
670 }
671 
672 /*
673  * Update system wide CPU feature registers with the values from a
674  * non-boot CPU. Also performs SANITY checks to make sure that there
675  * aren't any insane variations from that of the boot CPU.
676  */
update_cpu_features(int cpu,struct cpuinfo_arm64 * info,struct cpuinfo_arm64 * boot)677 void update_cpu_features(int cpu,
678 			 struct cpuinfo_arm64 *info,
679 			 struct cpuinfo_arm64 *boot)
680 {
681 	int taint = 0;
682 
683 	/*
684 	 * The kernel can handle differing I-cache policies, but otherwise
685 	 * caches should look identical. Userspace JITs will make use of
686 	 * *minLine.
687 	 */
688 	taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
689 				      info->reg_ctr, boot->reg_ctr);
690 
691 	/*
692 	 * Userspace may perform DC ZVA instructions. Mismatched block sizes
693 	 * could result in too much or too little memory being zeroed if a
694 	 * process is preempted and migrated between CPUs.
695 	 */
696 	taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
697 				      info->reg_dczid, boot->reg_dczid);
698 
699 	/* If different, timekeeping will be broken (especially with KVM) */
700 	taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
701 				      info->reg_cntfrq, boot->reg_cntfrq);
702 
703 	/*
704 	 * The kernel uses self-hosted debug features and expects CPUs to
705 	 * support identical debug features. We presently need CTX_CMPs, WRPs,
706 	 * and BRPs to be identical.
707 	 * ID_AA64DFR1 is currently RES0.
708 	 */
709 	taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
710 				      info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
711 	taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
712 				      info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
713 	/*
714 	 * Even in big.LITTLE, processors should be identical instruction-set
715 	 * wise.
716 	 */
717 	taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
718 				      info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
719 	taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
720 				      info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
721 	taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu,
722 				      info->reg_id_aa64isar2, boot->reg_id_aa64isar2);
723 
724 	/*
725 	 * Differing PARange support is fine as long as all peripherals and
726 	 * memory are mapped within the minimum PARange of all CPUs.
727 	 * Linux should not care about secure memory.
728 	 */
729 	taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
730 				      info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
731 	taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
732 				      info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
733 	taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
734 				      info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
735 
736 	taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
737 				      info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
738 	taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
739 				      info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
740 
741 	taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu,
742 				      info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0);
743 
744 	/*
745 	 * If we have AArch32, we care about 32-bit features for compat.
746 	 * If the system doesn't support AArch32, don't update them.
747 	 */
748 	if (id_aa64pfr0_32bit_el0(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
749 		id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
750 
751 		taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
752 					info->reg_id_dfr0, boot->reg_id_dfr0);
753 		taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
754 					info->reg_id_isar0, boot->reg_id_isar0);
755 		taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
756 					info->reg_id_isar1, boot->reg_id_isar1);
757 		taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
758 					info->reg_id_isar2, boot->reg_id_isar2);
759 		taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
760 					info->reg_id_isar3, boot->reg_id_isar3);
761 		taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
762 					info->reg_id_isar4, boot->reg_id_isar4);
763 		taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
764 					info->reg_id_isar5, boot->reg_id_isar5);
765 
766 		/*
767 		 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
768 		 * ACTLR formats could differ across CPUs and therefore would have to
769 		 * be trapped for virtualization anyway.
770 		 */
771 		taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
772 					info->reg_id_mmfr0, boot->reg_id_mmfr0);
773 		taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
774 					info->reg_id_mmfr1, boot->reg_id_mmfr1);
775 		taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
776 					info->reg_id_mmfr2, boot->reg_id_mmfr2);
777 		taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
778 					info->reg_id_mmfr3, boot->reg_id_mmfr3);
779 		taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
780 					info->reg_id_pfr0, boot->reg_id_pfr0);
781 		taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
782 					info->reg_id_pfr1, boot->reg_id_pfr1);
783 		taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
784 					info->reg_mvfr0, boot->reg_mvfr0);
785 		taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
786 					info->reg_mvfr1, boot->reg_mvfr1);
787 		taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
788 					info->reg_mvfr2, boot->reg_mvfr2);
789 	}
790 
791 	if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
792 		taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu,
793 					info->reg_zcr, boot->reg_zcr);
794 
795 		/* Probe vector lengths, unless we already gave up on SVE */
796 		if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
797 		    !sys_caps_initialised)
798 			sve_update_vq_map();
799 	}
800 
801 	/*
802 	 * Mismatched CPU features are a recipe for disaster. Don't even
803 	 * pretend to support them.
804 	 */
805 	if (taint) {
806 		pr_warn_once("Unsupported CPU feature variation detected.\n");
807 		add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
808 	}
809 }
810 
read_sanitised_ftr_reg(u32 id)811 u64 read_sanitised_ftr_reg(u32 id)
812 {
813 	struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
814 
815 	/* We shouldn't get a request for an unsupported register */
816 	BUG_ON(!regp);
817 	return regp->sys_val;
818 }
819 
820 #define read_sysreg_case(r)	\
821 	case r:		return read_sysreg_s(r)
822 
823 /*
824  * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated.
825  * Read the system register on the current CPU
826  */
__read_sysreg_by_encoding(u32 sys_id)827 static u64 __read_sysreg_by_encoding(u32 sys_id)
828 {
829 	switch (sys_id) {
830 	read_sysreg_case(SYS_ID_PFR0_EL1);
831 	read_sysreg_case(SYS_ID_PFR1_EL1);
832 	read_sysreg_case(SYS_ID_DFR0_EL1);
833 	read_sysreg_case(SYS_ID_MMFR0_EL1);
834 	read_sysreg_case(SYS_ID_MMFR1_EL1);
835 	read_sysreg_case(SYS_ID_MMFR2_EL1);
836 	read_sysreg_case(SYS_ID_MMFR3_EL1);
837 	read_sysreg_case(SYS_ID_ISAR0_EL1);
838 	read_sysreg_case(SYS_ID_ISAR1_EL1);
839 	read_sysreg_case(SYS_ID_ISAR2_EL1);
840 	read_sysreg_case(SYS_ID_ISAR3_EL1);
841 	read_sysreg_case(SYS_ID_ISAR4_EL1);
842 	read_sysreg_case(SYS_ID_ISAR5_EL1);
843 	read_sysreg_case(SYS_MVFR0_EL1);
844 	read_sysreg_case(SYS_MVFR1_EL1);
845 	read_sysreg_case(SYS_MVFR2_EL1);
846 
847 	read_sysreg_case(SYS_ID_AA64PFR0_EL1);
848 	read_sysreg_case(SYS_ID_AA64PFR1_EL1);
849 	read_sysreg_case(SYS_ID_AA64ZFR0_EL1);
850 	read_sysreg_case(SYS_ID_AA64DFR0_EL1);
851 	read_sysreg_case(SYS_ID_AA64DFR1_EL1);
852 	read_sysreg_case(SYS_ID_AA64MMFR0_EL1);
853 	read_sysreg_case(SYS_ID_AA64MMFR1_EL1);
854 	read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
855 	read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
856 	read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
857 	read_sysreg_case(SYS_ID_AA64ISAR2_EL1);
858 
859 	read_sysreg_case(SYS_CNTFRQ_EL0);
860 	read_sysreg_case(SYS_CTR_EL0);
861 	read_sysreg_case(SYS_DCZID_EL0);
862 
863 	default:
864 		BUG();
865 		return 0;
866 	}
867 }
868 
869 #include <linux/irqchip/arm-gic-v3.h>
870 
871 static bool
feature_matches(u64 reg,const struct arm64_cpu_capabilities * entry)872 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
873 {
874 	int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign);
875 
876 	return val >= entry->min_field_value;
877 }
878 
879 static bool
has_cpuid_feature(const struct arm64_cpu_capabilities * entry,int scope)880 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
881 {
882 	u64 val;
883 
884 	WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
885 	if (scope == SCOPE_SYSTEM)
886 		val = read_sanitised_ftr_reg(entry->sys_reg);
887 	else
888 		val = __read_sysreg_by_encoding(entry->sys_reg);
889 
890 	return feature_matches(val, entry);
891 }
892 
has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities * entry,int scope)893 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
894 {
895 	bool has_sre;
896 
897 	if (!has_cpuid_feature(entry, scope))
898 		return false;
899 
900 	has_sre = gic_enable_sre();
901 	if (!has_sre)
902 		pr_warn_once("%s present but disabled by higher exception level\n",
903 			     entry->desc);
904 
905 	return has_sre;
906 }
907 
has_no_hw_prefetch(const struct arm64_cpu_capabilities * entry,int __unused)908 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
909 {
910 	u32 midr = read_cpuid_id();
911 
912 	/* Cavium ThunderX pass 1.x and 2.x */
913 	return midr_is_cpu_model_range(midr, MIDR_THUNDERX,
914 		MIDR_CPU_VAR_REV(0, 0),
915 		MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK));
916 }
917 
has_no_fpsimd(const struct arm64_cpu_capabilities * entry,int __unused)918 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused)
919 {
920 	u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
921 
922 	return cpuid_feature_extract_signed_field(pfr0,
923 					ID_AA64PFR0_FP_SHIFT) < 0;
924 }
925 
has_cache_idc(const struct arm64_cpu_capabilities * entry,int scope)926 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry,
927 			  int scope)
928 {
929 	u64 ctr;
930 
931 	if (scope == SCOPE_SYSTEM)
932 		ctr = arm64_ftr_reg_ctrel0.sys_val;
933 	else
934 		ctr = read_cpuid_effective_cachetype();
935 
936 	return ctr & BIT(CTR_IDC_SHIFT);
937 }
938 
cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities * __unused)939 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused)
940 {
941 	/*
942 	 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively
943 	 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses
944 	 * to the CTR_EL0 on this CPU and emulate it with the real/safe
945 	 * value.
946 	 */
947 	if (!(read_cpuid_cachetype() & BIT(CTR_IDC_SHIFT)))
948 		sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
949 }
950 
has_cache_dic(const struct arm64_cpu_capabilities * entry,int scope)951 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry,
952 			  int scope)
953 {
954 	u64 ctr;
955 
956 	if (scope == SCOPE_SYSTEM)
957 		ctr = arm64_ftr_reg_ctrel0.sys_val;
958 	else
959 		ctr = read_cpuid_cachetype();
960 
961 	return ctr & BIT(CTR_DIC_SHIFT);
962 }
963 
964 static bool __maybe_unused
has_useable_cnp(const struct arm64_cpu_capabilities * entry,int scope)965 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope)
966 {
967 	/*
968 	 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP
969 	 * may share TLB entries with a CPU stuck in the crashed
970 	 * kernel.
971 	 */
972 	 if (is_kdump_kernel())
973 		return false;
974 
975 	return has_cpuid_feature(entry, scope);
976 }
977 
978 static bool __meltdown_safe = true;
979 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */
980 
unmap_kernel_at_el0(const struct arm64_cpu_capabilities * entry,int scope)981 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
982 				int scope)
983 {
984 	/* List of CPUs that are not vulnerable and don't need KPTI */
985 	static const struct midr_range kpti_safe_list[] = {
986 		MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
987 		MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
988 		MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
989 		MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
990 		MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
991 		MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
992 		MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
993 		MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
994 		MIDR_ALL_VERSIONS(MIDR_HISI_TSV110),
995 		{ /* sentinel */ }
996 	};
997 	char const *str = "kpti command line option";
998 	bool meltdown_safe;
999 
1000 	meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list);
1001 
1002 	/* Defer to CPU feature registers */
1003 	if (has_cpuid_feature(entry, scope))
1004 		meltdown_safe = true;
1005 
1006 	if (!meltdown_safe)
1007 		__meltdown_safe = false;
1008 
1009 	/*
1010 	 * For reasons that aren't entirely clear, enabling KPTI on Cavium
1011 	 * ThunderX leads to apparent I-cache corruption of kernel text, which
1012 	 * ends as well as you might imagine. Don't even try.
1013 	 */
1014 	if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_27456)) {
1015 		str = "ARM64_WORKAROUND_CAVIUM_27456";
1016 		__kpti_forced = -1;
1017 	}
1018 
1019 	/* Useful for KASLR robustness */
1020 	if (IS_ENABLED(CONFIG_RANDOMIZE_BASE) && kaslr_offset() > 0) {
1021 		if (!__kpti_forced) {
1022 			str = "KASLR";
1023 			__kpti_forced = 1;
1024 		}
1025 	}
1026 
1027 	if (cpu_mitigations_off() && !__kpti_forced) {
1028 		str = "mitigations=off";
1029 		__kpti_forced = -1;
1030 	}
1031 
1032 	if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) {
1033 		pr_info_once("kernel page table isolation disabled by kernel configuration\n");
1034 		return false;
1035 	}
1036 
1037 	/* Forced? */
1038 	if (__kpti_forced) {
1039 		pr_info_once("kernel page table isolation forced %s by %s\n",
1040 			     __kpti_forced > 0 ? "ON" : "OFF", str);
1041 		return __kpti_forced > 0;
1042 	}
1043 
1044 	return !meltdown_safe;
1045 }
1046 
1047 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
1048 static void __nocfi
kpti_install_ng_mappings(const struct arm64_cpu_capabilities * __unused)1049 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1050 {
1051 	typedef void (kpti_remap_fn)(int, int, phys_addr_t);
1052 	extern kpti_remap_fn idmap_kpti_install_ng_mappings;
1053 	kpti_remap_fn *remap_fn;
1054 
1055 	static bool kpti_applied = false;
1056 	int cpu = smp_processor_id();
1057 
1058 	if (__this_cpu_read(this_cpu_vector) == vectors) {
1059 		const char *v = arm64_get_bp_hardening_vector(EL1_VECTOR_KPTI);
1060 
1061 		__this_cpu_write(this_cpu_vector, v);
1062 	}
1063 
1064 	/*
1065 	 * We don't need to rewrite the page-tables if either we've done
1066 	 * it already or we have KASLR enabled and therefore have not
1067 	 * created any global mappings at all.
1068 	 */
1069 	if (kpti_applied || kaslr_offset() > 0)
1070 		return;
1071 
1072 	remap_fn = (void *)__pa_function(idmap_kpti_install_ng_mappings);
1073 
1074 	cpu_install_idmap();
1075 	remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir));
1076 	cpu_uninstall_idmap();
1077 
1078 	if (!cpu)
1079 		kpti_applied = true;
1080 
1081 	return;
1082 }
1083 #else
1084 static void
kpti_install_ng_mappings(const struct arm64_cpu_capabilities * __unused)1085 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1086 {
1087 }
1088 #endif	/* CONFIG_UNMAP_KERNEL_AT_EL0 */
1089 
parse_kpti(char * str)1090 static int __init parse_kpti(char *str)
1091 {
1092 	bool enabled;
1093 	int ret = strtobool(str, &enabled);
1094 
1095 	if (ret)
1096 		return ret;
1097 
1098 	__kpti_forced = enabled ? 1 : -1;
1099 	return 0;
1100 }
1101 early_param("kpti", parse_kpti);
1102 
1103 #ifdef CONFIG_ARM64_HW_AFDBM
__cpu_enable_hw_dbm(void)1104 static inline void __cpu_enable_hw_dbm(void)
1105 {
1106 	u64 tcr = read_sysreg(tcr_el1) | TCR_HD;
1107 
1108 	write_sysreg(tcr, tcr_el1);
1109 	isb();
1110 }
1111 
cpu_has_broken_dbm(void)1112 static bool cpu_has_broken_dbm(void)
1113 {
1114 	/* List of CPUs which have broken DBM support. */
1115 	static const struct midr_range cpus[] = {
1116 #ifdef CONFIG_ARM64_ERRATUM_1024718
1117 		MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
1118 #endif
1119 		{},
1120 	};
1121 
1122 	return is_midr_in_range_list(read_cpuid_id(), cpus);
1123 }
1124 
cpu_can_use_dbm(const struct arm64_cpu_capabilities * cap)1125 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap)
1126 {
1127 	return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) &&
1128 	       !cpu_has_broken_dbm();
1129 }
1130 
cpu_enable_hw_dbm(struct arm64_cpu_capabilities const * cap)1131 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap)
1132 {
1133 	if (cpu_can_use_dbm(cap))
1134 		__cpu_enable_hw_dbm();
1135 }
1136 
has_hw_dbm(const struct arm64_cpu_capabilities * cap,int __unused)1137 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap,
1138 		       int __unused)
1139 {
1140 	static bool detected = false;
1141 	/*
1142 	 * DBM is a non-conflicting feature. i.e, the kernel can safely
1143 	 * run a mix of CPUs with and without the feature. So, we
1144 	 * unconditionally enable the capability to allow any late CPU
1145 	 * to use the feature. We only enable the control bits on the
1146 	 * CPU, if it actually supports.
1147 	 *
1148 	 * We have to make sure we print the "feature" detection only
1149 	 * when at least one CPU actually uses it. So check if this CPU
1150 	 * can actually use it and print the message exactly once.
1151 	 *
1152 	 * This is safe as all CPUs (including secondary CPUs - due to the
1153 	 * LOCAL_CPU scope - and the hotplugged CPUs - via verification)
1154 	 * goes through the "matches" check exactly once. Also if a CPU
1155 	 * matches the criteria, it is guaranteed that the CPU will turn
1156 	 * the DBM on, as the capability is unconditionally enabled.
1157 	 */
1158 	if (!detected && cpu_can_use_dbm(cap)) {
1159 		detected = true;
1160 		pr_info("detected: Hardware dirty bit management\n");
1161 	}
1162 
1163 	return true;
1164 }
1165 
1166 #endif
1167 
1168 #ifdef CONFIG_ARM64_AMU_EXTN
1169 
1170 /*
1171  * The "amu_cpus" cpumask only signals that the CPU implementation for the
1172  * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide
1173  * information regarding all the events that it supports. When a CPU bit is
1174  * set in the cpumask, the user of this feature can only rely on the presence
1175  * of the 4 fixed counters for that CPU. But this does not guarantee that the
1176  * counters are enabled or access to these counters is enabled by code
1177  * executed at higher exception levels (firmware).
1178  */
1179 static struct cpumask amu_cpus __read_mostly;
1180 
cpu_has_amu_feat(int cpu)1181 bool cpu_has_amu_feat(int cpu)
1182 {
1183 	return cpumask_test_cpu(cpu, &amu_cpus);
1184 }
1185 
cpu_amu_enable(struct arm64_cpu_capabilities const * cap)1186 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap)
1187 {
1188 	if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) {
1189 		pr_info("detected CPU%d: Activity Monitors Unit (AMU)\n",
1190 			smp_processor_id());
1191 		cpumask_set_cpu(smp_processor_id(), &amu_cpus);
1192 	}
1193 }
1194 
has_amu(const struct arm64_cpu_capabilities * cap,int __unused)1195 static bool has_amu(const struct arm64_cpu_capabilities *cap,
1196 		    int __unused)
1197 {
1198 	/*
1199 	 * The AMU extension is a non-conflicting feature: the kernel can
1200 	 * safely run a mix of CPUs with and without support for the
1201 	 * activity monitors extension. Therefore, unconditionally enable
1202 	 * the capability to allow any late CPU to use the feature.
1203 	 *
1204 	 * With this feature unconditionally enabled, the cpu_enable
1205 	 * function will be called for all CPUs that match the criteria,
1206 	 * including secondary and hotplugged, marking this feature as
1207 	 * present on that respective CPU. The enable function will also
1208 	 * print a detection message.
1209 	 */
1210 
1211 	return true;
1212 }
1213 #endif
1214 
1215 #ifdef CONFIG_ARM64_VHE
runs_at_el2(const struct arm64_cpu_capabilities * entry,int __unused)1216 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
1217 {
1218 	return is_kernel_in_hyp_mode();
1219 }
1220 
cpu_copy_el2regs(const struct arm64_cpu_capabilities * __unused)1221 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused)
1222 {
1223 	/*
1224 	 * Copy register values that aren't redirected by hardware.
1225 	 *
1226 	 * Before code patching, we only set tpidr_el1, all CPUs need to copy
1227 	 * this value to tpidr_el2 before we patch the code. Once we've done
1228 	 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to
1229 	 * do anything here.
1230 	 */
1231 	if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN))
1232 		write_sysreg(read_sysreg(tpidr_el1), tpidr_el2);
1233 }
1234 #endif
1235 
cpu_has_fwb(const struct arm64_cpu_capabilities * __unused)1236 static void cpu_has_fwb(const struct arm64_cpu_capabilities *__unused)
1237 {
1238 	u64 val = read_sysreg_s(SYS_CLIDR_EL1);
1239 
1240 	/* Check that CLIDR_EL1.LOU{U,IS} are both 0 */
1241 	WARN_ON(val & (7 << 27 | 7 << 21));
1242 }
1243 
1244 #ifdef CONFIG_ARM64_SSBD
ssbs_emulation_handler(struct pt_regs * regs,u32 instr)1245 static int ssbs_emulation_handler(struct pt_regs *regs, u32 instr)
1246 {
1247 	if (user_mode(regs))
1248 		return 1;
1249 
1250 	if (instr & BIT(PSTATE_Imm_shift))
1251 		regs->pstate |= PSR_SSBS_BIT;
1252 	else
1253 		regs->pstate &= ~PSR_SSBS_BIT;
1254 
1255 	arm64_skip_faulting_instruction(regs, 4);
1256 	return 0;
1257 }
1258 
1259 static struct undef_hook ssbs_emulation_hook = {
1260 	.instr_mask	= ~(1U << PSTATE_Imm_shift),
1261 	.instr_val	= 0xd500401f | PSTATE_SSBS,
1262 	.fn		= ssbs_emulation_handler,
1263 };
1264 
cpu_enable_ssbs(const struct arm64_cpu_capabilities * __unused)1265 static void cpu_enable_ssbs(const struct arm64_cpu_capabilities *__unused)
1266 {
1267 	static bool undef_hook_registered = false;
1268 	static DEFINE_RAW_SPINLOCK(hook_lock);
1269 
1270 	raw_spin_lock(&hook_lock);
1271 	if (!undef_hook_registered) {
1272 		register_undef_hook(&ssbs_emulation_hook);
1273 		undef_hook_registered = true;
1274 	}
1275 	raw_spin_unlock(&hook_lock);
1276 
1277 	if (arm64_get_ssbd_state() == ARM64_SSBD_FORCE_DISABLE) {
1278 		sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_DSSBS);
1279 		arm64_set_ssbd_mitigation(false);
1280 	} else {
1281 		arm64_set_ssbd_mitigation(true);
1282 	}
1283 }
1284 #endif /* CONFIG_ARM64_SSBD */
1285 
1286 #ifdef CONFIG_ARM64_PAN
cpu_enable_pan(const struct arm64_cpu_capabilities * __unused)1287 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused)
1288 {
1289 	/*
1290 	 * We modify PSTATE. This won't work from irq context as the PSTATE
1291 	 * is discarded once we return from the exception.
1292 	 */
1293 	WARN_ON_ONCE(in_interrupt());
1294 
1295 	sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0);
1296 	asm(SET_PSTATE_PAN(1));
1297 }
1298 #endif /* CONFIG_ARM64_PAN */
1299 
1300 #ifdef CONFIG_ARM64_RAS_EXTN
cpu_clear_disr(const struct arm64_cpu_capabilities * __unused)1301 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused)
1302 {
1303 	/* Firmware may have left a deferred SError in this register. */
1304 	write_sysreg_s(0, SYS_DISR_EL1);
1305 }
1306 #endif /* CONFIG_ARM64_RAS_EXTN */
1307 
1308 #ifdef CONFIG_ARM64_PTR_AUTH
cpu_enable_address_auth(struct arm64_cpu_capabilities const * cap)1309 static void cpu_enable_address_auth(struct arm64_cpu_capabilities const *cap)
1310 {
1311 	sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ENIA | SCTLR_ELx_ENIB |
1312 				       SCTLR_ELx_ENDA | SCTLR_ELx_ENDB);
1313 }
1314 #endif /* CONFIG_ARM64_PTR_AUTH */
1315 
1316 #ifdef CONFIG_ARM64_PSEUDO_NMI
1317 static bool enable_pseudo_nmi;
1318 
early_enable_pseudo_nmi(char * p)1319 static int __init early_enable_pseudo_nmi(char *p)
1320 {
1321 	return strtobool(p, &enable_pseudo_nmi);
1322 }
1323 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi);
1324 
can_use_gic_priorities(const struct arm64_cpu_capabilities * entry,int scope)1325 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry,
1326 				   int scope)
1327 {
1328 	return enable_pseudo_nmi && has_useable_gicv3_cpuif(entry, scope);
1329 }
1330 #endif
1331 
elf_hwcap_fixup(void)1332 static void elf_hwcap_fixup(void)
1333 {
1334 #ifdef CONFIG_ARM64_ERRATUM_1742098
1335 	if (cpus_have_const_cap(ARM64_WORKAROUND_1742098))
1336 		compat_elf_hwcap2 &= ~COMPAT_HWCAP2_AES;
1337 #endif /* ARM64_ERRATUM_1742098 */
1338 }
1339 
1340 static const struct arm64_cpu_capabilities arm64_features[] = {
1341 	{
1342 		.desc = "GIC system register CPU interface",
1343 		.capability = ARM64_HAS_SYSREG_GIC_CPUIF,
1344 		.type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1345 		.matches = has_useable_gicv3_cpuif,
1346 		.sys_reg = SYS_ID_AA64PFR0_EL1,
1347 		.field_pos = ID_AA64PFR0_GIC_SHIFT,
1348 		.sign = FTR_UNSIGNED,
1349 		.min_field_value = 1,
1350 	},
1351 #ifdef CONFIG_ARM64_PAN
1352 	{
1353 		.desc = "Privileged Access Never",
1354 		.capability = ARM64_HAS_PAN,
1355 		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
1356 		.matches = has_cpuid_feature,
1357 		.sys_reg = SYS_ID_AA64MMFR1_EL1,
1358 		.field_pos = ID_AA64MMFR1_PAN_SHIFT,
1359 		.sign = FTR_UNSIGNED,
1360 		.min_field_value = 1,
1361 		.cpu_enable = cpu_enable_pan,
1362 	},
1363 #endif /* CONFIG_ARM64_PAN */
1364 #if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
1365 	{
1366 		.desc = "LSE atomic instructions",
1367 		.capability = ARM64_HAS_LSE_ATOMICS,
1368 		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
1369 		.matches = has_cpuid_feature,
1370 		.sys_reg = SYS_ID_AA64ISAR0_EL1,
1371 		.field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
1372 		.sign = FTR_UNSIGNED,
1373 		.min_field_value = 2,
1374 	},
1375 #endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
1376 	{
1377 		.desc = "Software prefetching using PRFM",
1378 		.capability = ARM64_HAS_NO_HW_PREFETCH,
1379 		.type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1380 		.matches = has_no_hw_prefetch,
1381 	},
1382 #ifdef CONFIG_ARM64_UAO
1383 	{
1384 		.desc = "User Access Override",
1385 		.capability = ARM64_HAS_UAO,
1386 		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
1387 		.matches = has_cpuid_feature,
1388 		.sys_reg = SYS_ID_AA64MMFR2_EL1,
1389 		.field_pos = ID_AA64MMFR2_UAO_SHIFT,
1390 		.min_field_value = 1,
1391 		/*
1392 		 * We rely on stop_machine() calling uao_thread_switch() to set
1393 		 * UAO immediately after patching.
1394 		 */
1395 	},
1396 #endif /* CONFIG_ARM64_UAO */
1397 #ifdef CONFIG_ARM64_PAN
1398 	{
1399 		.capability = ARM64_ALT_PAN_NOT_UAO,
1400 		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
1401 		.matches = cpufeature_pan_not_uao,
1402 	},
1403 #endif /* CONFIG_ARM64_PAN */
1404 #ifdef CONFIG_ARM64_VHE
1405 	{
1406 		.desc = "Virtualization Host Extensions",
1407 		.capability = ARM64_HAS_VIRT_HOST_EXTN,
1408 		.type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1409 		.matches = runs_at_el2,
1410 		.cpu_enable = cpu_copy_el2regs,
1411 	},
1412 #endif	/* CONFIG_ARM64_VHE */
1413 	{
1414 		.desc = "32-bit EL0 Support",
1415 		.capability = ARM64_HAS_32BIT_EL0,
1416 		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
1417 		.matches = has_cpuid_feature,
1418 		.sys_reg = SYS_ID_AA64PFR0_EL1,
1419 		.sign = FTR_UNSIGNED,
1420 		.field_pos = ID_AA64PFR0_EL0_SHIFT,
1421 		.min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,
1422 	},
1423 	{
1424 		.desc = "Kernel page table isolation (KPTI)",
1425 		.capability = ARM64_UNMAP_KERNEL_AT_EL0,
1426 		.type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
1427 		/*
1428 		 * The ID feature fields below are used to indicate that
1429 		 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for
1430 		 * more details.
1431 		 */
1432 		.sys_reg = SYS_ID_AA64PFR0_EL1,
1433 		.field_pos = ID_AA64PFR0_CSV3_SHIFT,
1434 		.min_field_value = 1,
1435 		.matches = unmap_kernel_at_el0,
1436 		.cpu_enable = kpti_install_ng_mappings,
1437 	},
1438 	{
1439 		/* FP/SIMD is not implemented */
1440 		.capability = ARM64_HAS_NO_FPSIMD,
1441 		.type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
1442 		.min_field_value = 0,
1443 		.matches = has_no_fpsimd,
1444 	},
1445 #ifdef CONFIG_ARM64_PMEM
1446 	{
1447 		.desc = "Data cache clean to Point of Persistence",
1448 		.capability = ARM64_HAS_DCPOP,
1449 		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
1450 		.matches = has_cpuid_feature,
1451 		.sys_reg = SYS_ID_AA64ISAR1_EL1,
1452 		.field_pos = ID_AA64ISAR1_DPB_SHIFT,
1453 		.min_field_value = 1,
1454 	},
1455 	{
1456 		.desc = "Data cache clean to Point of Deep Persistence",
1457 		.capability = ARM64_HAS_DCPODP,
1458 		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
1459 		.matches = has_cpuid_feature,
1460 		.sys_reg = SYS_ID_AA64ISAR1_EL1,
1461 		.sign = FTR_UNSIGNED,
1462 		.field_pos = ID_AA64ISAR1_DPB_SHIFT,
1463 		.min_field_value = 2,
1464 	},
1465 #endif
1466 #ifdef CONFIG_ARM64_SVE
1467 	{
1468 		.desc = "Scalable Vector Extension",
1469 		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
1470 		.capability = ARM64_SVE,
1471 		.sys_reg = SYS_ID_AA64PFR0_EL1,
1472 		.sign = FTR_UNSIGNED,
1473 		.field_pos = ID_AA64PFR0_SVE_SHIFT,
1474 		.min_field_value = ID_AA64PFR0_SVE,
1475 		.matches = has_cpuid_feature,
1476 		.cpu_enable = sve_kernel_enable,
1477 	},
1478 #endif /* CONFIG_ARM64_SVE */
1479 #ifdef CONFIG_ARM64_RAS_EXTN
1480 	{
1481 		.desc = "RAS Extension Support",
1482 		.capability = ARM64_HAS_RAS_EXTN,
1483 		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
1484 		.matches = has_cpuid_feature,
1485 		.sys_reg = SYS_ID_AA64PFR0_EL1,
1486 		.sign = FTR_UNSIGNED,
1487 		.field_pos = ID_AA64PFR0_RAS_SHIFT,
1488 		.min_field_value = ID_AA64PFR0_RAS_V1,
1489 		.cpu_enable = cpu_clear_disr,
1490 	},
1491 #endif /* CONFIG_ARM64_RAS_EXTN */
1492 #ifdef CONFIG_ARM64_AMU_EXTN
1493 	{
1494 		/*
1495 		 * The feature is enabled by default if CONFIG_ARM64_AMU_EXTN=y.
1496 		 * Therefore, don't provide .desc as we don't want the detection
1497 		 * message to be shown until at least one CPU is detected to
1498 		 * support the feature.
1499 		 */
1500 		.capability = ARM64_HAS_AMU_EXTN,
1501 		.type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1502 		.matches = has_amu,
1503 		.sys_reg = SYS_ID_AA64PFR0_EL1,
1504 		.sign = FTR_UNSIGNED,
1505 		.field_pos = ID_AA64PFR0_AMU_SHIFT,
1506 		.min_field_value = ID_AA64PFR0_AMU,
1507 		.cpu_enable = cpu_amu_enable,
1508 	},
1509 #endif /* CONFIG_ARM64_AMU_EXTN */
1510 	{
1511 		.desc = "Data cache clean to the PoU not required for I/D coherence",
1512 		.capability = ARM64_HAS_CACHE_IDC,
1513 		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
1514 		.matches = has_cache_idc,
1515 		.cpu_enable = cpu_emulate_effective_ctr,
1516 	},
1517 	{
1518 		.desc = "Instruction cache invalidation not required for I/D coherence",
1519 		.capability = ARM64_HAS_CACHE_DIC,
1520 		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
1521 		.matches = has_cache_dic,
1522 	},
1523 	{
1524 		.desc = "Stage-2 Force Write-Back",
1525 		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
1526 		.capability = ARM64_HAS_STAGE2_FWB,
1527 		.sys_reg = SYS_ID_AA64MMFR2_EL1,
1528 		.sign = FTR_UNSIGNED,
1529 		.field_pos = ID_AA64MMFR2_FWB_SHIFT,
1530 		.min_field_value = 1,
1531 		.matches = has_cpuid_feature,
1532 		.cpu_enable = cpu_has_fwb,
1533 	},
1534 #ifdef CONFIG_ARM64_HW_AFDBM
1535 	{
1536 		/*
1537 		 * Since we turn this on always, we don't want the user to
1538 		 * think that the feature is available when it may not be.
1539 		 * So hide the description.
1540 		 *
1541 		 * .desc = "Hardware pagetable Dirty Bit Management",
1542 		 *
1543 		 */
1544 		.type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1545 		.capability = ARM64_HW_DBM,
1546 		.sys_reg = SYS_ID_AA64MMFR1_EL1,
1547 		.sign = FTR_UNSIGNED,
1548 		.field_pos = ID_AA64MMFR1_HADBS_SHIFT,
1549 		.min_field_value = 2,
1550 		.matches = has_hw_dbm,
1551 		.cpu_enable = cpu_enable_hw_dbm,
1552 	},
1553 #endif
1554 	{
1555 		.desc = "CRC32 instructions",
1556 		.capability = ARM64_HAS_CRC32,
1557 		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
1558 		.matches = has_cpuid_feature,
1559 		.sys_reg = SYS_ID_AA64ISAR0_EL1,
1560 		.field_pos = ID_AA64ISAR0_CRC32_SHIFT,
1561 		.min_field_value = 1,
1562 	},
1563 #ifdef CONFIG_ARM64_SSBD
1564 	{
1565 		.desc = "Speculative Store Bypassing Safe (SSBS)",
1566 		.capability = ARM64_SSBS,
1567 		.type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1568 		.matches = has_cpuid_feature,
1569 		.sys_reg = SYS_ID_AA64PFR1_EL1,
1570 		.field_pos = ID_AA64PFR1_SSBS_SHIFT,
1571 		.sign = FTR_UNSIGNED,
1572 		.min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY,
1573 		.cpu_enable = cpu_enable_ssbs,
1574 	},
1575 #endif
1576 #ifdef CONFIG_ARM64_CNP
1577 	{
1578 		.desc = "Common not Private translations",
1579 		.capability = ARM64_HAS_CNP,
1580 		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
1581 		.matches = has_useable_cnp,
1582 		.sys_reg = SYS_ID_AA64MMFR2_EL1,
1583 		.sign = FTR_UNSIGNED,
1584 		.field_pos = ID_AA64MMFR2_CNP_SHIFT,
1585 		.min_field_value = 1,
1586 		.cpu_enable = cpu_enable_cnp,
1587 	},
1588 #endif
1589 	{
1590 		.desc = "Speculation barrier (SB)",
1591 		.capability = ARM64_HAS_SB,
1592 		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
1593 		.matches = has_cpuid_feature,
1594 		.sys_reg = SYS_ID_AA64ISAR1_EL1,
1595 		.field_pos = ID_AA64ISAR1_SB_SHIFT,
1596 		.sign = FTR_UNSIGNED,
1597 		.min_field_value = 1,
1598 	},
1599 #ifdef CONFIG_ARM64_PTR_AUTH
1600 	{
1601 		.desc = "Address authentication (architected algorithm)",
1602 		.capability = ARM64_HAS_ADDRESS_AUTH_ARCH,
1603 		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
1604 		.sys_reg = SYS_ID_AA64ISAR1_EL1,
1605 		.sign = FTR_UNSIGNED,
1606 		.field_pos = ID_AA64ISAR1_APA_SHIFT,
1607 		.min_field_value = ID_AA64ISAR1_APA_ARCHITECTED,
1608 		.matches = has_cpuid_feature,
1609 		.cpu_enable = cpu_enable_address_auth,
1610 	},
1611 	{
1612 		.desc = "Address authentication (IMP DEF algorithm)",
1613 		.capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF,
1614 		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
1615 		.sys_reg = SYS_ID_AA64ISAR1_EL1,
1616 		.sign = FTR_UNSIGNED,
1617 		.field_pos = ID_AA64ISAR1_API_SHIFT,
1618 		.min_field_value = ID_AA64ISAR1_API_IMP_DEF,
1619 		.matches = has_cpuid_feature,
1620 		.cpu_enable = cpu_enable_address_auth,
1621 	},
1622 	{
1623 		.desc = "Generic authentication (architected algorithm)",
1624 		.capability = ARM64_HAS_GENERIC_AUTH_ARCH,
1625 		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
1626 		.sys_reg = SYS_ID_AA64ISAR1_EL1,
1627 		.sign = FTR_UNSIGNED,
1628 		.field_pos = ID_AA64ISAR1_GPA_SHIFT,
1629 		.min_field_value = ID_AA64ISAR1_GPA_ARCHITECTED,
1630 		.matches = has_cpuid_feature,
1631 	},
1632 	{
1633 		.desc = "Generic authentication (IMP DEF algorithm)",
1634 		.capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF,
1635 		.type = ARM64_CPUCAP_SYSTEM_FEATURE,
1636 		.sys_reg = SYS_ID_AA64ISAR1_EL1,
1637 		.sign = FTR_UNSIGNED,
1638 		.field_pos = ID_AA64ISAR1_GPI_SHIFT,
1639 		.min_field_value = ID_AA64ISAR1_GPI_IMP_DEF,
1640 		.matches = has_cpuid_feature,
1641 	},
1642 #endif /* CONFIG_ARM64_PTR_AUTH */
1643 #ifdef CONFIG_ARM64_PSEUDO_NMI
1644 	{
1645 		/*
1646 		 * Depends on having GICv3
1647 		 */
1648 		.desc = "IRQ priority masking",
1649 		.capability = ARM64_HAS_IRQ_PRIO_MASKING,
1650 		.type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1651 		.matches = can_use_gic_priorities,
1652 		.sys_reg = SYS_ID_AA64PFR0_EL1,
1653 		.field_pos = ID_AA64PFR0_GIC_SHIFT,
1654 		.sign = FTR_UNSIGNED,
1655 		.min_field_value = 1,
1656 	},
1657 #endif
1658 	{},
1659 };
1660 
1661 #define HWCAP_CPUID_MATCH(reg, field, s, min_value)				\
1662 		.matches = has_cpuid_feature,					\
1663 		.sys_reg = reg,							\
1664 		.field_pos = field,						\
1665 		.sign = s,							\
1666 		.min_field_value = min_value,
1667 
1668 #define __HWCAP_CAP(name, cap_type, cap)					\
1669 		.desc = name,							\
1670 		.type = ARM64_CPUCAP_SYSTEM_FEATURE,				\
1671 		.hwcap_type = cap_type,						\
1672 		.hwcap = cap,							\
1673 
1674 #define HWCAP_CAP(reg, field, s, min_value, cap_type, cap)			\
1675 	{									\
1676 		__HWCAP_CAP(#cap, cap_type, cap)				\
1677 		HWCAP_CPUID_MATCH(reg, field, s, min_value)			\
1678 	}
1679 
1680 #define HWCAP_MULTI_CAP(list, cap_type, cap)					\
1681 	{									\
1682 		__HWCAP_CAP(#cap, cap_type, cap)				\
1683 		.matches = cpucap_multi_entry_cap_matches,			\
1684 		.match_list = list,						\
1685 	}
1686 
1687 #define HWCAP_CAP_MATCH(match, cap_type, cap)					\
1688 	{									\
1689 		__HWCAP_CAP(#cap, cap_type, cap)				\
1690 		.matches = match,						\
1691 	}
1692 
1693 #ifdef CONFIG_ARM64_PTR_AUTH
1694 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = {
1695 	{
1696 		HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_APA_SHIFT,
1697 				  FTR_UNSIGNED, ID_AA64ISAR1_APA_ARCHITECTED)
1698 	},
1699 	{
1700 		HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_API_SHIFT,
1701 				  FTR_UNSIGNED, ID_AA64ISAR1_API_IMP_DEF)
1702 	},
1703 	{},
1704 };
1705 
1706 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = {
1707 	{
1708 		HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPA_SHIFT,
1709 				  FTR_UNSIGNED, ID_AA64ISAR1_GPA_ARCHITECTED)
1710 	},
1711 	{
1712 		HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPI_SHIFT,
1713 				  FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP_DEF)
1714 	},
1715 	{},
1716 };
1717 #endif
1718 
1719 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
1720 	HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_PMULL),
1721 	HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AES),
1722 	HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA1),
1723 	HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2),
1724 	HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512),
1725 	HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32),
1726 	HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS),
1727 	HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM),
1728 	HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3),
1729 	HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3),
1730 	HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM4),
1731 	HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP),
1732 	HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM),
1733 	HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FLAGM),
1734 	HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2),
1735 	HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_FP),
1736 	HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FPHP),
1737 	HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD),
1738 	HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP),
1739 	HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT),
1740 	HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP),
1741 	HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP),
1742 	HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT),
1743 	HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA),
1744 	HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC),
1745 	HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC),
1746 	HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FRINTTS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FRINT),
1747 	HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_SB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SB),
1748 	HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT),
1749 #ifdef CONFIG_ARM64_SVE
1750 	HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, KERNEL_HWCAP_SVE),
1751 	HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SVEVER_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SVEVER_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2),
1752 	HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES, CAP_HWCAP, KERNEL_HWCAP_SVEAES),
1753 	HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES_PMULL, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL),
1754 	HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BITPERM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BITPERM, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM),
1755 	HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SHA3_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SHA3, CAP_HWCAP, KERNEL_HWCAP_SVESHA3),
1756 	HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SM4_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SM4, CAP_HWCAP, KERNEL_HWCAP_SVESM4),
1757 #endif
1758 	HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, KERNEL_HWCAP_SSBS),
1759 #ifdef CONFIG_ARM64_PTR_AUTH
1760 	HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA),
1761 	HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG),
1762 #endif
1763 	{},
1764 };
1765 
1766 #ifdef CONFIG_COMPAT
compat_has_neon(const struct arm64_cpu_capabilities * cap,int scope)1767 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope)
1768 {
1769 	/*
1770 	 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available,
1771 	 * in line with that of arm32 as in vfp_init(). We make sure that the
1772 	 * check is future proof, by making sure value is non-zero.
1773 	 */
1774 	u32 mvfr1;
1775 
1776 	WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
1777 	if (scope == SCOPE_SYSTEM)
1778 		mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1);
1779 	else
1780 		mvfr1 = read_sysreg_s(SYS_MVFR1_EL1);
1781 
1782 	return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDSP_SHIFT) &&
1783 		cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDINT_SHIFT) &&
1784 		cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_SIMDLS_SHIFT);
1785 }
1786 #endif
1787 
1788 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
1789 #ifdef CONFIG_COMPAT
1790 	HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON),
1791 	HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_SIMDFMAC_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4),
1792 	/* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */
1793 	HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP),
1794 	HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_FPDP_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3),
1795 	HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
1796 	HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
1797 	HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
1798 	HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
1799 	HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
1800 #endif
1801 	{},
1802 };
1803 
cap_set_elf_hwcap(const struct arm64_cpu_capabilities * cap)1804 static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
1805 {
1806 	switch (cap->hwcap_type) {
1807 	case CAP_HWCAP:
1808 		cpu_set_feature(cap->hwcap);
1809 		break;
1810 #ifdef CONFIG_COMPAT
1811 	case CAP_COMPAT_HWCAP:
1812 		compat_elf_hwcap |= (u32)cap->hwcap;
1813 		break;
1814 	case CAP_COMPAT_HWCAP2:
1815 		compat_elf_hwcap2 |= (u32)cap->hwcap;
1816 		break;
1817 #endif
1818 	default:
1819 		WARN_ON(1);
1820 		break;
1821 	}
1822 }
1823 
1824 /* Check if we have a particular HWCAP enabled */
cpus_have_elf_hwcap(const struct arm64_cpu_capabilities * cap)1825 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
1826 {
1827 	bool rc;
1828 
1829 	switch (cap->hwcap_type) {
1830 	case CAP_HWCAP:
1831 		rc = cpu_have_feature(cap->hwcap);
1832 		break;
1833 #ifdef CONFIG_COMPAT
1834 	case CAP_COMPAT_HWCAP:
1835 		rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
1836 		break;
1837 	case CAP_COMPAT_HWCAP2:
1838 		rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
1839 		break;
1840 #endif
1841 	default:
1842 		WARN_ON(1);
1843 		rc = false;
1844 	}
1845 
1846 	return rc;
1847 }
1848 
setup_elf_hwcaps(const struct arm64_cpu_capabilities * hwcaps)1849 static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
1850 {
1851 	/* We support emulation of accesses to CPU ID feature registers */
1852 	cpu_set_named_feature(CPUID);
1853 	for (; hwcaps->matches; hwcaps++)
1854 		if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps)))
1855 			cap_set_elf_hwcap(hwcaps);
1856 }
1857 
update_cpu_capabilities(u16 scope_mask)1858 static void update_cpu_capabilities(u16 scope_mask)
1859 {
1860 	int i;
1861 	const struct arm64_cpu_capabilities *caps;
1862 
1863 	scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
1864 	for (i = 0; i < ARM64_NCAPS; i++) {
1865 		caps = cpu_hwcaps_ptrs[i];
1866 		if (!caps || !(caps->type & scope_mask) ||
1867 		    cpus_have_cap(caps->capability) ||
1868 		    !caps->matches(caps, cpucap_default_scope(caps)))
1869 			continue;
1870 
1871 		if (caps->desc)
1872 			pr_info("detected: %s\n", caps->desc);
1873 		cpus_set_cap(caps->capability);
1874 
1875 		if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU))
1876 			set_bit(caps->capability, boot_capabilities);
1877 	}
1878 }
1879 
1880 /*
1881  * Enable all the available capabilities on this CPU. The capabilities
1882  * with BOOT_CPU scope are handled separately and hence skipped here.
1883  */
cpu_enable_non_boot_scope_capabilities(void * __unused)1884 static int cpu_enable_non_boot_scope_capabilities(void *__unused)
1885 {
1886 	int i;
1887 	u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU;
1888 
1889 	for_each_available_cap(i) {
1890 		const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[i];
1891 
1892 		if (WARN_ON(!cap))
1893 			continue;
1894 
1895 		if (!(cap->type & non_boot_scope))
1896 			continue;
1897 
1898 		if (cap->cpu_enable)
1899 			cap->cpu_enable(cap);
1900 	}
1901 	return 0;
1902 }
1903 
1904 /*
1905  * Run through the enabled capabilities and enable() it on all active
1906  * CPUs
1907  */
enable_cpu_capabilities(u16 scope_mask)1908 static void __init enable_cpu_capabilities(u16 scope_mask)
1909 {
1910 	int i;
1911 	const struct arm64_cpu_capabilities *caps;
1912 	bool boot_scope;
1913 
1914 	scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
1915 	boot_scope = !!(scope_mask & SCOPE_BOOT_CPU);
1916 
1917 	for (i = 0; i < ARM64_NCAPS; i++) {
1918 		unsigned int num;
1919 
1920 		caps = cpu_hwcaps_ptrs[i];
1921 		if (!caps || !(caps->type & scope_mask))
1922 			continue;
1923 		num = caps->capability;
1924 		if (!cpus_have_cap(num))
1925 			continue;
1926 
1927 		/* Ensure cpus_have_const_cap(num) works */
1928 		static_branch_enable(&cpu_hwcap_keys[num]);
1929 
1930 		if (boot_scope && caps->cpu_enable)
1931 			/*
1932 			 * Capabilities with SCOPE_BOOT_CPU scope are finalised
1933 			 * before any secondary CPU boots. Thus, each secondary
1934 			 * will enable the capability as appropriate via
1935 			 * check_local_cpu_capabilities(). The only exception is
1936 			 * the boot CPU, for which the capability must be
1937 			 * enabled here. This approach avoids costly
1938 			 * stop_machine() calls for this case.
1939 			 */
1940 			caps->cpu_enable(caps);
1941 	}
1942 
1943 	/*
1944 	 * For all non-boot scope capabilities, use stop_machine()
1945 	 * as it schedules the work allowing us to modify PSTATE,
1946 	 * instead of on_each_cpu() which uses an IPI, giving us a
1947 	 * PSTATE that disappears when we return.
1948 	 */
1949 	if (!boot_scope)
1950 		stop_machine(cpu_enable_non_boot_scope_capabilities,
1951 			     NULL, cpu_online_mask);
1952 }
1953 
1954 /*
1955  * Run through the list of capabilities to check for conflicts.
1956  * If the system has already detected a capability, take necessary
1957  * action on this CPU.
1958  *
1959  * Returns "false" on conflicts.
1960  */
verify_local_cpu_caps(u16 scope_mask)1961 static bool verify_local_cpu_caps(u16 scope_mask)
1962 {
1963 	int i;
1964 	bool cpu_has_cap, system_has_cap;
1965 	const struct arm64_cpu_capabilities *caps;
1966 
1967 	scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
1968 
1969 	for (i = 0; i < ARM64_NCAPS; i++) {
1970 		caps = cpu_hwcaps_ptrs[i];
1971 		if (!caps || !(caps->type & scope_mask))
1972 			continue;
1973 
1974 		cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU);
1975 		system_has_cap = cpus_have_cap(caps->capability);
1976 
1977 		if (system_has_cap) {
1978 			/*
1979 			 * Check if the new CPU misses an advertised feature,
1980 			 * which is not safe to miss.
1981 			 */
1982 			if (!cpu_has_cap && !cpucap_late_cpu_optional(caps))
1983 				break;
1984 			/*
1985 			 * We have to issue cpu_enable() irrespective of
1986 			 * whether the CPU has it or not, as it is enabeld
1987 			 * system wide. It is upto the call back to take
1988 			 * appropriate action on this CPU.
1989 			 */
1990 			if (caps->cpu_enable)
1991 				caps->cpu_enable(caps);
1992 		} else {
1993 			/*
1994 			 * Check if the CPU has this capability if it isn't
1995 			 * safe to have when the system doesn't.
1996 			 */
1997 			if (cpu_has_cap && !cpucap_late_cpu_permitted(caps))
1998 				break;
1999 		}
2000 	}
2001 
2002 	if (i < ARM64_NCAPS) {
2003 		pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n",
2004 			smp_processor_id(), caps->capability,
2005 			caps->desc, system_has_cap, cpu_has_cap);
2006 		return false;
2007 	}
2008 
2009 	return true;
2010 }
2011 
2012 /*
2013  * Check for CPU features that are used in early boot
2014  * based on the Boot CPU value.
2015  */
check_early_cpu_features(void)2016 static void check_early_cpu_features(void)
2017 {
2018 	verify_cpu_asid_bits();
2019 	/*
2020 	 * Early features are used by the kernel already. If there
2021 	 * is a conflict, we cannot proceed further.
2022 	 */
2023 	if (!verify_local_cpu_caps(SCOPE_BOOT_CPU))
2024 		cpu_panic_kernel();
2025 }
2026 
2027 static void
verify_local_elf_hwcaps(const struct arm64_cpu_capabilities * caps)2028 verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
2029 {
2030 
2031 	for (; caps->matches; caps++)
2032 		if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
2033 			pr_crit("CPU%d: missing HWCAP: %s\n",
2034 					smp_processor_id(), caps->desc);
2035 			cpu_die_early();
2036 		}
2037 }
2038 
verify_sve_features(void)2039 static void verify_sve_features(void)
2040 {
2041 	u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1);
2042 	u64 zcr = read_zcr_features();
2043 
2044 	unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK;
2045 	unsigned int len = zcr & ZCR_ELx_LEN_MASK;
2046 
2047 	if (len < safe_len || sve_verify_vq_map()) {
2048 		pr_crit("CPU%d: SVE: vector length support mismatch\n",
2049 			smp_processor_id());
2050 		cpu_die_early();
2051 	}
2052 
2053 	/* Add checks on other ZCR bits here if necessary */
2054 }
2055 
2056 
2057 /*
2058  * Run through the enabled system capabilities and enable() it on this CPU.
2059  * The capabilities were decided based on the available CPUs at the boot time.
2060  * Any new CPU should match the system wide status of the capability. If the
2061  * new CPU doesn't have a capability which the system now has enabled, we
2062  * cannot do anything to fix it up and could cause unexpected failures. So
2063  * we park the CPU.
2064  */
verify_local_cpu_capabilities(void)2065 static void verify_local_cpu_capabilities(void)
2066 {
2067 	/*
2068 	 * The capabilities with SCOPE_BOOT_CPU are checked from
2069 	 * check_early_cpu_features(), as they need to be verified
2070 	 * on all secondary CPUs.
2071 	 */
2072 	if (!verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU))
2073 		cpu_die_early();
2074 
2075 	verify_local_elf_hwcaps(arm64_elf_hwcaps);
2076 
2077 	if (system_supports_32bit_el0())
2078 		verify_local_elf_hwcaps(compat_elf_hwcaps);
2079 
2080 	if (system_supports_sve())
2081 		verify_sve_features();
2082 }
2083 
check_local_cpu_capabilities(void)2084 void check_local_cpu_capabilities(void)
2085 {
2086 	/*
2087 	 * All secondary CPUs should conform to the early CPU features
2088 	 * in use by the kernel based on boot CPU.
2089 	 */
2090 	check_early_cpu_features();
2091 
2092 	/*
2093 	 * If we haven't finalised the system capabilities, this CPU gets
2094 	 * a chance to update the errata work arounds and local features.
2095 	 * Otherwise, this CPU should verify that it has all the system
2096 	 * advertised capabilities.
2097 	 */
2098 	if (!sys_caps_initialised)
2099 		update_cpu_capabilities(SCOPE_LOCAL_CPU);
2100 	else
2101 		verify_local_cpu_capabilities();
2102 }
2103 
setup_boot_cpu_capabilities(void)2104 static void __init setup_boot_cpu_capabilities(void)
2105 {
2106 	/* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */
2107 	update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU);
2108 	/* Enable the SCOPE_BOOT_CPU capabilities alone right away */
2109 	enable_cpu_capabilities(SCOPE_BOOT_CPU);
2110 }
2111 
2112 DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready);
2113 EXPORT_SYMBOL(arm64_const_caps_ready);
2114 
mark_const_caps_ready(void)2115 static void __init mark_const_caps_ready(void)
2116 {
2117 	static_branch_enable(&arm64_const_caps_ready);
2118 }
2119 
this_cpu_has_cap(unsigned int n)2120 bool this_cpu_has_cap(unsigned int n)
2121 {
2122 	if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) {
2123 		const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n];
2124 
2125 		if (cap)
2126 			return cap->matches(cap, SCOPE_LOCAL_CPU);
2127 	}
2128 
2129 	return false;
2130 }
2131 
cpu_set_feature(unsigned int num)2132 void cpu_set_feature(unsigned int num)
2133 {
2134 	WARN_ON(num >= MAX_CPU_FEATURES);
2135 	elf_hwcap |= BIT(num);
2136 }
2137 EXPORT_SYMBOL_GPL(cpu_set_feature);
2138 
cpu_have_feature(unsigned int num)2139 bool cpu_have_feature(unsigned int num)
2140 {
2141 	WARN_ON(num >= MAX_CPU_FEATURES);
2142 	return elf_hwcap & BIT(num);
2143 }
2144 EXPORT_SYMBOL_GPL(cpu_have_feature);
2145 
cpu_get_elf_hwcap(void)2146 unsigned long cpu_get_elf_hwcap(void)
2147 {
2148 	/*
2149 	 * We currently only populate the first 32 bits of AT_HWCAP. Please
2150 	 * note that for userspace compatibility we guarantee that bits 62
2151 	 * and 63 will always be returned as 0.
2152 	 */
2153 	return lower_32_bits(elf_hwcap);
2154 }
2155 
cpu_get_elf_hwcap2(void)2156 unsigned long cpu_get_elf_hwcap2(void)
2157 {
2158 	return upper_32_bits(elf_hwcap);
2159 }
2160 
setup_system_capabilities(void)2161 static void __init setup_system_capabilities(void)
2162 {
2163 	/*
2164 	 * We have finalised the system-wide safe feature
2165 	 * registers, finalise the capabilities that depend
2166 	 * on it. Also enable all the available capabilities,
2167 	 * that are not enabled already.
2168 	 */
2169 	update_cpu_capabilities(SCOPE_SYSTEM);
2170 	enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU);
2171 }
2172 
setup_cpu_features(void)2173 void __init setup_cpu_features(void)
2174 {
2175 	u32 cwg;
2176 
2177 	setup_system_capabilities();
2178 	mark_const_caps_ready();
2179 	setup_elf_hwcaps(arm64_elf_hwcaps);
2180 
2181 	if (system_supports_32bit_el0()) {
2182 		setup_elf_hwcaps(compat_elf_hwcaps);
2183 		elf_hwcap_fixup();
2184 	}
2185 
2186 	if (system_uses_ttbr0_pan())
2187 		pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n");
2188 
2189 	sve_setup();
2190 	minsigstksz_setup();
2191 
2192 	/* Advertise that we have computed the system capabilities */
2193 	set_sys_caps_initialised();
2194 
2195 	/*
2196 	 * Check for sane CTR_EL0.CWG value.
2197 	 */
2198 	cwg = cache_type_cwg();
2199 	if (!cwg)
2200 		pr_warn("No Cache Writeback Granule information, assuming %d\n",
2201 			ARCH_DMA_MINALIGN);
2202 }
2203 
2204 static bool __maybe_unused
cpufeature_pan_not_uao(const struct arm64_cpu_capabilities * entry,int __unused)2205 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused)
2206 {
2207 	return (cpus_have_const_cap(ARM64_HAS_PAN) && !cpus_have_const_cap(ARM64_HAS_UAO));
2208 }
2209 
cpu_enable_cnp(struct arm64_cpu_capabilities const * cap)2210 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap)
2211 {
2212 	cpu_replace_ttbr1(lm_alias(swapper_pg_dir));
2213 }
2214 
2215 /*
2216  * We emulate only the following system register space.
2217  * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7]
2218  * See Table C5-6 System instruction encodings for System register accesses,
2219  * ARMv8 ARM(ARM DDI 0487A.f) for more details.
2220  */
is_emulated(u32 id)2221 static inline bool __attribute_const__ is_emulated(u32 id)
2222 {
2223 	return (sys_reg_Op0(id) == 0x3 &&
2224 		sys_reg_CRn(id) == 0x0 &&
2225 		sys_reg_Op1(id) == 0x0 &&
2226 		(sys_reg_CRm(id) == 0 ||
2227 		 ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7))));
2228 }
2229 
2230 /*
2231  * With CRm == 0, reg should be one of :
2232  * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1.
2233  */
emulate_id_reg(u32 id,u64 * valp)2234 static inline int emulate_id_reg(u32 id, u64 *valp)
2235 {
2236 	switch (id) {
2237 	case SYS_MIDR_EL1:
2238 		*valp = read_cpuid_id();
2239 		break;
2240 	case SYS_MPIDR_EL1:
2241 		*valp = SYS_MPIDR_SAFE_VAL;
2242 		break;
2243 	case SYS_REVIDR_EL1:
2244 		/* IMPLEMENTATION DEFINED values are emulated with 0 */
2245 		*valp = 0;
2246 		break;
2247 	default:
2248 		return -EINVAL;
2249 	}
2250 
2251 	return 0;
2252 }
2253 
emulate_sys_reg(u32 id,u64 * valp)2254 static int emulate_sys_reg(u32 id, u64 *valp)
2255 {
2256 	struct arm64_ftr_reg *regp;
2257 
2258 	if (!is_emulated(id))
2259 		return -EINVAL;
2260 
2261 	if (sys_reg_CRm(id) == 0)
2262 		return emulate_id_reg(id, valp);
2263 
2264 	regp = get_arm64_ftr_reg(id);
2265 	if (regp)
2266 		*valp = arm64_ftr_reg_user_value(regp);
2267 	else
2268 		/*
2269 		 * The untracked registers are either IMPLEMENTATION DEFINED
2270 		 * (e.g, ID_AFR0_EL1) or reserved RAZ.
2271 		 */
2272 		*valp = 0;
2273 	return 0;
2274 }
2275 
do_emulate_mrs(struct pt_regs * regs,u32 sys_reg,u32 rt)2276 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt)
2277 {
2278 	int rc;
2279 	u64 val;
2280 
2281 	rc = emulate_sys_reg(sys_reg, &val);
2282 	if (!rc) {
2283 		pt_regs_write_reg(regs, rt, val);
2284 		arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
2285 	}
2286 	return rc;
2287 }
2288 
emulate_mrs(struct pt_regs * regs,u32 insn)2289 static int emulate_mrs(struct pt_regs *regs, u32 insn)
2290 {
2291 	u32 sys_reg, rt;
2292 
2293 	/*
2294 	 * sys_reg values are defined as used in mrs/msr instruction.
2295 	 * shift the imm value to get the encoding.
2296 	 */
2297 	sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5;
2298 	rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
2299 	return do_emulate_mrs(regs, sys_reg, rt);
2300 }
2301 
2302 static struct undef_hook mrs_hook = {
2303 	.instr_mask = 0xfff00000,
2304 	.instr_val  = 0xd5300000,
2305 	.pstate_mask = PSR_AA32_MODE_MASK,
2306 	.pstate_val = PSR_MODE_EL0t,
2307 	.fn = emulate_mrs,
2308 };
2309 
enable_mrs_emulation(void)2310 static int __init enable_mrs_emulation(void)
2311 {
2312 	register_undef_hook(&mrs_hook);
2313 	return 0;
2314 }
2315 
2316 core_initcall(enable_mrs_emulation);
2317 
cpu_show_meltdown(struct device * dev,struct device_attribute * attr,char * buf)2318 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr,
2319 			  char *buf)
2320 {
2321 	if (__meltdown_safe)
2322 		return sprintf(buf, "Not affected\n");
2323 
2324 	if (arm64_kernel_unmapped_at_el0())
2325 		return sprintf(buf, "Mitigation: PTI\n");
2326 
2327 	return sprintf(buf, "Vulnerable\n");
2328 }
2329