1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
4 */
5
6 #include <linux/seq_file.h>
7 #include <linux/fs.h>
8 #include <linux/delay.h>
9 #include <linux/root_dev.h>
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
12 #include <linux/clocksource.h>
13 #include <linux/console.h>
14 #include <linux/module.h>
15 #include <linux/sizes.h>
16 #include <linux/cpu.h>
17 #include <linux/of_fdt.h>
18 #include <linux/of.h>
19 #include <linux/cache.h>
20 #include <uapi/linux/mount.h>
21 #include <asm/sections.h>
22 #include <asm/arcregs.h>
23 #include <asm/tlb.h>
24 #include <asm/setup.h>
25 #include <asm/page.h>
26 #include <asm/irq.h>
27 #include <asm/unwind.h>
28 #include <asm/mach_desc.h>
29 #include <asm/smp.h>
30
31 #define FIX_PTR(x) __asm__ __volatile__(";" : "+r"(x))
32
33 unsigned int intr_to_DE_cnt;
34
35 /* Part of U-boot ABI: see head.S */
36 int __initdata uboot_tag;
37 int __initdata uboot_magic;
38 char __initdata *uboot_arg;
39
40 const struct machine_desc *machine_desc;
41
42 struct task_struct *_current_task[NR_CPUS]; /* For stack switching */
43
44 struct cpuinfo_arc cpuinfo_arc700[NR_CPUS];
45
46 static const struct id_to_str arc_legacy_rel[] = {
47 /* ID.ARCVER, Release */
48 #ifdef CONFIG_ISA_ARCOMPACT
49 { 0x34, "R4.10"},
50 { 0x35, "R4.11"},
51 #else
52 { 0x51, "R2.0" },
53 { 0x52, "R2.1" },
54 { 0x53, "R3.0" },
55 #endif
56 { 0x00, NULL }
57 };
58
59 static const struct id_to_str arc_cpu_rel[] = {
60 /* UARCH.MAJOR, Release */
61 { 0, "R3.10a"},
62 { 1, "R3.50a"},
63 { 0xFF, NULL }
64 };
65
read_decode_ccm_bcr(struct cpuinfo_arc * cpu)66 static void read_decode_ccm_bcr(struct cpuinfo_arc *cpu)
67 {
68 if (is_isa_arcompact()) {
69 struct bcr_iccm_arcompact iccm;
70 struct bcr_dccm_arcompact dccm;
71
72 READ_BCR(ARC_REG_ICCM_BUILD, iccm);
73 if (iccm.ver) {
74 cpu->iccm.sz = 4096 << iccm.sz; /* 8K to 512K */
75 cpu->iccm.base_addr = iccm.base << 16;
76 }
77
78 READ_BCR(ARC_REG_DCCM_BUILD, dccm);
79 if (dccm.ver) {
80 unsigned long base;
81 cpu->dccm.sz = 2048 << dccm.sz; /* 2K to 256K */
82
83 base = read_aux_reg(ARC_REG_DCCM_BASE_BUILD);
84 cpu->dccm.base_addr = base & ~0xF;
85 }
86 } else {
87 struct bcr_iccm_arcv2 iccm;
88 struct bcr_dccm_arcv2 dccm;
89 unsigned long region;
90
91 READ_BCR(ARC_REG_ICCM_BUILD, iccm);
92 if (iccm.ver) {
93 cpu->iccm.sz = 256 << iccm.sz00; /* 512B to 16M */
94 if (iccm.sz00 == 0xF && iccm.sz01 > 0)
95 cpu->iccm.sz <<= iccm.sz01;
96
97 region = read_aux_reg(ARC_REG_AUX_ICCM);
98 cpu->iccm.base_addr = region & 0xF0000000;
99 }
100
101 READ_BCR(ARC_REG_DCCM_BUILD, dccm);
102 if (dccm.ver) {
103 cpu->dccm.sz = 256 << dccm.sz0;
104 if (dccm.sz0 == 0xF && dccm.sz1 > 0)
105 cpu->dccm.sz <<= dccm.sz1;
106
107 region = read_aux_reg(ARC_REG_AUX_DCCM);
108 cpu->dccm.base_addr = region & 0xF0000000;
109 }
110 }
111 }
112
decode_arc_core(struct cpuinfo_arc * cpu)113 static void decode_arc_core(struct cpuinfo_arc *cpu)
114 {
115 struct bcr_uarch_build_arcv2 uarch;
116 const struct id_to_str *tbl;
117
118 /*
119 * Up until (including) the first core4 release (0x54) things were
120 * simple: AUX IDENTITY.ARCVER was sufficient to identify arc family
121 * and release: 0x50 to 0x53 was HS38, 0x54 was HS48 (dual issue)
122 */
123
124 if (cpu->core.family < 0x54) { /* includes arc700 */
125
126 for (tbl = &arc_legacy_rel[0]; tbl->id != 0; tbl++) {
127 if (cpu->core.family == tbl->id) {
128 cpu->release = tbl->str;
129 break;
130 }
131 }
132
133 if (is_isa_arcompact())
134 cpu->name = "ARC700";
135 else if (tbl->str)
136 cpu->name = "HS38";
137 else
138 cpu->name = cpu->release = "Unknown";
139
140 return;
141 }
142
143 /*
144 * However the subsequent HS release (same 0x54) allow HS38 or HS48
145 * configurations and encode this info in a different BCR.
146 * The BCR was introduced in 0x54 so can't be read unconditionally.
147 */
148
149 READ_BCR(ARC_REG_MICRO_ARCH_BCR, uarch);
150
151 if (uarch.prod == 4) {
152 cpu->name = "HS48";
153 cpu->extn.dual = 1;
154
155 } else {
156 cpu->name = "HS38";
157 }
158
159 for (tbl = &arc_cpu_rel[0]; tbl->id != 0xFF; tbl++) {
160 if (uarch.maj == tbl->id) {
161 cpu->release = tbl->str;
162 break;
163 }
164 }
165 }
166
read_arc_build_cfg_regs(void)167 static void read_arc_build_cfg_regs(void)
168 {
169 struct bcr_timer timer;
170 struct bcr_generic bcr;
171 struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
172 struct bcr_isa_arcv2 isa;
173 struct bcr_actionpoint ap;
174
175 FIX_PTR(cpu);
176
177 READ_BCR(AUX_IDENTITY, cpu->core);
178 decode_arc_core(cpu);
179
180 READ_BCR(ARC_REG_TIMERS_BCR, timer);
181 cpu->extn.timer0 = timer.t0;
182 cpu->extn.timer1 = timer.t1;
183 cpu->extn.rtc = timer.rtc;
184
185 cpu->vec_base = read_aux_reg(AUX_INTR_VEC_BASE);
186
187 READ_BCR(ARC_REG_MUL_BCR, cpu->extn_mpy);
188
189 /* Read CCM BCRs for boot reporting even if not enabled in Kconfig */
190 read_decode_ccm_bcr(cpu);
191
192 read_decode_mmu_bcr();
193 read_decode_cache_bcr();
194
195 if (is_isa_arcompact()) {
196 struct bcr_fp_arcompact sp, dp;
197 struct bcr_bpu_arcompact bpu;
198
199 READ_BCR(ARC_REG_FP_BCR, sp);
200 READ_BCR(ARC_REG_DPFP_BCR, dp);
201 cpu->extn.fpu_sp = sp.ver ? 1 : 0;
202 cpu->extn.fpu_dp = dp.ver ? 1 : 0;
203
204 READ_BCR(ARC_REG_BPU_BCR, bpu);
205 cpu->bpu.ver = bpu.ver;
206 cpu->bpu.full = bpu.fam ? 1 : 0;
207 if (bpu.ent) {
208 cpu->bpu.num_cache = 256 << (bpu.ent - 1);
209 cpu->bpu.num_pred = 256 << (bpu.ent - 1);
210 }
211 } else {
212 struct bcr_fp_arcv2 spdp;
213 struct bcr_bpu_arcv2 bpu;
214
215 READ_BCR(ARC_REG_FP_V2_BCR, spdp);
216 cpu->extn.fpu_sp = spdp.sp ? 1 : 0;
217 cpu->extn.fpu_dp = spdp.dp ? 1 : 0;
218
219 READ_BCR(ARC_REG_BPU_BCR, bpu);
220 cpu->bpu.ver = bpu.ver;
221 cpu->bpu.full = bpu.ft;
222 cpu->bpu.num_cache = 256 << bpu.bce;
223 cpu->bpu.num_pred = 2048 << bpu.pte;
224 cpu->bpu.ret_stk = 4 << bpu.rse;
225
226 /* if dual issue hardware, is it enabled ? */
227 if (cpu->extn.dual) {
228 unsigned int exec_ctrl;
229
230 READ_BCR(AUX_EXEC_CTRL, exec_ctrl);
231 cpu->extn.dual_enb = !(exec_ctrl & 1);
232 }
233 }
234
235 READ_BCR(ARC_REG_AP_BCR, ap);
236 if (ap.ver) {
237 cpu->extn.ap_num = 2 << ap.num;
238 cpu->extn.ap_full = !ap.min;
239 }
240
241 READ_BCR(ARC_REG_SMART_BCR, bcr);
242 cpu->extn.smart = bcr.ver ? 1 : 0;
243
244 READ_BCR(ARC_REG_RTT_BCR, bcr);
245 cpu->extn.rtt = bcr.ver ? 1 : 0;
246
247 READ_BCR(ARC_REG_ISA_CFG_BCR, isa);
248
249 /* some hacks for lack of feature BCR info in old ARC700 cores */
250 if (is_isa_arcompact()) {
251 if (!isa.ver) /* ISA BCR absent, use Kconfig info */
252 cpu->isa.atomic = IS_ENABLED(CONFIG_ARC_HAS_LLSC);
253 else {
254 /* ARC700_BUILD only has 2 bits of isa info */
255 struct bcr_generic bcr = *(struct bcr_generic *)&isa;
256 cpu->isa.atomic = bcr.info & 1;
257 }
258
259 cpu->isa.be = IS_ENABLED(CONFIG_CPU_BIG_ENDIAN);
260
261 /* there's no direct way to distinguish 750 vs. 770 */
262 if (unlikely(cpu->core.family < 0x34 || cpu->mmu.ver < 3))
263 cpu->name = "ARC750";
264 } else {
265 cpu->isa = isa;
266 }
267 }
268
arc_cpu_mumbojumbo(int cpu_id,char * buf,int len)269 static char *arc_cpu_mumbojumbo(int cpu_id, char *buf, int len)
270 {
271 struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id];
272 struct bcr_identity *core = &cpu->core;
273 char mpy_opt[16];
274 int n = 0;
275
276 FIX_PTR(cpu);
277
278 n += scnprintf(buf + n, len - n,
279 "\nIDENTITY\t: ARCVER [%#02x] ARCNUM [%#02x] CHIPID [%#4x]\n",
280 core->family, core->cpu_id, core->chip_id);
281
282 n += scnprintf(buf + n, len - n, "processor [%d]\t: %s %s (%s ISA) %s%s%s\n",
283 cpu_id, cpu->name, cpu->release,
284 is_isa_arcompact() ? "ARCompact" : "ARCv2",
285 IS_AVAIL1(cpu->isa.be, "[Big-Endian]"),
286 IS_AVAIL3(cpu->extn.dual, cpu->extn.dual_enb, " Dual-Issue "));
287
288 n += scnprintf(buf + n, len - n, "Timers\t\t: %s%s%s%s%s%s\nISA Extn\t: ",
289 IS_AVAIL1(cpu->extn.timer0, "Timer0 "),
290 IS_AVAIL1(cpu->extn.timer1, "Timer1 "),
291 IS_AVAIL2(cpu->extn.rtc, "RTC [UP 64-bit] ", CONFIG_ARC_TIMERS_64BIT),
292 IS_AVAIL2(cpu->extn.gfrc, "GFRC [SMP 64-bit] ", CONFIG_ARC_TIMERS_64BIT));
293
294 if (cpu->extn_mpy.ver) {
295 if (is_isa_arcompact()) {
296 scnprintf(mpy_opt, 16, "mpy");
297 } else {
298
299 int opt = 2; /* stock MPY/MPYH */
300
301 if (cpu->extn_mpy.dsp) /* OPT 7-9 */
302 opt = cpu->extn_mpy.dsp + 6;
303
304 scnprintf(mpy_opt, 16, "mpy[opt %d] ", opt);
305 }
306 }
307
308 n += scnprintf(buf + n, len - n, "%s%s%s%s%s%s%s%s\n",
309 IS_AVAIL2(cpu->isa.atomic, "atomic ", CONFIG_ARC_HAS_LLSC),
310 IS_AVAIL2(cpu->isa.ldd, "ll64 ", CONFIG_ARC_HAS_LL64),
311 IS_AVAIL2(cpu->isa.unalign, "unalign ", CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS),
312 IS_AVAIL1(cpu->extn_mpy.ver, mpy_opt),
313 IS_AVAIL1(cpu->isa.div_rem, "div_rem "));
314
315 if (cpu->bpu.ver) {
316 n += scnprintf(buf + n, len - n,
317 "BPU\t\t: %s%s match, cache:%d, Predict Table:%d Return stk: %d",
318 IS_AVAIL1(cpu->bpu.full, "full"),
319 IS_AVAIL1(!cpu->bpu.full, "partial"),
320 cpu->bpu.num_cache, cpu->bpu.num_pred, cpu->bpu.ret_stk);
321
322 if (is_isa_arcv2()) {
323 struct bcr_lpb lpb;
324
325 READ_BCR(ARC_REG_LPB_BUILD, lpb);
326 if (lpb.ver) {
327 unsigned int ctl;
328 ctl = read_aux_reg(ARC_REG_LPB_CTRL);
329
330 n += scnprintf(buf + n, len - n, " Loop Buffer:%d %s",
331 lpb.entries,
332 IS_DISABLED_RUN(!ctl));
333 }
334 }
335 n += scnprintf(buf + n, len - n, "\n");
336 }
337
338 return buf;
339 }
340
arc_extn_mumbojumbo(int cpu_id,char * buf,int len)341 static char *arc_extn_mumbojumbo(int cpu_id, char *buf, int len)
342 {
343 int n = 0;
344 struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id];
345
346 FIX_PTR(cpu);
347
348 n += scnprintf(buf + n, len - n, "Vector Table\t: %#x\n", cpu->vec_base);
349
350 if (cpu->extn.fpu_sp || cpu->extn.fpu_dp)
351 n += scnprintf(buf + n, len - n, "FPU\t\t: %s%s\n",
352 IS_AVAIL1(cpu->extn.fpu_sp, "SP "),
353 IS_AVAIL1(cpu->extn.fpu_dp, "DP "));
354
355 if (cpu->extn.ap_num | cpu->extn.smart | cpu->extn.rtt) {
356 n += scnprintf(buf + n, len - n, "DEBUG\t\t: %s%s",
357 IS_AVAIL1(cpu->extn.smart, "smaRT "),
358 IS_AVAIL1(cpu->extn.rtt, "RTT "));
359 if (cpu->extn.ap_num) {
360 n += scnprintf(buf + n, len - n, "ActionPoint %d/%s",
361 cpu->extn.ap_num,
362 cpu->extn.ap_full ? "full":"min");
363 }
364 n += scnprintf(buf + n, len - n, "\n");
365 }
366
367 if (cpu->dccm.sz || cpu->iccm.sz)
368 n += scnprintf(buf + n, len - n, "Extn [CCM]\t: DCCM @ %x, %d KB / ICCM: @ %x, %d KB\n",
369 cpu->dccm.base_addr, TO_KB(cpu->dccm.sz),
370 cpu->iccm.base_addr, TO_KB(cpu->iccm.sz));
371
372 if (is_isa_arcv2()) {
373
374 /* Error Protection: ECC/Parity */
375 struct bcr_erp erp;
376 READ_BCR(ARC_REG_ERP_BUILD, erp);
377
378 if (erp.ver) {
379 struct ctl_erp ctl;
380 READ_BCR(ARC_REG_ERP_CTRL, ctl);
381
382 /* inverted bits: 0 means enabled */
383 n += scnprintf(buf + n, len - n, "Extn [ECC]\t: %s%s%s%s%s%s\n",
384 IS_AVAIL3(erp.ic, !ctl.dpi, "IC "),
385 IS_AVAIL3(erp.dc, !ctl.dpd, "DC "),
386 IS_AVAIL3(erp.mmu, !ctl.mpd, "MMU "));
387 }
388 }
389
390 return buf;
391 }
392
arc_chk_core_config(void)393 static void arc_chk_core_config(void)
394 {
395 struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
396 int saved = 0, present = 0;
397 char *opt_nm = NULL;
398
399 if (!cpu->extn.timer0)
400 panic("Timer0 is not present!\n");
401
402 if (!cpu->extn.timer1)
403 panic("Timer1 is not present!\n");
404
405 #ifdef CONFIG_ARC_HAS_DCCM
406 /*
407 * DCCM can be arbit placed in hardware.
408 * Make sure it's placement/sz matches what Linux is built with
409 */
410 if ((unsigned int)__arc_dccm_base != cpu->dccm.base_addr)
411 panic("Linux built with incorrect DCCM Base address\n");
412
413 if (CONFIG_ARC_DCCM_SZ * SZ_1K != cpu->dccm.sz)
414 panic("Linux built with incorrect DCCM Size\n");
415 #endif
416
417 #ifdef CONFIG_ARC_HAS_ICCM
418 if (CONFIG_ARC_ICCM_SZ * SZ_1K != cpu->iccm.sz)
419 panic("Linux built with incorrect ICCM Size\n");
420 #endif
421
422 /*
423 * FP hardware/software config sanity
424 * -If hardware present, kernel needs to save/restore FPU state
425 * -If not, it will crash trying to save/restore the non-existant regs
426 */
427
428 if (is_isa_arcompact()) {
429 opt_nm = "CONFIG_ARC_FPU_SAVE_RESTORE";
430 saved = IS_ENABLED(CONFIG_ARC_FPU_SAVE_RESTORE);
431
432 /* only DPDP checked since SP has no arch visible regs */
433 present = cpu->extn.fpu_dp;
434 } else {
435 opt_nm = "CONFIG_ARC_HAS_ACCL_REGS";
436 saved = IS_ENABLED(CONFIG_ARC_HAS_ACCL_REGS);
437
438 /* Accumulator Low:High pair (r58:59) present if DSP MPY or FPU */
439 present = cpu->extn_mpy.dsp | cpu->extn.fpu_sp | cpu->extn.fpu_dp;
440 }
441
442 if (present && !saved)
443 pr_warn("Enable %s for working apps\n", opt_nm);
444 else if (!present && saved)
445 panic("Disable %s, hardware NOT present\n", opt_nm);
446 }
447
448 /*
449 * Initialize and setup the processor core
450 * This is called by all the CPUs thus should not do special case stuff
451 * such as only for boot CPU etc
452 */
453
setup_processor(void)454 void setup_processor(void)
455 {
456 char str[512];
457 int cpu_id = smp_processor_id();
458
459 read_arc_build_cfg_regs();
460 arc_init_IRQ();
461
462 pr_info("%s", arc_cpu_mumbojumbo(cpu_id, str, sizeof(str)));
463
464 arc_mmu_init();
465 arc_cache_init();
466
467 pr_info("%s", arc_extn_mumbojumbo(cpu_id, str, sizeof(str)));
468 pr_info("%s", arc_platform_smp_cpuinfo());
469
470 arc_chk_core_config();
471 }
472
uboot_arg_invalid(unsigned long addr)473 static inline bool uboot_arg_invalid(unsigned long addr)
474 {
475 /*
476 * Check that it is a untranslated address (although MMU is not enabled
477 * yet, it being a high address ensures this is not by fluke)
478 */
479 if (addr < PAGE_OFFSET)
480 return true;
481
482 /* Check that address doesn't clobber resident kernel image */
483 return addr >= (unsigned long)_stext && addr <= (unsigned long)_end;
484 }
485
486 #define IGNORE_ARGS "Ignore U-boot args: "
487
488 /* uboot_tag values for U-boot - kernel ABI revision 0; see head.S */
489 #define UBOOT_TAG_NONE 0
490 #define UBOOT_TAG_CMDLINE 1
491 #define UBOOT_TAG_DTB 2
492 /* We always pass 0 as magic from U-boot */
493 #define UBOOT_MAGIC_VALUE 0
494
handle_uboot_args(void)495 void __init handle_uboot_args(void)
496 {
497 bool use_embedded_dtb = true;
498 bool append_cmdline = false;
499
500 /* check that we know this tag */
501 if (uboot_tag != UBOOT_TAG_NONE &&
502 uboot_tag != UBOOT_TAG_CMDLINE &&
503 uboot_tag != UBOOT_TAG_DTB) {
504 pr_warn(IGNORE_ARGS "invalid uboot tag: '%08x'\n", uboot_tag);
505 goto ignore_uboot_args;
506 }
507
508 if (uboot_magic != UBOOT_MAGIC_VALUE) {
509 pr_warn(IGNORE_ARGS "non zero uboot magic\n");
510 goto ignore_uboot_args;
511 }
512
513 if (uboot_tag != UBOOT_TAG_NONE &&
514 uboot_arg_invalid((unsigned long)uboot_arg)) {
515 pr_warn(IGNORE_ARGS "invalid uboot arg: '%px'\n", uboot_arg);
516 goto ignore_uboot_args;
517 }
518
519 /* see if U-boot passed an external Device Tree blob */
520 if (uboot_tag == UBOOT_TAG_DTB) {
521 machine_desc = setup_machine_fdt((void *)uboot_arg);
522
523 /* external Device Tree blob is invalid - use embedded one */
524 use_embedded_dtb = !machine_desc;
525 }
526
527 if (uboot_tag == UBOOT_TAG_CMDLINE)
528 append_cmdline = true;
529
530 ignore_uboot_args:
531
532 if (use_embedded_dtb) {
533 machine_desc = setup_machine_fdt(__dtb_start);
534 if (!machine_desc)
535 panic("Embedded DT invalid\n");
536 }
537
538 /*
539 * NOTE: @boot_command_line is populated by setup_machine_fdt() so this
540 * append processing can only happen after.
541 */
542 if (append_cmdline) {
543 /* Ensure a whitespace between the 2 cmdlines */
544 strlcat(boot_command_line, " ", COMMAND_LINE_SIZE);
545 strlcat(boot_command_line, uboot_arg, COMMAND_LINE_SIZE);
546 }
547 }
548
setup_arch(char ** cmdline_p)549 void __init setup_arch(char **cmdline_p)
550 {
551 handle_uboot_args();
552
553 /* Save unparsed command line copy for /proc/cmdline */
554 *cmdline_p = boot_command_line;
555
556 /* To force early parsing of things like mem=xxx */
557 parse_early_param();
558
559 /* Platform/board specific: e.g. early console registration */
560 if (machine_desc->init_early)
561 machine_desc->init_early();
562
563 smp_init_cpus();
564
565 setup_processor();
566 setup_arch_memory();
567
568 /* copy flat DT out of .init and then unflatten it */
569 unflatten_and_copy_device_tree();
570
571 /* Can be issue if someone passes cmd line arg "ro"
572 * But that is unlikely so keeping it as it is
573 */
574 root_mountflags &= ~MS_RDONLY;
575
576 #if defined(CONFIG_VT) && defined(CONFIG_DUMMY_CONSOLE)
577 conswitchp = &dummy_con;
578 #endif
579
580 arc_unwind_init();
581 }
582
583 /*
584 * Called from start_kernel() - boot CPU only
585 */
time_init(void)586 void __init time_init(void)
587 {
588 of_clk_init(NULL);
589 timer_probe();
590 }
591
customize_machine(void)592 static int __init customize_machine(void)
593 {
594 if (machine_desc->init_machine)
595 machine_desc->init_machine();
596
597 return 0;
598 }
599 arch_initcall(customize_machine);
600
init_late_machine(void)601 static int __init init_late_machine(void)
602 {
603 if (machine_desc->init_late)
604 machine_desc->init_late();
605
606 return 0;
607 }
608 late_initcall(init_late_machine);
609 /*
610 * Get CPU information for use by the procfs.
611 */
612
613 #define cpu_to_ptr(c) ((void *)(0xFFFF0000 | (unsigned int)(c)))
614 #define ptr_to_cpu(p) (~0xFFFF0000UL & (unsigned int)(p))
615
show_cpuinfo(struct seq_file * m,void * v)616 static int show_cpuinfo(struct seq_file *m, void *v)
617 {
618 char *str;
619 int cpu_id = ptr_to_cpu(v);
620 struct device *cpu_dev = get_cpu_device(cpu_id);
621 struct clk *cpu_clk;
622 unsigned long freq = 0;
623
624 if (!cpu_online(cpu_id)) {
625 seq_printf(m, "processor [%d]\t: Offline\n", cpu_id);
626 goto done;
627 }
628
629 str = (char *)__get_free_page(GFP_KERNEL);
630 if (!str)
631 goto done;
632
633 seq_printf(m, arc_cpu_mumbojumbo(cpu_id, str, PAGE_SIZE));
634
635 cpu_clk = clk_get(cpu_dev, NULL);
636 if (IS_ERR(cpu_clk)) {
637 seq_printf(m, "CPU speed \t: Cannot get clock for processor [%d]\n",
638 cpu_id);
639 } else {
640 freq = clk_get_rate(cpu_clk);
641 }
642 if (freq)
643 seq_printf(m, "CPU speed\t: %lu.%02lu Mhz\n",
644 freq / 1000000, (freq / 10000) % 100);
645
646 seq_printf(m, "Bogo MIPS\t: %lu.%02lu\n",
647 loops_per_jiffy / (500000 / HZ),
648 (loops_per_jiffy / (5000 / HZ)) % 100);
649
650 seq_printf(m, arc_mmu_mumbojumbo(cpu_id, str, PAGE_SIZE));
651 seq_printf(m, arc_cache_mumbojumbo(cpu_id, str, PAGE_SIZE));
652 seq_printf(m, arc_extn_mumbojumbo(cpu_id, str, PAGE_SIZE));
653 seq_printf(m, arc_platform_smp_cpuinfo());
654
655 free_page((unsigned long)str);
656 done:
657 seq_printf(m, "\n");
658
659 return 0;
660 }
661
c_start(struct seq_file * m,loff_t * pos)662 static void *c_start(struct seq_file *m, loff_t *pos)
663 {
664 /*
665 * Callback returns cpu-id to iterator for show routine, NULL to stop.
666 * However since NULL is also a valid cpu-id (0), we use a round-about
667 * way to pass it w/o having to kmalloc/free a 2 byte string.
668 * Encode cpu-id as 0xFFcccc, which is decoded by show routine.
669 */
670 return *pos < nr_cpu_ids ? cpu_to_ptr(*pos) : NULL;
671 }
672
c_next(struct seq_file * m,void * v,loff_t * pos)673 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
674 {
675 ++*pos;
676 return c_start(m, pos);
677 }
678
c_stop(struct seq_file * m,void * v)679 static void c_stop(struct seq_file *m, void *v)
680 {
681 }
682
683 const struct seq_operations cpuinfo_op = {
684 .start = c_start,
685 .next = c_next,
686 .stop = c_stop,
687 .show = show_cpuinfo
688 };
689
690 static DEFINE_PER_CPU(struct cpu, cpu_topology);
691
topology_init(void)692 static int __init topology_init(void)
693 {
694 int cpu;
695
696 for_each_present_cpu(cpu)
697 register_cpu(&per_cpu(cpu_topology, cpu), cpu);
698
699 return 0;
700 }
701
702 subsys_initcall(topology_init);
703