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1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Copyright IBM Corporation 2001, 2005, 2006
4  * Copyright Dave Engebretsen & Todd Inglett 2001
5  * Copyright Linas Vepstas 2005, 2006
6  * Copyright 2001-2012 IBM Corporation.
7  *
8  * Please address comments and feedback to Linas Vepstas <linas@austin.ibm.com>
9  */
10 
11 #include <linux/delay.h>
12 #include <linux/sched.h>
13 #include <linux/init.h>
14 #include <linux/list.h>
15 #include <linux/pci.h>
16 #include <linux/iommu.h>
17 #include <linux/proc_fs.h>
18 #include <linux/rbtree.h>
19 #include <linux/reboot.h>
20 #include <linux/seq_file.h>
21 #include <linux/spinlock.h>
22 #include <linux/export.h>
23 #include <linux/of.h>
24 
25 #include <linux/atomic.h>
26 #include <asm/debugfs.h>
27 #include <asm/eeh.h>
28 #include <asm/eeh_event.h>
29 #include <asm/io.h>
30 #include <asm/iommu.h>
31 #include <asm/machdep.h>
32 #include <asm/ppc-pci.h>
33 #include <asm/rtas.h>
34 #include <asm/pte-walk.h>
35 
36 
37 /** Overview:
38  *  EEH, or "Enhanced Error Handling" is a PCI bridge technology for
39  *  dealing with PCI bus errors that can't be dealt with within the
40  *  usual PCI framework, except by check-stopping the CPU.  Systems
41  *  that are designed for high-availability/reliability cannot afford
42  *  to crash due to a "mere" PCI error, thus the need for EEH.
43  *  An EEH-capable bridge operates by converting a detected error
44  *  into a "slot freeze", taking the PCI adapter off-line, making
45  *  the slot behave, from the OS'es point of view, as if the slot
46  *  were "empty": all reads return 0xff's and all writes are silently
47  *  ignored.  EEH slot isolation events can be triggered by parity
48  *  errors on the address or data busses (e.g. during posted writes),
49  *  which in turn might be caused by low voltage on the bus, dust,
50  *  vibration, humidity, radioactivity or plain-old failed hardware.
51  *
52  *  Note, however, that one of the leading causes of EEH slot
53  *  freeze events are buggy device drivers, buggy device microcode,
54  *  or buggy device hardware.  This is because any attempt by the
55  *  device to bus-master data to a memory address that is not
56  *  assigned to the device will trigger a slot freeze.   (The idea
57  *  is to prevent devices-gone-wild from corrupting system memory).
58  *  Buggy hardware/drivers will have a miserable time co-existing
59  *  with EEH.
60  *
61  *  Ideally, a PCI device driver, when suspecting that an isolation
62  *  event has occurred (e.g. by reading 0xff's), will then ask EEH
63  *  whether this is the case, and then take appropriate steps to
64  *  reset the PCI slot, the PCI device, and then resume operations.
65  *  However, until that day,  the checking is done here, with the
66  *  eeh_check_failure() routine embedded in the MMIO macros.  If
67  *  the slot is found to be isolated, an "EEH Event" is synthesized
68  *  and sent out for processing.
69  */
70 
71 /* If a device driver keeps reading an MMIO register in an interrupt
72  * handler after a slot isolation event, it might be broken.
73  * This sets the threshold for how many read attempts we allow
74  * before printing an error message.
75  */
76 #define EEH_MAX_FAILS	2100000
77 
78 /* Time to wait for a PCI slot to report status, in milliseconds */
79 #define PCI_BUS_RESET_WAIT_MSEC (5*60*1000)
80 
81 /*
82  * EEH probe mode support, which is part of the flags,
83  * is to support multiple platforms for EEH. Some platforms
84  * like pSeries do PCI emunation based on device tree.
85  * However, other platforms like powernv probe PCI devices
86  * from hardware. The flag is used to distinguish that.
87  * In addition, struct eeh_ops::probe would be invoked for
88  * particular OF node or PCI device so that the corresponding
89  * PE would be created there.
90  */
91 int eeh_subsystem_flags;
92 EXPORT_SYMBOL(eeh_subsystem_flags);
93 
94 /*
95  * EEH allowed maximal frozen times. If one particular PE's
96  * frozen count in last hour exceeds this limit, the PE will
97  * be forced to be offline permanently.
98  */
99 u32 eeh_max_freezes = 5;
100 
101 /*
102  * Controls whether a recovery event should be scheduled when an
103  * isolated device is discovered. This is only really useful for
104  * debugging problems with the EEH core.
105  */
106 bool eeh_debugfs_no_recover;
107 
108 /* Platform dependent EEH operations */
109 struct eeh_ops *eeh_ops = NULL;
110 
111 /* Lock to avoid races due to multiple reports of an error */
112 DEFINE_RAW_SPINLOCK(confirm_error_lock);
113 EXPORT_SYMBOL_GPL(confirm_error_lock);
114 
115 /* Lock to protect passed flags */
116 static DEFINE_MUTEX(eeh_dev_mutex);
117 
118 /* Buffer for reporting pci register dumps. Its here in BSS, and
119  * not dynamically alloced, so that it ends up in RMO where RTAS
120  * can access it.
121  */
122 #define EEH_PCI_REGS_LOG_LEN 8192
123 static unsigned char pci_regs_buf[EEH_PCI_REGS_LOG_LEN];
124 
125 /*
126  * The struct is used to maintain the EEH global statistic
127  * information. Besides, the EEH global statistics will be
128  * exported to user space through procfs
129  */
130 struct eeh_stats {
131 	u64 no_device;		/* PCI device not found		*/
132 	u64 no_dn;		/* OF node not found		*/
133 	u64 no_cfg_addr;	/* Config address not found	*/
134 	u64 ignored_check;	/* EEH check skipped		*/
135 	u64 total_mmio_ffs;	/* Total EEH checks		*/
136 	u64 false_positives;	/* Unnecessary EEH checks	*/
137 	u64 slot_resets;	/* PE reset			*/
138 };
139 
140 static struct eeh_stats eeh_stats;
141 
eeh_setup(char * str)142 static int __init eeh_setup(char *str)
143 {
144 	if (!strcmp(str, "off"))
145 		eeh_add_flag(EEH_FORCE_DISABLED);
146 	else if (!strcmp(str, "early_log"))
147 		eeh_add_flag(EEH_EARLY_DUMP_LOG);
148 
149 	return 1;
150 }
151 __setup("eeh=", eeh_setup);
152 
eeh_show_enabled(void)153 void eeh_show_enabled(void)
154 {
155 	if (eeh_has_flag(EEH_FORCE_DISABLED))
156 		pr_info("EEH: Recovery disabled by kernel parameter.\n");
157 	else if (eeh_has_flag(EEH_ENABLED))
158 		pr_info("EEH: Capable adapter found: recovery enabled.\n");
159 	else
160 		pr_info("EEH: No capable adapters found: recovery disabled.\n");
161 }
162 
163 /*
164  * This routine captures assorted PCI configuration space data
165  * for the indicated PCI device, and puts them into a buffer
166  * for RTAS error logging.
167  */
eeh_dump_dev_log(struct eeh_dev * edev,char * buf,size_t len)168 static size_t eeh_dump_dev_log(struct eeh_dev *edev, char *buf, size_t len)
169 {
170 	struct pci_dn *pdn = eeh_dev_to_pdn(edev);
171 	u32 cfg;
172 	int cap, i;
173 	int n = 0, l = 0;
174 	char buffer[128];
175 
176 	if (!pdn) {
177 		pr_warn("EEH: Note: No error log for absent device.\n");
178 		return 0;
179 	}
180 
181 	n += scnprintf(buf+n, len-n, "%04x:%02x:%02x.%01x\n",
182 		       pdn->phb->global_number, pdn->busno,
183 		       PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn));
184 	pr_warn("EEH: of node=%04x:%02x:%02x.%01x\n",
185 		pdn->phb->global_number, pdn->busno,
186 		PCI_SLOT(pdn->devfn), PCI_FUNC(pdn->devfn));
187 
188 	eeh_ops->read_config(pdn, PCI_VENDOR_ID, 4, &cfg);
189 	n += scnprintf(buf+n, len-n, "dev/vend:%08x\n", cfg);
190 	pr_warn("EEH: PCI device/vendor: %08x\n", cfg);
191 
192 	eeh_ops->read_config(pdn, PCI_COMMAND, 4, &cfg);
193 	n += scnprintf(buf+n, len-n, "cmd/stat:%x\n", cfg);
194 	pr_warn("EEH: PCI cmd/status register: %08x\n", cfg);
195 
196 	/* Gather bridge-specific registers */
197 	if (edev->mode & EEH_DEV_BRIDGE) {
198 		eeh_ops->read_config(pdn, PCI_SEC_STATUS, 2, &cfg);
199 		n += scnprintf(buf+n, len-n, "sec stat:%x\n", cfg);
200 		pr_warn("EEH: Bridge secondary status: %04x\n", cfg);
201 
202 		eeh_ops->read_config(pdn, PCI_BRIDGE_CONTROL, 2, &cfg);
203 		n += scnprintf(buf+n, len-n, "brdg ctl:%x\n", cfg);
204 		pr_warn("EEH: Bridge control: %04x\n", cfg);
205 	}
206 
207 	/* Dump out the PCI-X command and status regs */
208 	cap = edev->pcix_cap;
209 	if (cap) {
210 		eeh_ops->read_config(pdn, cap, 4, &cfg);
211 		n += scnprintf(buf+n, len-n, "pcix-cmd:%x\n", cfg);
212 		pr_warn("EEH: PCI-X cmd: %08x\n", cfg);
213 
214 		eeh_ops->read_config(pdn, cap+4, 4, &cfg);
215 		n += scnprintf(buf+n, len-n, "pcix-stat:%x\n", cfg);
216 		pr_warn("EEH: PCI-X status: %08x\n", cfg);
217 	}
218 
219 	/* If PCI-E capable, dump PCI-E cap 10 */
220 	cap = edev->pcie_cap;
221 	if (cap) {
222 		n += scnprintf(buf+n, len-n, "pci-e cap10:\n");
223 		pr_warn("EEH: PCI-E capabilities and status follow:\n");
224 
225 		for (i=0; i<=8; i++) {
226 			eeh_ops->read_config(pdn, cap+4*i, 4, &cfg);
227 			n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg);
228 
229 			if ((i % 4) == 0) {
230 				if (i != 0)
231 					pr_warn("%s\n", buffer);
232 
233 				l = scnprintf(buffer, sizeof(buffer),
234 					      "EEH: PCI-E %02x: %08x ",
235 					      4*i, cfg);
236 			} else {
237 				l += scnprintf(buffer+l, sizeof(buffer)-l,
238 					       "%08x ", cfg);
239 			}
240 
241 		}
242 
243 		pr_warn("%s\n", buffer);
244 	}
245 
246 	/* If AER capable, dump it */
247 	cap = edev->aer_cap;
248 	if (cap) {
249 		n += scnprintf(buf+n, len-n, "pci-e AER:\n");
250 		pr_warn("EEH: PCI-E AER capability register set follows:\n");
251 
252 		for (i=0; i<=13; i++) {
253 			eeh_ops->read_config(pdn, cap+4*i, 4, &cfg);
254 			n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg);
255 
256 			if ((i % 4) == 0) {
257 				if (i != 0)
258 					pr_warn("%s\n", buffer);
259 
260 				l = scnprintf(buffer, sizeof(buffer),
261 					      "EEH: PCI-E AER %02x: %08x ",
262 					      4*i, cfg);
263 			} else {
264 				l += scnprintf(buffer+l, sizeof(buffer)-l,
265 					       "%08x ", cfg);
266 			}
267 		}
268 
269 		pr_warn("%s\n", buffer);
270 	}
271 
272 	return n;
273 }
274 
eeh_dump_pe_log(struct eeh_pe * pe,void * flag)275 static void *eeh_dump_pe_log(struct eeh_pe *pe, void *flag)
276 {
277 	struct eeh_dev *edev, *tmp;
278 	size_t *plen = flag;
279 
280 	eeh_pe_for_each_dev(pe, edev, tmp)
281 		*plen += eeh_dump_dev_log(edev, pci_regs_buf + *plen,
282 					  EEH_PCI_REGS_LOG_LEN - *plen);
283 
284 	return NULL;
285 }
286 
287 /**
288  * eeh_slot_error_detail - Generate combined log including driver log and error log
289  * @pe: EEH PE
290  * @severity: temporary or permanent error log
291  *
292  * This routine should be called to generate the combined log, which
293  * is comprised of driver log and error log. The driver log is figured
294  * out from the config space of the corresponding PCI device, while
295  * the error log is fetched through platform dependent function call.
296  */
eeh_slot_error_detail(struct eeh_pe * pe,int severity)297 void eeh_slot_error_detail(struct eeh_pe *pe, int severity)
298 {
299 	size_t loglen = 0;
300 
301 	/*
302 	 * When the PHB is fenced or dead, it's pointless to collect
303 	 * the data from PCI config space because it should return
304 	 * 0xFF's. For ER, we still retrieve the data from the PCI
305 	 * config space.
306 	 *
307 	 * For pHyp, we have to enable IO for log retrieval. Otherwise,
308 	 * 0xFF's is always returned from PCI config space.
309 	 *
310 	 * When the @severity is EEH_LOG_PERM, the PE is going to be
311 	 * removed. Prior to that, the drivers for devices included in
312 	 * the PE will be closed. The drivers rely on working IO path
313 	 * to bring the devices to quiet state. Otherwise, PCI traffic
314 	 * from those devices after they are removed is like to cause
315 	 * another unexpected EEH error.
316 	 */
317 	if (!(pe->type & EEH_PE_PHB)) {
318 		if (eeh_has_flag(EEH_ENABLE_IO_FOR_LOG) ||
319 		    severity == EEH_LOG_PERM)
320 			eeh_pci_enable(pe, EEH_OPT_THAW_MMIO);
321 
322 		/*
323 		 * The config space of some PCI devices can't be accessed
324 		 * when their PEs are in frozen state. Otherwise, fenced
325 		 * PHB might be seen. Those PEs are identified with flag
326 		 * EEH_PE_CFG_RESTRICTED, indicating EEH_PE_CFG_BLOCKED
327 		 * is set automatically when the PE is put to EEH_PE_ISOLATED.
328 		 *
329 		 * Restoring BARs possibly triggers PCI config access in
330 		 * (OPAL) firmware and then causes fenced PHB. If the
331 		 * PCI config is blocked with flag EEH_PE_CFG_BLOCKED, it's
332 		 * pointless to restore BARs and dump config space.
333 		 */
334 		eeh_ops->configure_bridge(pe);
335 		if (!(pe->state & EEH_PE_CFG_BLOCKED)) {
336 			eeh_pe_restore_bars(pe);
337 
338 			pci_regs_buf[0] = 0;
339 			eeh_pe_traverse(pe, eeh_dump_pe_log, &loglen);
340 		}
341 	}
342 
343 	eeh_ops->get_log(pe, severity, pci_regs_buf, loglen);
344 }
345 
346 /**
347  * eeh_token_to_phys - Convert EEH address token to phys address
348  * @token: I/O token, should be address in the form 0xA....
349  *
350  * This routine should be called to convert virtual I/O address
351  * to physical one.
352  */
eeh_token_to_phys(unsigned long token)353 static inline unsigned long eeh_token_to_phys(unsigned long token)
354 {
355 	pte_t *ptep;
356 	unsigned long pa;
357 	int hugepage_shift;
358 
359 	/*
360 	 * We won't find hugepages here(this is iomem). Hence we are not
361 	 * worried about _PAGE_SPLITTING/collapse. Also we will not hit
362 	 * page table free, because of init_mm.
363 	 */
364 	ptep = find_init_mm_pte(token, &hugepage_shift);
365 	if (!ptep)
366 		return token;
367 
368 	pa = pte_pfn(*ptep);
369 
370 	/* On radix we can do hugepage mappings for io, so handle that */
371 	if (!hugepage_shift)
372 		hugepage_shift = PAGE_SHIFT;
373 
374 	pa <<= PAGE_SHIFT;
375 	pa |= token & ((1ul << hugepage_shift) - 1);
376 	return pa;
377 }
378 
379 /*
380  * On PowerNV platform, we might already have fenced PHB there.
381  * For that case, it's meaningless to recover frozen PE. Intead,
382  * We have to handle fenced PHB firstly.
383  */
eeh_phb_check_failure(struct eeh_pe * pe)384 static int eeh_phb_check_failure(struct eeh_pe *pe)
385 {
386 	struct eeh_pe *phb_pe;
387 	unsigned long flags;
388 	int ret;
389 
390 	if (!eeh_has_flag(EEH_PROBE_MODE_DEV))
391 		return -EPERM;
392 
393 	/* Find the PHB PE */
394 	phb_pe = eeh_phb_pe_get(pe->phb);
395 	if (!phb_pe) {
396 		pr_warn("%s Can't find PE for PHB#%x\n",
397 			__func__, pe->phb->global_number);
398 		return -EEXIST;
399 	}
400 
401 	/* If the PHB has been in problematic state */
402 	eeh_serialize_lock(&flags);
403 	if (phb_pe->state & EEH_PE_ISOLATED) {
404 		ret = 0;
405 		goto out;
406 	}
407 
408 	/* Check PHB state */
409 	ret = eeh_ops->get_state(phb_pe, NULL);
410 	if ((ret < 0) ||
411 	    (ret == EEH_STATE_NOT_SUPPORT) || eeh_state_active(ret)) {
412 		ret = 0;
413 		goto out;
414 	}
415 
416 	/* Isolate the PHB and send event */
417 	eeh_pe_mark_isolated(phb_pe);
418 	eeh_serialize_unlock(flags);
419 
420 	pr_debug("EEH: PHB#%x failure detected, location: %s\n",
421 		phb_pe->phb->global_number, eeh_pe_loc_get(phb_pe));
422 	eeh_send_failure_event(phb_pe);
423 	return 1;
424 out:
425 	eeh_serialize_unlock(flags);
426 	return ret;
427 }
428 
429 /**
430  * eeh_dev_check_failure - Check if all 1's data is due to EEH slot freeze
431  * @edev: eeh device
432  *
433  * Check for an EEH failure for the given device node.  Call this
434  * routine if the result of a read was all 0xff's and you want to
435  * find out if this is due to an EEH slot freeze.  This routine
436  * will query firmware for the EEH status.
437  *
438  * Returns 0 if there has not been an EEH error; otherwise returns
439  * a non-zero value and queues up a slot isolation event notification.
440  *
441  * It is safe to call this routine in an interrupt context.
442  */
eeh_dev_check_failure(struct eeh_dev * edev)443 int eeh_dev_check_failure(struct eeh_dev *edev)
444 {
445 	int ret;
446 	unsigned long flags;
447 	struct device_node *dn;
448 	struct pci_dev *dev;
449 	struct eeh_pe *pe, *parent_pe;
450 	int rc = 0;
451 	const char *location = NULL;
452 
453 	eeh_stats.total_mmio_ffs++;
454 
455 	if (!eeh_enabled())
456 		return 0;
457 
458 	if (!edev) {
459 		eeh_stats.no_dn++;
460 		return 0;
461 	}
462 	dev = eeh_dev_to_pci_dev(edev);
463 	pe = eeh_dev_to_pe(edev);
464 
465 	/* Access to IO BARs might get this far and still not want checking. */
466 	if (!pe) {
467 		eeh_stats.ignored_check++;
468 		eeh_edev_dbg(edev, "Ignored check\n");
469 		return 0;
470 	}
471 
472 	if (!pe->addr && !pe->config_addr) {
473 		eeh_stats.no_cfg_addr++;
474 		return 0;
475 	}
476 
477 	/*
478 	 * On PowerNV platform, we might already have fenced PHB
479 	 * there and we need take care of that firstly.
480 	 */
481 	ret = eeh_phb_check_failure(pe);
482 	if (ret > 0)
483 		return ret;
484 
485 	/*
486 	 * If the PE isn't owned by us, we shouldn't check the
487 	 * state. Instead, let the owner handle it if the PE has
488 	 * been frozen.
489 	 */
490 	if (eeh_pe_passed(pe))
491 		return 0;
492 
493 	/* If we already have a pending isolation event for this
494 	 * slot, we know it's bad already, we don't need to check.
495 	 * Do this checking under a lock; as multiple PCI devices
496 	 * in one slot might report errors simultaneously, and we
497 	 * only want one error recovery routine running.
498 	 */
499 	eeh_serialize_lock(&flags);
500 	rc = 1;
501 	if (pe->state & EEH_PE_ISOLATED) {
502 		pe->check_count++;
503 		if (pe->check_count == EEH_MAX_FAILS) {
504 			dn = pci_device_to_OF_node(dev);
505 			if (dn)
506 				location = of_get_property(dn, "ibm,loc-code",
507 						NULL);
508 			eeh_edev_err(edev, "%d reads ignored for recovering device at location=%s driver=%s\n",
509 				pe->check_count,
510 				location ? location : "unknown",
511 				eeh_driver_name(dev));
512 			eeh_edev_err(edev, "Might be infinite loop in %s driver\n",
513 				eeh_driver_name(dev));
514 			dump_stack();
515 		}
516 		goto dn_unlock;
517 	}
518 
519 	/*
520 	 * Now test for an EEH failure.  This is VERY expensive.
521 	 * Note that the eeh_config_addr may be a parent device
522 	 * in the case of a device behind a bridge, or it may be
523 	 * function zero of a multi-function device.
524 	 * In any case they must share a common PHB.
525 	 */
526 	ret = eeh_ops->get_state(pe, NULL);
527 
528 	/* Note that config-io to empty slots may fail;
529 	 * they are empty when they don't have children.
530 	 * We will punt with the following conditions: Failure to get
531 	 * PE's state, EEH not support and Permanently unavailable
532 	 * state, PE is in good state.
533 	 */
534 	if ((ret < 0) ||
535 	    (ret == EEH_STATE_NOT_SUPPORT) || eeh_state_active(ret)) {
536 		eeh_stats.false_positives++;
537 		pe->false_positives++;
538 		rc = 0;
539 		goto dn_unlock;
540 	}
541 
542 	/*
543 	 * It should be corner case that the parent PE has been
544 	 * put into frozen state as well. We should take care
545 	 * that at first.
546 	 */
547 	parent_pe = pe->parent;
548 	while (parent_pe) {
549 		/* Hit the ceiling ? */
550 		if (parent_pe->type & EEH_PE_PHB)
551 			break;
552 
553 		/* Frozen parent PE ? */
554 		ret = eeh_ops->get_state(parent_pe, NULL);
555 		if (ret > 0 && !eeh_state_active(ret)) {
556 			pe = parent_pe;
557 			pr_err("EEH: Failure of PHB#%x-PE#%x will be handled at parent PHB#%x-PE#%x.\n",
558 			       pe->phb->global_number, pe->addr,
559 			       pe->phb->global_number, parent_pe->addr);
560 		}
561 
562 		/* Next parent level */
563 		parent_pe = parent_pe->parent;
564 	}
565 
566 	eeh_stats.slot_resets++;
567 
568 	/* Avoid repeated reports of this failure, including problems
569 	 * with other functions on this device, and functions under
570 	 * bridges.
571 	 */
572 	eeh_pe_mark_isolated(pe);
573 	eeh_serialize_unlock(flags);
574 
575 	/* Most EEH events are due to device driver bugs.  Having
576 	 * a stack trace will help the device-driver authors figure
577 	 * out what happened.  So print that out.
578 	 */
579 	pr_debug("EEH: %s: Frozen PHB#%x-PE#%x detected\n",
580 		__func__, pe->phb->global_number, pe->addr);
581 	eeh_send_failure_event(pe);
582 
583 	return 1;
584 
585 dn_unlock:
586 	eeh_serialize_unlock(flags);
587 	return rc;
588 }
589 
590 EXPORT_SYMBOL_GPL(eeh_dev_check_failure);
591 
592 /**
593  * eeh_check_failure - Check if all 1's data is due to EEH slot freeze
594  * @token: I/O address
595  *
596  * Check for an EEH failure at the given I/O address. Call this
597  * routine if the result of a read was all 0xff's and you want to
598  * find out if this is due to an EEH slot freeze event. This routine
599  * will query firmware for the EEH status.
600  *
601  * Note this routine is safe to call in an interrupt context.
602  */
eeh_check_failure(const volatile void __iomem * token)603 int eeh_check_failure(const volatile void __iomem *token)
604 {
605 	unsigned long addr;
606 	struct eeh_dev *edev;
607 
608 	/* Finding the phys addr + pci device; this is pretty quick. */
609 	addr = eeh_token_to_phys((unsigned long __force) token);
610 	edev = eeh_addr_cache_get_dev(addr);
611 	if (!edev) {
612 		eeh_stats.no_device++;
613 		return 0;
614 	}
615 
616 	return eeh_dev_check_failure(edev);
617 }
618 EXPORT_SYMBOL(eeh_check_failure);
619 
620 
621 /**
622  * eeh_pci_enable - Enable MMIO or DMA transfers for this slot
623  * @pe: EEH PE
624  *
625  * This routine should be called to reenable frozen MMIO or DMA
626  * so that it would work correctly again. It's useful while doing
627  * recovery or log collection on the indicated device.
628  */
eeh_pci_enable(struct eeh_pe * pe,int function)629 int eeh_pci_enable(struct eeh_pe *pe, int function)
630 {
631 	int active_flag, rc;
632 
633 	/*
634 	 * pHyp doesn't allow to enable IO or DMA on unfrozen PE.
635 	 * Also, it's pointless to enable them on unfrozen PE. So
636 	 * we have to check before enabling IO or DMA.
637 	 */
638 	switch (function) {
639 	case EEH_OPT_THAW_MMIO:
640 		active_flag = EEH_STATE_MMIO_ACTIVE | EEH_STATE_MMIO_ENABLED;
641 		break;
642 	case EEH_OPT_THAW_DMA:
643 		active_flag = EEH_STATE_DMA_ACTIVE;
644 		break;
645 	case EEH_OPT_DISABLE:
646 	case EEH_OPT_ENABLE:
647 	case EEH_OPT_FREEZE_PE:
648 		active_flag = 0;
649 		break;
650 	default:
651 		pr_warn("%s: Invalid function %d\n",
652 			__func__, function);
653 		return -EINVAL;
654 	}
655 
656 	/*
657 	 * Check if IO or DMA has been enabled before
658 	 * enabling them.
659 	 */
660 	if (active_flag) {
661 		rc = eeh_ops->get_state(pe, NULL);
662 		if (rc < 0)
663 			return rc;
664 
665 		/* Needn't enable it at all */
666 		if (rc == EEH_STATE_NOT_SUPPORT)
667 			return 0;
668 
669 		/* It's already enabled */
670 		if (rc & active_flag)
671 			return 0;
672 	}
673 
674 
675 	/* Issue the request */
676 	rc = eeh_ops->set_option(pe, function);
677 	if (rc)
678 		pr_warn("%s: Unexpected state change %d on "
679 			"PHB#%x-PE#%x, err=%d\n",
680 			__func__, function, pe->phb->global_number,
681 			pe->addr, rc);
682 
683 	/* Check if the request is finished successfully */
684 	if (active_flag) {
685 		rc = eeh_wait_state(pe, PCI_BUS_RESET_WAIT_MSEC);
686 		if (rc < 0)
687 			return rc;
688 
689 		if (rc & active_flag)
690 			return 0;
691 
692 		return -EIO;
693 	}
694 
695 	return rc;
696 }
697 
eeh_disable_and_save_dev_state(struct eeh_dev * edev,void * userdata)698 static void eeh_disable_and_save_dev_state(struct eeh_dev *edev,
699 					    void *userdata)
700 {
701 	struct pci_dev *pdev = eeh_dev_to_pci_dev(edev);
702 	struct pci_dev *dev = userdata;
703 
704 	/*
705 	 * The caller should have disabled and saved the
706 	 * state for the specified device
707 	 */
708 	if (!pdev || pdev == dev)
709 		return;
710 
711 	/* Ensure we have D0 power state */
712 	pci_set_power_state(pdev, PCI_D0);
713 
714 	/* Save device state */
715 	pci_save_state(pdev);
716 
717 	/*
718 	 * Disable device to avoid any DMA traffic and
719 	 * interrupt from the device
720 	 */
721 	pci_write_config_word(pdev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
722 }
723 
eeh_restore_dev_state(struct eeh_dev * edev,void * userdata)724 static void eeh_restore_dev_state(struct eeh_dev *edev, void *userdata)
725 {
726 	struct pci_dn *pdn = eeh_dev_to_pdn(edev);
727 	struct pci_dev *pdev = eeh_dev_to_pci_dev(edev);
728 	struct pci_dev *dev = userdata;
729 
730 	if (!pdev)
731 		return;
732 
733 	/* Apply customization from firmware */
734 	if (pdn && eeh_ops->restore_config)
735 		eeh_ops->restore_config(pdn);
736 
737 	/* The caller should restore state for the specified device */
738 	if (pdev != dev)
739 		pci_restore_state(pdev);
740 }
741 
eeh_restore_vf_config(struct pci_dn * pdn)742 int eeh_restore_vf_config(struct pci_dn *pdn)
743 {
744 	struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
745 	u32 devctl, cmd, cap2, aer_capctl;
746 	int old_mps;
747 
748 	if (edev->pcie_cap) {
749 		/* Restore MPS */
750 		old_mps = (ffs(pdn->mps) - 8) << 5;
751 		eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
752 				     2, &devctl);
753 		devctl &= ~PCI_EXP_DEVCTL_PAYLOAD;
754 		devctl |= old_mps;
755 		eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
756 				      2, devctl);
757 
758 		/* Disable Completion Timeout if possible */
759 		eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCAP2,
760 				     4, &cap2);
761 		if (cap2 & PCI_EXP_DEVCAP2_COMP_TMOUT_DIS) {
762 			eeh_ops->read_config(pdn,
763 					     edev->pcie_cap + PCI_EXP_DEVCTL2,
764 					     4, &cap2);
765 			cap2 |= PCI_EXP_DEVCTL2_COMP_TMOUT_DIS;
766 			eeh_ops->write_config(pdn,
767 					      edev->pcie_cap + PCI_EXP_DEVCTL2,
768 					      4, cap2);
769 		}
770 	}
771 
772 	/* Enable SERR and parity checking */
773 	eeh_ops->read_config(pdn, PCI_COMMAND, 2, &cmd);
774 	cmd |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
775 	eeh_ops->write_config(pdn, PCI_COMMAND, 2, cmd);
776 
777 	/* Enable report various errors */
778 	if (edev->pcie_cap) {
779 		eeh_ops->read_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
780 				     2, &devctl);
781 		devctl &= ~PCI_EXP_DEVCTL_CERE;
782 		devctl |= (PCI_EXP_DEVCTL_NFERE |
783 			   PCI_EXP_DEVCTL_FERE |
784 			   PCI_EXP_DEVCTL_URRE);
785 		eeh_ops->write_config(pdn, edev->pcie_cap + PCI_EXP_DEVCTL,
786 				      2, devctl);
787 	}
788 
789 	/* Enable ECRC generation and check */
790 	if (edev->pcie_cap && edev->aer_cap) {
791 		eeh_ops->read_config(pdn, edev->aer_cap + PCI_ERR_CAP,
792 				     4, &aer_capctl);
793 		aer_capctl |= (PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE);
794 		eeh_ops->write_config(pdn, edev->aer_cap + PCI_ERR_CAP,
795 				      4, aer_capctl);
796 	}
797 
798 	return 0;
799 }
800 
801 /**
802  * pcibios_set_pcie_reset_state - Set PCI-E reset state
803  * @dev: pci device struct
804  * @state: reset state to enter
805  *
806  * Return value:
807  * 	0 if success
808  */
pcibios_set_pcie_reset_state(struct pci_dev * dev,enum pcie_reset_state state)809 int pcibios_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
810 {
811 	struct eeh_dev *edev = pci_dev_to_eeh_dev(dev);
812 	struct eeh_pe *pe = eeh_dev_to_pe(edev);
813 
814 	if (!pe) {
815 		pr_err("%s: No PE found on PCI device %s\n",
816 			__func__, pci_name(dev));
817 		return -EINVAL;
818 	}
819 
820 	switch (state) {
821 	case pcie_deassert_reset:
822 		eeh_ops->reset(pe, EEH_RESET_DEACTIVATE);
823 		eeh_unfreeze_pe(pe);
824 		if (!(pe->type & EEH_PE_VF))
825 			eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED, true);
826 		eeh_pe_dev_traverse(pe, eeh_restore_dev_state, dev);
827 		eeh_pe_state_clear(pe, EEH_PE_ISOLATED, true);
828 		break;
829 	case pcie_hot_reset:
830 		eeh_pe_mark_isolated(pe);
831 		eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED, true);
832 		eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);
833 		eeh_pe_dev_traverse(pe, eeh_disable_and_save_dev_state, dev);
834 		if (!(pe->type & EEH_PE_VF))
835 			eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED);
836 		eeh_ops->reset(pe, EEH_RESET_HOT);
837 		break;
838 	case pcie_warm_reset:
839 		eeh_pe_mark_isolated(pe);
840 		eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED, true);
841 		eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);
842 		eeh_pe_dev_traverse(pe, eeh_disable_and_save_dev_state, dev);
843 		if (!(pe->type & EEH_PE_VF))
844 			eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED);
845 		eeh_ops->reset(pe, EEH_RESET_FUNDAMENTAL);
846 		break;
847 	default:
848 		eeh_pe_state_clear(pe, EEH_PE_ISOLATED | EEH_PE_CFG_BLOCKED, true);
849 		return -EINVAL;
850 	};
851 
852 	return 0;
853 }
854 
855 /**
856  * eeh_set_pe_freset - Check the required reset for the indicated device
857  * @data: EEH device
858  * @flag: return value
859  *
860  * Each device might have its preferred reset type: fundamental or
861  * hot reset. The routine is used to collected the information for
862  * the indicated device and its children so that the bunch of the
863  * devices could be reset properly.
864  */
eeh_set_dev_freset(struct eeh_dev * edev,void * flag)865 static void eeh_set_dev_freset(struct eeh_dev *edev, void *flag)
866 {
867 	struct pci_dev *dev;
868 	unsigned int *freset = (unsigned int *)flag;
869 
870 	dev = eeh_dev_to_pci_dev(edev);
871 	if (dev)
872 		*freset |= dev->needs_freset;
873 }
874 
eeh_pe_refreeze_passed(struct eeh_pe * root)875 static void eeh_pe_refreeze_passed(struct eeh_pe *root)
876 {
877 	struct eeh_pe *pe;
878 	int state;
879 
880 	eeh_for_each_pe(root, pe) {
881 		if (eeh_pe_passed(pe)) {
882 			state = eeh_ops->get_state(pe, NULL);
883 			if (state &
884 			   (EEH_STATE_MMIO_ACTIVE | EEH_STATE_MMIO_ENABLED)) {
885 				pr_info("EEH: Passed-through PE PHB#%x-PE#%x was thawed by reset, re-freezing for safety.\n",
886 					pe->phb->global_number, pe->addr);
887 				eeh_pe_set_option(pe, EEH_OPT_FREEZE_PE);
888 			}
889 		}
890 	}
891 }
892 
893 /**
894  * eeh_pe_reset_full - Complete a full reset process on the indicated PE
895  * @pe: EEH PE
896  *
897  * This function executes a full reset procedure on a PE, including setting
898  * the appropriate flags, performing a fundamental or hot reset, and then
899  * deactivating the reset status.  It is designed to be used within the EEH
900  * subsystem, as opposed to eeh_pe_reset which is exported to drivers and
901  * only performs a single operation at a time.
902  *
903  * This function will attempt to reset a PE three times before failing.
904  */
eeh_pe_reset_full(struct eeh_pe * pe,bool include_passed)905 int eeh_pe_reset_full(struct eeh_pe *pe, bool include_passed)
906 {
907 	int reset_state = (EEH_PE_RESET | EEH_PE_CFG_BLOCKED);
908 	int type = EEH_RESET_HOT;
909 	unsigned int freset = 0;
910 	int i, state = 0, ret;
911 
912 	/*
913 	 * Determine the type of reset to perform - hot or fundamental.
914 	 * Hot reset is the default operation, unless any device under the
915 	 * PE requires a fundamental reset.
916 	 */
917 	eeh_pe_dev_traverse(pe, eeh_set_dev_freset, &freset);
918 
919 	if (freset)
920 		type = EEH_RESET_FUNDAMENTAL;
921 
922 	/* Mark the PE as in reset state and block config space accesses */
923 	eeh_pe_state_mark(pe, reset_state);
924 
925 	/* Make three attempts at resetting the bus */
926 	for (i = 0; i < 3; i++) {
927 		ret = eeh_pe_reset(pe, type, include_passed);
928 		if (!ret)
929 			ret = eeh_pe_reset(pe, EEH_RESET_DEACTIVATE,
930 					   include_passed);
931 		if (ret) {
932 			ret = -EIO;
933 			pr_warn("EEH: Failure %d resetting PHB#%x-PE#%x (attempt %d)\n\n",
934 				state, pe->phb->global_number, pe->addr, i + 1);
935 			continue;
936 		}
937 		if (i)
938 			pr_warn("EEH: PHB#%x-PE#%x: Successful reset (attempt %d)\n",
939 				pe->phb->global_number, pe->addr, i + 1);
940 
941 		/* Wait until the PE is in a functioning state */
942 		state = eeh_wait_state(pe, PCI_BUS_RESET_WAIT_MSEC);
943 		if (state < 0) {
944 			pr_warn("EEH: Unrecoverable slot failure on PHB#%x-PE#%x",
945 				pe->phb->global_number, pe->addr);
946 			ret = -ENOTRECOVERABLE;
947 			break;
948 		}
949 		if (eeh_state_active(state))
950 			break;
951 		else
952 			pr_warn("EEH: PHB#%x-PE#%x: Slot inactive after reset: 0x%x (attempt %d)\n",
953 				pe->phb->global_number, pe->addr, state, i + 1);
954 	}
955 
956 	/* Resetting the PE may have unfrozen child PEs. If those PEs have been
957 	 * (potentially) passed through to a guest, re-freeze them:
958 	 */
959 	if (!include_passed)
960 		eeh_pe_refreeze_passed(pe);
961 
962 	eeh_pe_state_clear(pe, reset_state, true);
963 	return ret;
964 }
965 
966 /**
967  * eeh_save_bars - Save device bars
968  * @edev: PCI device associated EEH device
969  *
970  * Save the values of the device bars. Unlike the restore
971  * routine, this routine is *not* recursive. This is because
972  * PCI devices are added individually; but, for the restore,
973  * an entire slot is reset at a time.
974  */
eeh_save_bars(struct eeh_dev * edev)975 void eeh_save_bars(struct eeh_dev *edev)
976 {
977 	struct pci_dn *pdn;
978 	int i;
979 
980 	pdn = eeh_dev_to_pdn(edev);
981 	if (!pdn)
982 		return;
983 
984 	for (i = 0; i < 16; i++)
985 		eeh_ops->read_config(pdn, i * 4, 4, &edev->config_space[i]);
986 
987 	/*
988 	 * For PCI bridges including root port, we need enable bus
989 	 * master explicitly. Otherwise, it can't fetch IODA table
990 	 * entries correctly. So we cache the bit in advance so that
991 	 * we can restore it after reset, either PHB range or PE range.
992 	 */
993 	if (edev->mode & EEH_DEV_BRIDGE)
994 		edev->config_space[1] |= PCI_COMMAND_MASTER;
995 }
996 
997 /**
998  * eeh_ops_register - Register platform dependent EEH operations
999  * @ops: platform dependent EEH operations
1000  *
1001  * Register the platform dependent EEH operation callback
1002  * functions. The platform should call this function before
1003  * any other EEH operations.
1004  */
eeh_ops_register(struct eeh_ops * ops)1005 int __init eeh_ops_register(struct eeh_ops *ops)
1006 {
1007 	if (!ops->name) {
1008 		pr_warn("%s: Invalid EEH ops name for %p\n",
1009 			__func__, ops);
1010 		return -EINVAL;
1011 	}
1012 
1013 	if (eeh_ops && eeh_ops != ops) {
1014 		pr_warn("%s: EEH ops of platform %s already existing (%s)\n",
1015 			__func__, eeh_ops->name, ops->name);
1016 		return -EEXIST;
1017 	}
1018 
1019 	eeh_ops = ops;
1020 
1021 	return 0;
1022 }
1023 
1024 /**
1025  * eeh_ops_unregister - Unreigster platform dependent EEH operations
1026  * @name: name of EEH platform operations
1027  *
1028  * Unregister the platform dependent EEH operation callback
1029  * functions.
1030  */
eeh_ops_unregister(const char * name)1031 int __exit eeh_ops_unregister(const char *name)
1032 {
1033 	if (!name || !strlen(name)) {
1034 		pr_warn("%s: Invalid EEH ops name\n",
1035 			__func__);
1036 		return -EINVAL;
1037 	}
1038 
1039 	if (eeh_ops && !strcmp(eeh_ops->name, name)) {
1040 		eeh_ops = NULL;
1041 		return 0;
1042 	}
1043 
1044 	return -EEXIST;
1045 }
1046 
eeh_reboot_notifier(struct notifier_block * nb,unsigned long action,void * unused)1047 static int eeh_reboot_notifier(struct notifier_block *nb,
1048 			       unsigned long action, void *unused)
1049 {
1050 	eeh_clear_flag(EEH_ENABLED);
1051 	return NOTIFY_DONE;
1052 }
1053 
1054 static struct notifier_block eeh_reboot_nb = {
1055 	.notifier_call = eeh_reboot_notifier,
1056 };
1057 
1058 /**
1059  * eeh_init - EEH initialization
1060  *
1061  * Initialize EEH by trying to enable it for all of the adapters in the system.
1062  * As a side effect we can determine here if eeh is supported at all.
1063  * Note that we leave EEH on so failed config cycles won't cause a machine
1064  * check.  If a user turns off EEH for a particular adapter they are really
1065  * telling Linux to ignore errors.  Some hardware (e.g. POWER5) won't
1066  * grant access to a slot if EEH isn't enabled, and so we always enable
1067  * EEH for all slots/all devices.
1068  *
1069  * The eeh-force-off option disables EEH checking globally, for all slots.
1070  * Even if force-off is set, the EEH hardware is still enabled, so that
1071  * newer systems can boot.
1072  */
eeh_init(void)1073 static int eeh_init(void)
1074 {
1075 	struct pci_controller *hose, *tmp;
1076 	int ret = 0;
1077 
1078 	/* Register reboot notifier */
1079 	ret = register_reboot_notifier(&eeh_reboot_nb);
1080 	if (ret) {
1081 		pr_warn("%s: Failed to register notifier (%d)\n",
1082 			__func__, ret);
1083 		return ret;
1084 	}
1085 
1086 	/* call platform initialization function */
1087 	if (!eeh_ops) {
1088 		pr_warn("%s: Platform EEH operation not found\n",
1089 			__func__);
1090 		return -EEXIST;
1091 	} else if ((ret = eeh_ops->init()))
1092 		return ret;
1093 
1094 	/* Initialize PHB PEs */
1095 	list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1096 		eeh_dev_phb_init_dynamic(hose);
1097 
1098 	eeh_addr_cache_init();
1099 
1100 	/* Initialize EEH event */
1101 	return eeh_event_init();
1102 }
1103 
1104 core_initcall_sync(eeh_init);
1105 
1106 /**
1107  * eeh_add_device_early - Enable EEH for the indicated device node
1108  * @pdn: PCI device node for which to set up EEH
1109  *
1110  * This routine must be used to perform EEH initialization for PCI
1111  * devices that were added after system boot (e.g. hotplug, dlpar).
1112  * This routine must be called before any i/o is performed to the
1113  * adapter (inluding any config-space i/o).
1114  * Whether this actually enables EEH or not for this device depends
1115  * on the CEC architecture, type of the device, on earlier boot
1116  * command-line arguments & etc.
1117  */
eeh_add_device_early(struct pci_dn * pdn)1118 void eeh_add_device_early(struct pci_dn *pdn)
1119 {
1120 	struct pci_controller *phb = pdn ? pdn->phb : NULL;
1121 	struct eeh_dev *edev = pdn_to_eeh_dev(pdn);
1122 
1123 	if (!edev)
1124 		return;
1125 
1126 	if (!eeh_has_flag(EEH_PROBE_MODE_DEVTREE))
1127 		return;
1128 
1129 	/* USB Bus children of PCI devices will not have BUID's */
1130 	if (NULL == phb ||
1131 	    (eeh_has_flag(EEH_PROBE_MODE_DEVTREE) && 0 == phb->buid))
1132 		return;
1133 
1134 	eeh_ops->probe(pdn, NULL);
1135 }
1136 
1137 /**
1138  * eeh_add_device_tree_early - Enable EEH for the indicated device
1139  * @pdn: PCI device node
1140  *
1141  * This routine must be used to perform EEH initialization for the
1142  * indicated PCI device that was added after system boot (e.g.
1143  * hotplug, dlpar).
1144  */
eeh_add_device_tree_early(struct pci_dn * pdn)1145 void eeh_add_device_tree_early(struct pci_dn *pdn)
1146 {
1147 	struct pci_dn *n;
1148 
1149 	if (!pdn)
1150 		return;
1151 
1152 	list_for_each_entry(n, &pdn->child_list, list)
1153 		eeh_add_device_tree_early(n);
1154 	eeh_add_device_early(pdn);
1155 }
1156 EXPORT_SYMBOL_GPL(eeh_add_device_tree_early);
1157 
1158 /**
1159  * eeh_add_device_late - Perform EEH initialization for the indicated pci device
1160  * @dev: pci device for which to set up EEH
1161  *
1162  * This routine must be used to complete EEH initialization for PCI
1163  * devices that were added after system boot (e.g. hotplug, dlpar).
1164  */
eeh_add_device_late(struct pci_dev * dev)1165 void eeh_add_device_late(struct pci_dev *dev)
1166 {
1167 	struct pci_dn *pdn;
1168 	struct eeh_dev *edev;
1169 
1170 	if (!dev)
1171 		return;
1172 
1173 	pdn = pci_get_pdn_by_devfn(dev->bus, dev->devfn);
1174 	edev = pdn_to_eeh_dev(pdn);
1175 	eeh_edev_dbg(edev, "Adding device\n");
1176 	if (edev->pdev == dev) {
1177 		eeh_edev_dbg(edev, "Device already referenced!\n");
1178 		return;
1179 	}
1180 
1181 	/*
1182 	 * The EEH cache might not be removed correctly because of
1183 	 * unbalanced kref to the device during unplug time, which
1184 	 * relies on pcibios_release_device(). So we have to remove
1185 	 * that here explicitly.
1186 	 */
1187 	if (edev->pdev) {
1188 		eeh_rmv_from_parent_pe(edev);
1189 		eeh_addr_cache_rmv_dev(edev->pdev);
1190 		eeh_sysfs_remove_device(edev->pdev);
1191 		edev->mode &= ~EEH_DEV_SYSFS;
1192 
1193 		/*
1194 		 * We definitely should have the PCI device removed
1195 		 * though it wasn't correctly. So we needn't call
1196 		 * into error handler afterwards.
1197 		 */
1198 		edev->mode |= EEH_DEV_NO_HANDLER;
1199 
1200 		edev->pdev = NULL;
1201 		dev->dev.archdata.edev = NULL;
1202 	}
1203 
1204 	if (eeh_has_flag(EEH_PROBE_MODE_DEV))
1205 		eeh_ops->probe(pdn, NULL);
1206 
1207 	edev->pdev = dev;
1208 	dev->dev.archdata.edev = edev;
1209 
1210 	eeh_addr_cache_insert_dev(dev);
1211 }
1212 
1213 /**
1214  * eeh_add_device_tree_late - Perform EEH initialization for the indicated PCI bus
1215  * @bus: PCI bus
1216  *
1217  * This routine must be used to perform EEH initialization for PCI
1218  * devices which are attached to the indicated PCI bus. The PCI bus
1219  * is added after system boot through hotplug or dlpar.
1220  */
eeh_add_device_tree_late(struct pci_bus * bus)1221 void eeh_add_device_tree_late(struct pci_bus *bus)
1222 {
1223 	struct pci_dev *dev;
1224 
1225 	if (eeh_has_flag(EEH_FORCE_DISABLED))
1226 		return;
1227 	list_for_each_entry(dev, &bus->devices, bus_list) {
1228 		eeh_add_device_late(dev);
1229 		if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
1230 			struct pci_bus *subbus = dev->subordinate;
1231 			if (subbus)
1232 				eeh_add_device_tree_late(subbus);
1233 		}
1234 	}
1235 }
1236 EXPORT_SYMBOL_GPL(eeh_add_device_tree_late);
1237 
1238 /**
1239  * eeh_add_sysfs_files - Add EEH sysfs files for the indicated PCI bus
1240  * @bus: PCI bus
1241  *
1242  * This routine must be used to add EEH sysfs files for PCI
1243  * devices which are attached to the indicated PCI bus. The PCI bus
1244  * is added after system boot through hotplug or dlpar.
1245  */
eeh_add_sysfs_files(struct pci_bus * bus)1246 void eeh_add_sysfs_files(struct pci_bus *bus)
1247 {
1248 	struct pci_dev *dev;
1249 
1250 	list_for_each_entry(dev, &bus->devices, bus_list) {
1251 		eeh_sysfs_add_device(dev);
1252 		if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
1253 			struct pci_bus *subbus = dev->subordinate;
1254 			if (subbus)
1255 				eeh_add_sysfs_files(subbus);
1256 		}
1257 	}
1258 }
1259 EXPORT_SYMBOL_GPL(eeh_add_sysfs_files);
1260 
1261 /**
1262  * eeh_remove_device - Undo EEH setup for the indicated pci device
1263  * @dev: pci device to be removed
1264  *
1265  * This routine should be called when a device is removed from
1266  * a running system (e.g. by hotplug or dlpar).  It unregisters
1267  * the PCI device from the EEH subsystem.  I/O errors affecting
1268  * this device will no longer be detected after this call; thus,
1269  * i/o errors affecting this slot may leave this device unusable.
1270  */
eeh_remove_device(struct pci_dev * dev)1271 void eeh_remove_device(struct pci_dev *dev)
1272 {
1273 	struct eeh_dev *edev;
1274 
1275 	if (!dev || !eeh_enabled())
1276 		return;
1277 	edev = pci_dev_to_eeh_dev(dev);
1278 
1279 	/* Unregister the device with the EEH/PCI address search system */
1280 	dev_dbg(&dev->dev, "EEH: Removing device\n");
1281 
1282 	if (!edev || !edev->pdev || !edev->pe) {
1283 		dev_dbg(&dev->dev, "EEH: Device not referenced!\n");
1284 		return;
1285 	}
1286 
1287 	/*
1288 	 * During the hotplug for EEH error recovery, we need the EEH
1289 	 * device attached to the parent PE in order for BAR restore
1290 	 * a bit later. So we keep it for BAR restore and remove it
1291 	 * from the parent PE during the BAR resotre.
1292 	 */
1293 	edev->pdev = NULL;
1294 
1295 	/*
1296 	 * The flag "in_error" is used to trace EEH devices for VFs
1297 	 * in error state or not. It's set in eeh_report_error(). If
1298 	 * it's not set, eeh_report_{reset,resume}() won't be called
1299 	 * for the VF EEH device.
1300 	 */
1301 	edev->in_error = false;
1302 	dev->dev.archdata.edev = NULL;
1303 	if (!(edev->pe->state & EEH_PE_KEEP))
1304 		eeh_rmv_from_parent_pe(edev);
1305 	else
1306 		edev->mode |= EEH_DEV_DISCONNECTED;
1307 
1308 	/*
1309 	 * We're removing from the PCI subsystem, that means
1310 	 * the PCI device driver can't support EEH or not
1311 	 * well. So we rely on hotplug completely to do recovery
1312 	 * for the specific PCI device.
1313 	 */
1314 	edev->mode |= EEH_DEV_NO_HANDLER;
1315 
1316 	eeh_addr_cache_rmv_dev(dev);
1317 	eeh_sysfs_remove_device(dev);
1318 	edev->mode &= ~EEH_DEV_SYSFS;
1319 }
1320 
eeh_unfreeze_pe(struct eeh_pe * pe)1321 int eeh_unfreeze_pe(struct eeh_pe *pe)
1322 {
1323 	int ret;
1324 
1325 	ret = eeh_pci_enable(pe, EEH_OPT_THAW_MMIO);
1326 	if (ret) {
1327 		pr_warn("%s: Failure %d enabling IO on PHB#%x-PE#%x\n",
1328 			__func__, ret, pe->phb->global_number, pe->addr);
1329 		return ret;
1330 	}
1331 
1332 	ret = eeh_pci_enable(pe, EEH_OPT_THAW_DMA);
1333 	if (ret) {
1334 		pr_warn("%s: Failure %d enabling DMA on PHB#%x-PE#%x\n",
1335 			__func__, ret, pe->phb->global_number, pe->addr);
1336 		return ret;
1337 	}
1338 
1339 	return ret;
1340 }
1341 
1342 
1343 static struct pci_device_id eeh_reset_ids[] = {
1344 	{ PCI_DEVICE(0x19a2, 0x0710) },	/* Emulex, BE     */
1345 	{ PCI_DEVICE(0x10df, 0xe220) },	/* Emulex, Lancer */
1346 	{ PCI_DEVICE(0x14e4, 0x1657) }, /* Broadcom BCM5719 */
1347 	{ 0 }
1348 };
1349 
eeh_pe_change_owner(struct eeh_pe * pe)1350 static int eeh_pe_change_owner(struct eeh_pe *pe)
1351 {
1352 	struct eeh_dev *edev, *tmp;
1353 	struct pci_dev *pdev;
1354 	struct pci_device_id *id;
1355 	int ret;
1356 
1357 	/* Check PE state */
1358 	ret = eeh_ops->get_state(pe, NULL);
1359 	if (ret < 0 || ret == EEH_STATE_NOT_SUPPORT)
1360 		return 0;
1361 
1362 	/* Unfrozen PE, nothing to do */
1363 	if (eeh_state_active(ret))
1364 		return 0;
1365 
1366 	/* Frozen PE, check if it needs PE level reset */
1367 	eeh_pe_for_each_dev(pe, edev, tmp) {
1368 		pdev = eeh_dev_to_pci_dev(edev);
1369 		if (!pdev)
1370 			continue;
1371 
1372 		for (id = &eeh_reset_ids[0]; id->vendor != 0; id++) {
1373 			if (id->vendor != PCI_ANY_ID &&
1374 			    id->vendor != pdev->vendor)
1375 				continue;
1376 			if (id->device != PCI_ANY_ID &&
1377 			    id->device != pdev->device)
1378 				continue;
1379 			if (id->subvendor != PCI_ANY_ID &&
1380 			    id->subvendor != pdev->subsystem_vendor)
1381 				continue;
1382 			if (id->subdevice != PCI_ANY_ID &&
1383 			    id->subdevice != pdev->subsystem_device)
1384 				continue;
1385 
1386 			return eeh_pe_reset_and_recover(pe);
1387 		}
1388 	}
1389 
1390 	ret = eeh_unfreeze_pe(pe);
1391 	if (!ret)
1392 		eeh_pe_state_clear(pe, EEH_PE_ISOLATED, true);
1393 	return ret;
1394 }
1395 
1396 /**
1397  * eeh_dev_open - Increase count of pass through devices for PE
1398  * @pdev: PCI device
1399  *
1400  * Increase count of passed through devices for the indicated
1401  * PE. In the result, the EEH errors detected on the PE won't be
1402  * reported. The PE owner will be responsible for detection
1403  * and recovery.
1404  */
eeh_dev_open(struct pci_dev * pdev)1405 int eeh_dev_open(struct pci_dev *pdev)
1406 {
1407 	struct eeh_dev *edev;
1408 	int ret = -ENODEV;
1409 
1410 	mutex_lock(&eeh_dev_mutex);
1411 
1412 	/* No PCI device ? */
1413 	if (!pdev)
1414 		goto out;
1415 
1416 	/* No EEH device or PE ? */
1417 	edev = pci_dev_to_eeh_dev(pdev);
1418 	if (!edev || !edev->pe)
1419 		goto out;
1420 
1421 	/*
1422 	 * The PE might have been put into frozen state, but we
1423 	 * didn't detect that yet. The passed through PCI devices
1424 	 * in frozen PE won't work properly. Clear the frozen state
1425 	 * in advance.
1426 	 */
1427 	ret = eeh_pe_change_owner(edev->pe);
1428 	if (ret)
1429 		goto out;
1430 
1431 	/* Increase PE's pass through count */
1432 	atomic_inc(&edev->pe->pass_dev_cnt);
1433 	mutex_unlock(&eeh_dev_mutex);
1434 
1435 	return 0;
1436 out:
1437 	mutex_unlock(&eeh_dev_mutex);
1438 	return ret;
1439 }
1440 EXPORT_SYMBOL_GPL(eeh_dev_open);
1441 
1442 /**
1443  * eeh_dev_release - Decrease count of pass through devices for PE
1444  * @pdev: PCI device
1445  *
1446  * Decrease count of pass through devices for the indicated PE. If
1447  * there is no passed through device in PE, the EEH errors detected
1448  * on the PE will be reported and handled as usual.
1449  */
eeh_dev_release(struct pci_dev * pdev)1450 void eeh_dev_release(struct pci_dev *pdev)
1451 {
1452 	struct eeh_dev *edev;
1453 
1454 	mutex_lock(&eeh_dev_mutex);
1455 
1456 	/* No PCI device ? */
1457 	if (!pdev)
1458 		goto out;
1459 
1460 	/* No EEH device ? */
1461 	edev = pci_dev_to_eeh_dev(pdev);
1462 	if (!edev || !edev->pe || !eeh_pe_passed(edev->pe))
1463 		goto out;
1464 
1465 	/* Decrease PE's pass through count */
1466 	WARN_ON(atomic_dec_if_positive(&edev->pe->pass_dev_cnt) < 0);
1467 	eeh_pe_change_owner(edev->pe);
1468 out:
1469 	mutex_unlock(&eeh_dev_mutex);
1470 }
1471 EXPORT_SYMBOL(eeh_dev_release);
1472 
1473 #ifdef CONFIG_IOMMU_API
1474 
dev_has_iommu_table(struct device * dev,void * data)1475 static int dev_has_iommu_table(struct device *dev, void *data)
1476 {
1477 	struct pci_dev *pdev = to_pci_dev(dev);
1478 	struct pci_dev **ppdev = data;
1479 
1480 	if (!dev)
1481 		return 0;
1482 
1483 	if (device_iommu_mapped(dev)) {
1484 		*ppdev = pdev;
1485 		return 1;
1486 	}
1487 
1488 	return 0;
1489 }
1490 
1491 /**
1492  * eeh_iommu_group_to_pe - Convert IOMMU group to EEH PE
1493  * @group: IOMMU group
1494  *
1495  * The routine is called to convert IOMMU group to EEH PE.
1496  */
eeh_iommu_group_to_pe(struct iommu_group * group)1497 struct eeh_pe *eeh_iommu_group_to_pe(struct iommu_group *group)
1498 {
1499 	struct pci_dev *pdev = NULL;
1500 	struct eeh_dev *edev;
1501 	int ret;
1502 
1503 	/* No IOMMU group ? */
1504 	if (!group)
1505 		return NULL;
1506 
1507 	ret = iommu_group_for_each_dev(group, &pdev, dev_has_iommu_table);
1508 	if (!ret || !pdev)
1509 		return NULL;
1510 
1511 	/* No EEH device or PE ? */
1512 	edev = pci_dev_to_eeh_dev(pdev);
1513 	if (!edev || !edev->pe)
1514 		return NULL;
1515 
1516 	return edev->pe;
1517 }
1518 EXPORT_SYMBOL_GPL(eeh_iommu_group_to_pe);
1519 
1520 #endif /* CONFIG_IOMMU_API */
1521 
1522 /**
1523  * eeh_pe_set_option - Set options for the indicated PE
1524  * @pe: EEH PE
1525  * @option: requested option
1526  *
1527  * The routine is called to enable or disable EEH functionality
1528  * on the indicated PE, to enable IO or DMA for the frozen PE.
1529  */
eeh_pe_set_option(struct eeh_pe * pe,int option)1530 int eeh_pe_set_option(struct eeh_pe *pe, int option)
1531 {
1532 	int ret = 0;
1533 
1534 	/* Invalid PE ? */
1535 	if (!pe)
1536 		return -ENODEV;
1537 
1538 	/*
1539 	 * EEH functionality could possibly be disabled, just
1540 	 * return error for the case. And the EEH functinality
1541 	 * isn't expected to be disabled on one specific PE.
1542 	 */
1543 	switch (option) {
1544 	case EEH_OPT_ENABLE:
1545 		if (eeh_enabled()) {
1546 			ret = eeh_pe_change_owner(pe);
1547 			break;
1548 		}
1549 		ret = -EIO;
1550 		break;
1551 	case EEH_OPT_DISABLE:
1552 		break;
1553 	case EEH_OPT_THAW_MMIO:
1554 	case EEH_OPT_THAW_DMA:
1555 	case EEH_OPT_FREEZE_PE:
1556 		if (!eeh_ops || !eeh_ops->set_option) {
1557 			ret = -ENOENT;
1558 			break;
1559 		}
1560 
1561 		ret = eeh_pci_enable(pe, option);
1562 		break;
1563 	default:
1564 		pr_debug("%s: Option %d out of range (%d, %d)\n",
1565 			__func__, option, EEH_OPT_DISABLE, EEH_OPT_THAW_DMA);
1566 		ret = -EINVAL;
1567 	}
1568 
1569 	return ret;
1570 }
1571 EXPORT_SYMBOL_GPL(eeh_pe_set_option);
1572 
1573 /**
1574  * eeh_pe_get_state - Retrieve PE's state
1575  * @pe: EEH PE
1576  *
1577  * Retrieve the PE's state, which includes 3 aspects: enabled
1578  * DMA, enabled IO and asserted reset.
1579  */
eeh_pe_get_state(struct eeh_pe * pe)1580 int eeh_pe_get_state(struct eeh_pe *pe)
1581 {
1582 	int result, ret = 0;
1583 	bool rst_active, dma_en, mmio_en;
1584 
1585 	/* Existing PE ? */
1586 	if (!pe)
1587 		return -ENODEV;
1588 
1589 	if (!eeh_ops || !eeh_ops->get_state)
1590 		return -ENOENT;
1591 
1592 	/*
1593 	 * If the parent PE is owned by the host kernel and is undergoing
1594 	 * error recovery, we should return the PE state as temporarily
1595 	 * unavailable so that the error recovery on the guest is suspended
1596 	 * until the recovery completes on the host.
1597 	 */
1598 	if (pe->parent &&
1599 	    !(pe->state & EEH_PE_REMOVED) &&
1600 	    (pe->parent->state & (EEH_PE_ISOLATED | EEH_PE_RECOVERING)))
1601 		return EEH_PE_STATE_UNAVAIL;
1602 
1603 	result = eeh_ops->get_state(pe, NULL);
1604 	rst_active = !!(result & EEH_STATE_RESET_ACTIVE);
1605 	dma_en = !!(result & EEH_STATE_DMA_ENABLED);
1606 	mmio_en = !!(result & EEH_STATE_MMIO_ENABLED);
1607 
1608 	if (rst_active)
1609 		ret = EEH_PE_STATE_RESET;
1610 	else if (dma_en && mmio_en)
1611 		ret = EEH_PE_STATE_NORMAL;
1612 	else if (!dma_en && !mmio_en)
1613 		ret = EEH_PE_STATE_STOPPED_IO_DMA;
1614 	else if (!dma_en && mmio_en)
1615 		ret = EEH_PE_STATE_STOPPED_DMA;
1616 	else
1617 		ret = EEH_PE_STATE_UNAVAIL;
1618 
1619 	return ret;
1620 }
1621 EXPORT_SYMBOL_GPL(eeh_pe_get_state);
1622 
eeh_pe_reenable_devices(struct eeh_pe * pe,bool include_passed)1623 static int eeh_pe_reenable_devices(struct eeh_pe *pe, bool include_passed)
1624 {
1625 	struct eeh_dev *edev, *tmp;
1626 	struct pci_dev *pdev;
1627 	int ret = 0;
1628 
1629 	eeh_pe_restore_bars(pe);
1630 
1631 	/*
1632 	 * Reenable PCI devices as the devices passed
1633 	 * through are always enabled before the reset.
1634 	 */
1635 	eeh_pe_for_each_dev(pe, edev, tmp) {
1636 		pdev = eeh_dev_to_pci_dev(edev);
1637 		if (!pdev)
1638 			continue;
1639 
1640 		ret = pci_reenable_device(pdev);
1641 		if (ret) {
1642 			pr_warn("%s: Failure %d reenabling %s\n",
1643 				__func__, ret, pci_name(pdev));
1644 			return ret;
1645 		}
1646 	}
1647 
1648 	/* The PE is still in frozen state */
1649 	if (include_passed || !eeh_pe_passed(pe)) {
1650 		ret = eeh_unfreeze_pe(pe);
1651 	} else
1652 		pr_info("EEH: Note: Leaving passthrough PHB#%x-PE#%x frozen.\n",
1653 			pe->phb->global_number, pe->addr);
1654 	if (!ret)
1655 		eeh_pe_state_clear(pe, EEH_PE_ISOLATED, include_passed);
1656 	return ret;
1657 }
1658 
1659 
1660 /**
1661  * eeh_pe_reset - Issue PE reset according to specified type
1662  * @pe: EEH PE
1663  * @option: reset type
1664  *
1665  * The routine is called to reset the specified PE with the
1666  * indicated type, either fundamental reset or hot reset.
1667  * PE reset is the most important part for error recovery.
1668  */
eeh_pe_reset(struct eeh_pe * pe,int option,bool include_passed)1669 int eeh_pe_reset(struct eeh_pe *pe, int option, bool include_passed)
1670 {
1671 	int ret = 0;
1672 
1673 	/* Invalid PE ? */
1674 	if (!pe)
1675 		return -ENODEV;
1676 
1677 	if (!eeh_ops || !eeh_ops->set_option || !eeh_ops->reset)
1678 		return -ENOENT;
1679 
1680 	switch (option) {
1681 	case EEH_RESET_DEACTIVATE:
1682 		ret = eeh_ops->reset(pe, option);
1683 		eeh_pe_state_clear(pe, EEH_PE_CFG_BLOCKED, include_passed);
1684 		if (ret)
1685 			break;
1686 
1687 		ret = eeh_pe_reenable_devices(pe, include_passed);
1688 		break;
1689 	case EEH_RESET_HOT:
1690 	case EEH_RESET_FUNDAMENTAL:
1691 		/*
1692 		 * Proactively freeze the PE to drop all MMIO access
1693 		 * during reset, which should be banned as it's always
1694 		 * cause recursive EEH error.
1695 		 */
1696 		eeh_ops->set_option(pe, EEH_OPT_FREEZE_PE);
1697 
1698 		eeh_pe_state_mark(pe, EEH_PE_CFG_BLOCKED);
1699 		ret = eeh_ops->reset(pe, option);
1700 		break;
1701 	default:
1702 		pr_debug("%s: Unsupported option %d\n",
1703 			__func__, option);
1704 		ret = -EINVAL;
1705 	}
1706 
1707 	return ret;
1708 }
1709 EXPORT_SYMBOL_GPL(eeh_pe_reset);
1710 
1711 /**
1712  * eeh_pe_configure - Configure PCI bridges after PE reset
1713  * @pe: EEH PE
1714  *
1715  * The routine is called to restore the PCI config space for
1716  * those PCI devices, especially PCI bridges affected by PE
1717  * reset issued previously.
1718  */
eeh_pe_configure(struct eeh_pe * pe)1719 int eeh_pe_configure(struct eeh_pe *pe)
1720 {
1721 	int ret = 0;
1722 
1723 	/* Invalid PE ? */
1724 	if (!pe)
1725 		return -ENODEV;
1726 
1727 	return ret;
1728 }
1729 EXPORT_SYMBOL_GPL(eeh_pe_configure);
1730 
1731 /**
1732  * eeh_pe_inject_err - Injecting the specified PCI error to the indicated PE
1733  * @pe: the indicated PE
1734  * @type: error type
1735  * @function: error function
1736  * @addr: address
1737  * @mask: address mask
1738  *
1739  * The routine is called to inject the specified PCI error, which
1740  * is determined by @type and @function, to the indicated PE for
1741  * testing purpose.
1742  */
eeh_pe_inject_err(struct eeh_pe * pe,int type,int func,unsigned long addr,unsigned long mask)1743 int eeh_pe_inject_err(struct eeh_pe *pe, int type, int func,
1744 		      unsigned long addr, unsigned long mask)
1745 {
1746 	/* Invalid PE ? */
1747 	if (!pe)
1748 		return -ENODEV;
1749 
1750 	/* Unsupported operation ? */
1751 	if (!eeh_ops || !eeh_ops->err_inject)
1752 		return -ENOENT;
1753 
1754 	/* Check on PCI error type */
1755 	if (type != EEH_ERR_TYPE_32 && type != EEH_ERR_TYPE_64)
1756 		return -EINVAL;
1757 
1758 	/* Check on PCI error function */
1759 	if (func < EEH_ERR_FUNC_MIN || func > EEH_ERR_FUNC_MAX)
1760 		return -EINVAL;
1761 
1762 	return eeh_ops->err_inject(pe, type, func, addr, mask);
1763 }
1764 EXPORT_SYMBOL_GPL(eeh_pe_inject_err);
1765 
proc_eeh_show(struct seq_file * m,void * v)1766 static int proc_eeh_show(struct seq_file *m, void *v)
1767 {
1768 	if (!eeh_enabled()) {
1769 		seq_printf(m, "EEH Subsystem is globally disabled\n");
1770 		seq_printf(m, "eeh_total_mmio_ffs=%llu\n", eeh_stats.total_mmio_ffs);
1771 	} else {
1772 		seq_printf(m, "EEH Subsystem is enabled\n");
1773 		seq_printf(m,
1774 				"no device=%llu\n"
1775 				"no device node=%llu\n"
1776 				"no config address=%llu\n"
1777 				"check not wanted=%llu\n"
1778 				"eeh_total_mmio_ffs=%llu\n"
1779 				"eeh_false_positives=%llu\n"
1780 				"eeh_slot_resets=%llu\n",
1781 				eeh_stats.no_device,
1782 				eeh_stats.no_dn,
1783 				eeh_stats.no_cfg_addr,
1784 				eeh_stats.ignored_check,
1785 				eeh_stats.total_mmio_ffs,
1786 				eeh_stats.false_positives,
1787 				eeh_stats.slot_resets);
1788 	}
1789 
1790 	return 0;
1791 }
1792 
1793 #ifdef CONFIG_DEBUG_FS
eeh_enable_dbgfs_set(void * data,u64 val)1794 static int eeh_enable_dbgfs_set(void *data, u64 val)
1795 {
1796 	if (val)
1797 		eeh_clear_flag(EEH_FORCE_DISABLED);
1798 	else
1799 		eeh_add_flag(EEH_FORCE_DISABLED);
1800 
1801 	return 0;
1802 }
1803 
eeh_enable_dbgfs_get(void * data,u64 * val)1804 static int eeh_enable_dbgfs_get(void *data, u64 *val)
1805 {
1806 	if (eeh_enabled())
1807 		*val = 0x1ul;
1808 	else
1809 		*val = 0x0ul;
1810 	return 0;
1811 }
1812 
1813 DEFINE_DEBUGFS_ATTRIBUTE(eeh_enable_dbgfs_ops, eeh_enable_dbgfs_get,
1814 			 eeh_enable_dbgfs_set, "0x%llx\n");
1815 
eeh_force_recover_write(struct file * filp,const char __user * user_buf,size_t count,loff_t * ppos)1816 static ssize_t eeh_force_recover_write(struct file *filp,
1817 				const char __user *user_buf,
1818 				size_t count, loff_t *ppos)
1819 {
1820 	struct pci_controller *hose;
1821 	uint32_t phbid, pe_no;
1822 	struct eeh_pe *pe;
1823 	char buf[20];
1824 	int ret;
1825 
1826 	ret = simple_write_to_buffer(buf, sizeof(buf), ppos, user_buf, count);
1827 	if (!ret)
1828 		return -EFAULT;
1829 
1830 	/*
1831 	 * When PE is NULL the event is a "special" event. Rather than
1832 	 * recovering a specific PE it forces the EEH core to scan for failed
1833 	 * PHBs and recovers each. This needs to be done before any device
1834 	 * recoveries can occur.
1835 	 */
1836 	if (!strncmp(buf, "hwcheck", 7)) {
1837 		__eeh_send_failure_event(NULL);
1838 		return count;
1839 	}
1840 
1841 	ret = sscanf(buf, "%x:%x", &phbid, &pe_no);
1842 	if (ret != 2)
1843 		return -EINVAL;
1844 
1845 	hose = pci_find_controller_for_domain(phbid);
1846 	if (!hose)
1847 		return -ENODEV;
1848 
1849 	/* Retrieve PE */
1850 	pe = eeh_pe_get(hose, pe_no, 0);
1851 	if (!pe)
1852 		return -ENODEV;
1853 
1854 	/*
1855 	 * We don't do any state checking here since the detection
1856 	 * process is async to the recovery process. The recovery
1857 	 * thread *should* not break even if we schedule a recovery
1858 	 * from an odd state (e.g. PE removed, or recovery of a
1859 	 * non-isolated PE)
1860 	 */
1861 	__eeh_send_failure_event(pe);
1862 
1863 	return ret < 0 ? ret : count;
1864 }
1865 
1866 static const struct file_operations eeh_force_recover_fops = {
1867 	.open	= simple_open,
1868 	.llseek	= no_llseek,
1869 	.write	= eeh_force_recover_write,
1870 };
1871 
eeh_debugfs_dev_usage(struct file * filp,char __user * user_buf,size_t count,loff_t * ppos)1872 static ssize_t eeh_debugfs_dev_usage(struct file *filp,
1873 				char __user *user_buf,
1874 				size_t count, loff_t *ppos)
1875 {
1876 	static const char usage[] = "input format: <domain>:<bus>:<dev>.<fn>\n";
1877 
1878 	return simple_read_from_buffer(user_buf, count, ppos,
1879 				       usage, sizeof(usage) - 1);
1880 }
1881 
eeh_dev_check_write(struct file * filp,const char __user * user_buf,size_t count,loff_t * ppos)1882 static ssize_t eeh_dev_check_write(struct file *filp,
1883 				const char __user *user_buf,
1884 				size_t count, loff_t *ppos)
1885 {
1886 	uint32_t domain, bus, dev, fn;
1887 	struct pci_dev *pdev;
1888 	struct eeh_dev *edev;
1889 	char buf[20];
1890 	int ret;
1891 
1892 	memset(buf, 0, sizeof(buf));
1893 	ret = simple_write_to_buffer(buf, sizeof(buf)-1, ppos, user_buf, count);
1894 	if (!ret)
1895 		return -EFAULT;
1896 
1897 	ret = sscanf(buf, "%x:%x:%x.%x", &domain, &bus, &dev, &fn);
1898 	if (ret != 4) {
1899 		pr_err("%s: expected 4 args, got %d\n", __func__, ret);
1900 		return -EINVAL;
1901 	}
1902 
1903 	pdev = pci_get_domain_bus_and_slot(domain, bus, (dev << 3) | fn);
1904 	if (!pdev)
1905 		return -ENODEV;
1906 
1907 	edev = pci_dev_to_eeh_dev(pdev);
1908 	if (!edev) {
1909 		pci_err(pdev, "No eeh_dev for this device!\n");
1910 		pci_dev_put(pdev);
1911 		return -ENODEV;
1912 	}
1913 
1914 	ret = eeh_dev_check_failure(edev);
1915 	pci_info(pdev, "eeh_dev_check_failure(%04x:%02x:%02x.%01x) = %d\n",
1916 			domain, bus, dev, fn, ret);
1917 
1918 	pci_dev_put(pdev);
1919 
1920 	return count;
1921 }
1922 
1923 static const struct file_operations eeh_dev_check_fops = {
1924 	.open	= simple_open,
1925 	.llseek	= no_llseek,
1926 	.write	= eeh_dev_check_write,
1927 	.read   = eeh_debugfs_dev_usage,
1928 };
1929 
eeh_debugfs_break_device(struct pci_dev * pdev)1930 static int eeh_debugfs_break_device(struct pci_dev *pdev)
1931 {
1932 	struct resource *bar = NULL;
1933 	void __iomem *mapped;
1934 	u16 old, bit;
1935 	int i, pos;
1936 
1937 	/* Do we have an MMIO BAR to disable? */
1938 	for (i = 0; i <= PCI_STD_RESOURCE_END; i++) {
1939 		struct resource *r = &pdev->resource[i];
1940 
1941 		if (!r->flags || !r->start)
1942 			continue;
1943 		if (r->flags & IORESOURCE_IO)
1944 			continue;
1945 		if (r->flags & IORESOURCE_UNSET)
1946 			continue;
1947 
1948 		bar = r;
1949 		break;
1950 	}
1951 
1952 	if (!bar) {
1953 		pci_err(pdev, "Unable to find Memory BAR to cause EEH with\n");
1954 		return -ENXIO;
1955 	}
1956 
1957 	pci_err(pdev, "Going to break: %pR\n", bar);
1958 
1959 	if (pdev->is_virtfn) {
1960 #ifndef CONFIG_PCI_IOV
1961 		return -ENXIO;
1962 #else
1963 		/*
1964 		 * VFs don't have a per-function COMMAND register, so the best
1965 		 * we can do is clear the Memory Space Enable bit in the PF's
1966 		 * SRIOV control reg.
1967 		 *
1968 		 * Unfortunately, this requires that we have a PF (i.e doesn't
1969 		 * work for a passed-through VF) and it has the potential side
1970 		 * effect of also causing an EEH on every other VF under the
1971 		 * PF. Oh well.
1972 		 */
1973 		pdev = pdev->physfn;
1974 		if (!pdev)
1975 			return -ENXIO; /* passed through VFs have no PF */
1976 
1977 		pos  = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
1978 		pos += PCI_SRIOV_CTRL;
1979 		bit  = PCI_SRIOV_CTRL_MSE;
1980 #endif /* !CONFIG_PCI_IOV */
1981 	} else {
1982 		bit = PCI_COMMAND_MEMORY;
1983 		pos = PCI_COMMAND;
1984 	}
1985 
1986 	/*
1987 	 * Process here is:
1988 	 *
1989 	 * 1. Disable Memory space.
1990 	 *
1991 	 * 2. Perform an MMIO to the device. This should result in an error
1992 	 *    (CA  / UR) being raised by the device which results in an EEH
1993 	 *    PE freeze. Using the in_8() accessor skips the eeh detection hook
1994 	 *    so the freeze hook so the EEH Detection machinery won't be
1995 	 *    triggered here. This is to match the usual behaviour of EEH
1996 	 *    where the HW will asyncronously freeze a PE and it's up to
1997 	 *    the kernel to notice and deal with it.
1998 	 *
1999 	 * 3. Turn Memory space back on. This is more important for VFs
2000 	 *    since recovery will probably fail if we don't. For normal
2001 	 *    the COMMAND register is reset as a part of re-initialising
2002 	 *    the device.
2003 	 *
2004 	 * Breaking stuff is the point so who cares if it's racy ;)
2005 	 */
2006 	pci_read_config_word(pdev, pos, &old);
2007 
2008 	mapped = ioremap(bar->start, PAGE_SIZE);
2009 	if (!mapped) {
2010 		pci_err(pdev, "Unable to map MMIO BAR %pR\n", bar);
2011 		return -ENXIO;
2012 	}
2013 
2014 	pci_write_config_word(pdev, pos, old & ~bit);
2015 	in_8(mapped);
2016 	pci_write_config_word(pdev, pos, old);
2017 
2018 	iounmap(mapped);
2019 
2020 	return 0;
2021 }
2022 
eeh_dev_break_write(struct file * filp,const char __user * user_buf,size_t count,loff_t * ppos)2023 static ssize_t eeh_dev_break_write(struct file *filp,
2024 				const char __user *user_buf,
2025 				size_t count, loff_t *ppos)
2026 {
2027 	uint32_t domain, bus, dev, fn;
2028 	struct pci_dev *pdev;
2029 	char buf[20];
2030 	int ret;
2031 
2032 	memset(buf, 0, sizeof(buf));
2033 	ret = simple_write_to_buffer(buf, sizeof(buf)-1, ppos, user_buf, count);
2034 	if (!ret)
2035 		return -EFAULT;
2036 
2037 	ret = sscanf(buf, "%x:%x:%x.%x", &domain, &bus, &dev, &fn);
2038 	if (ret != 4) {
2039 		pr_err("%s: expected 4 args, got %d\n", __func__, ret);
2040 		return -EINVAL;
2041 	}
2042 
2043 	pdev = pci_get_domain_bus_and_slot(domain, bus, (dev << 3) | fn);
2044 	if (!pdev)
2045 		return -ENODEV;
2046 
2047 	ret = eeh_debugfs_break_device(pdev);
2048 	pci_dev_put(pdev);
2049 
2050 	if (ret < 0)
2051 		return ret;
2052 
2053 	return count;
2054 }
2055 
2056 static const struct file_operations eeh_dev_break_fops = {
2057 	.open	= simple_open,
2058 	.llseek	= no_llseek,
2059 	.write	= eeh_dev_break_write,
2060 	.read   = eeh_debugfs_dev_usage,
2061 };
2062 
2063 #endif
2064 
eeh_init_proc(void)2065 static int __init eeh_init_proc(void)
2066 {
2067 	if (machine_is(pseries) || machine_is(powernv)) {
2068 		proc_create_single("powerpc/eeh", 0, NULL, proc_eeh_show);
2069 #ifdef CONFIG_DEBUG_FS
2070 		debugfs_create_file_unsafe("eeh_enable", 0600,
2071 					   powerpc_debugfs_root, NULL,
2072 					   &eeh_enable_dbgfs_ops);
2073 		debugfs_create_u32("eeh_max_freezes", 0600,
2074 				powerpc_debugfs_root, &eeh_max_freezes);
2075 		debugfs_create_bool("eeh_disable_recovery", 0600,
2076 				powerpc_debugfs_root,
2077 				&eeh_debugfs_no_recover);
2078 		debugfs_create_file_unsafe("eeh_dev_check", 0600,
2079 				powerpc_debugfs_root, NULL,
2080 				&eeh_dev_check_fops);
2081 		debugfs_create_file_unsafe("eeh_dev_break", 0600,
2082 				powerpc_debugfs_root, NULL,
2083 				&eeh_dev_break_fops);
2084 		debugfs_create_file_unsafe("eeh_force_recover", 0600,
2085 				powerpc_debugfs_root, NULL,
2086 				&eeh_force_recover_fops);
2087 		eeh_cache_debugfs_init();
2088 #endif
2089 	}
2090 
2091 	return 0;
2092 }
2093 __initcall(eeh_init_proc);
2094