1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * MPC83xx/85xx/86xx PCI/PCIE support routing.
4 *
5 * Copyright 2007-2012 Freescale Semiconductor, Inc.
6 * Copyright 2008-2009 MontaVista Software, Inc.
7 *
8 * Initial author: Xianghua Xiao <x.xiao@freescale.com>
9 * Recode: ZHANG WEI <wei.zhang@freescale.com>
10 * Rewrite the routing for Frescale PCI and PCI Express
11 * Roy Zang <tie-fei.zang@freescale.com>
12 * MPC83xx PCI-Express support:
13 * Tony Li <tony.li@freescale.com>
14 * Anton Vorontsov <avorontsov@ru.mvista.com>
15 */
16 #include <linux/kernel.h>
17 #include <linux/pci.h>
18 #include <linux/delay.h>
19 #include <linux/string.h>
20 #include <linux/fsl/edac.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/memblock.h>
24 #include <linux/log2.h>
25 #include <linux/platform_device.h>
26 #include <linux/slab.h>
27 #include <linux/suspend.h>
28 #include <linux/syscore_ops.h>
29 #include <linux/uaccess.h>
30
31 #include <asm/io.h>
32 #include <asm/prom.h>
33 #include <asm/pci-bridge.h>
34 #include <asm/ppc-pci.h>
35 #include <asm/machdep.h>
36 #include <asm/mpc85xx.h>
37 #include <asm/disassemble.h>
38 #include <asm/ppc-opcode.h>
39 #include <asm/swiotlb.h>
40 #include <sysdev/fsl_soc.h>
41 #include <sysdev/fsl_pci.h>
42
43 static int fsl_pcie_bus_fixup, is_mpc83xx_pci;
44
quirk_fsl_pcie_early(struct pci_dev * dev)45 static void quirk_fsl_pcie_early(struct pci_dev *dev)
46 {
47 u8 hdr_type;
48
49 /* if we aren't a PCIe don't bother */
50 if (!pci_is_pcie(dev))
51 return;
52
53 /* if we aren't in host mode don't bother */
54 pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type);
55 if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE)
56 return;
57
58 dev->class = PCI_CLASS_BRIDGE_PCI << 8;
59 fsl_pcie_bus_fixup = 1;
60 return;
61 }
62
63 static int fsl_indirect_read_config(struct pci_bus *, unsigned int,
64 int, int, u32 *);
65
fsl_pcie_check_link(struct pci_controller * hose)66 static int fsl_pcie_check_link(struct pci_controller *hose)
67 {
68 u32 val = 0;
69
70 if (hose->indirect_type & PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK) {
71 if (hose->ops->read == fsl_indirect_read_config)
72 __indirect_read_config(hose, hose->first_busno, 0,
73 PCIE_LTSSM, 4, &val);
74 else
75 early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
76 if (val < PCIE_LTSSM_L0)
77 return 1;
78 } else {
79 struct ccsr_pci __iomem *pci = hose->private_data;
80 /* for PCIe IP rev 3.0 or greater use CSR0 for link state */
81 val = (in_be32(&pci->pex_csr0) & PEX_CSR0_LTSSM_MASK)
82 >> PEX_CSR0_LTSSM_SHIFT;
83 if (val != PEX_CSR0_LTSSM_L0)
84 return 1;
85 }
86
87 return 0;
88 }
89
fsl_indirect_read_config(struct pci_bus * bus,unsigned int devfn,int offset,int len,u32 * val)90 static int fsl_indirect_read_config(struct pci_bus *bus, unsigned int devfn,
91 int offset, int len, u32 *val)
92 {
93 struct pci_controller *hose = pci_bus_to_host(bus);
94
95 if (fsl_pcie_check_link(hose))
96 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
97 else
98 hose->indirect_type &= ~PPC_INDIRECT_TYPE_NO_PCIE_LINK;
99
100 return indirect_read_config(bus, devfn, offset, len, val);
101 }
102
103 #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
104
105 static struct pci_ops fsl_indirect_pcie_ops =
106 {
107 .read = fsl_indirect_read_config,
108 .write = indirect_write_config,
109 };
110
111 static u64 pci64_dma_offset;
112
113 #ifdef CONFIG_SWIOTLB
pci_dma_dev_setup_swiotlb(struct pci_dev * pdev)114 static void pci_dma_dev_setup_swiotlb(struct pci_dev *pdev)
115 {
116 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
117
118 pdev->dev.bus_dma_mask =
119 hose->dma_window_base_cur + hose->dma_window_size;
120 }
121
setup_swiotlb_ops(struct pci_controller * hose)122 static void setup_swiotlb_ops(struct pci_controller *hose)
123 {
124 if (ppc_swiotlb_enable)
125 hose->controller_ops.dma_dev_setup = pci_dma_dev_setup_swiotlb;
126 }
127 #else
setup_swiotlb_ops(struct pci_controller * hose)128 static inline void setup_swiotlb_ops(struct pci_controller *hose) {}
129 #endif
130
fsl_pci_dma_set_mask(struct device * dev,u64 dma_mask)131 static void fsl_pci_dma_set_mask(struct device *dev, u64 dma_mask)
132 {
133 /*
134 * Fix up PCI devices that are able to DMA to the large inbound
135 * mapping that allows addressing any RAM address from across PCI.
136 */
137 if (dev_is_pci(dev) && dma_mask >= pci64_dma_offset * 2 - 1) {
138 dev->bus_dma_mask = 0;
139 dev->archdata.dma_offset = pci64_dma_offset;
140 }
141 }
142
setup_one_atmu(struct ccsr_pci __iomem * pci,unsigned int index,const struct resource * res,resource_size_t offset)143 static int setup_one_atmu(struct ccsr_pci __iomem *pci,
144 unsigned int index, const struct resource *res,
145 resource_size_t offset)
146 {
147 resource_size_t pci_addr = res->start - offset;
148 resource_size_t phys_addr = res->start;
149 resource_size_t size = resource_size(res);
150 u32 flags = 0x80044000; /* enable & mem R/W */
151 unsigned int i;
152
153 pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n",
154 (u64)res->start, (u64)size);
155
156 if (res->flags & IORESOURCE_PREFETCH)
157 flags |= 0x10000000; /* enable relaxed ordering */
158
159 for (i = 0; size > 0; i++) {
160 unsigned int bits = min_t(u32, ilog2(size),
161 __ffs(pci_addr | phys_addr));
162
163 if (index + i >= 5)
164 return -1;
165
166 out_be32(&pci->pow[index + i].potar, pci_addr >> 12);
167 out_be32(&pci->pow[index + i].potear, (u64)pci_addr >> 44);
168 out_be32(&pci->pow[index + i].powbar, phys_addr >> 12);
169 out_be32(&pci->pow[index + i].powar, flags | (bits - 1));
170
171 pci_addr += (resource_size_t)1U << bits;
172 phys_addr += (resource_size_t)1U << bits;
173 size -= (resource_size_t)1U << bits;
174 }
175
176 return i;
177 }
178
is_kdump(void)179 static bool is_kdump(void)
180 {
181 struct device_node *node;
182
183 node = of_find_node_by_type(NULL, "memory");
184 if (!node) {
185 WARN_ON_ONCE(1);
186 return false;
187 }
188
189 return of_property_read_bool(node, "linux,usable-memory");
190 }
191
192 /* atmu setup for fsl pci/pcie controller */
setup_pci_atmu(struct pci_controller * hose)193 static void setup_pci_atmu(struct pci_controller *hose)
194 {
195 struct ccsr_pci __iomem *pci = hose->private_data;
196 int i, j, n, mem_log, win_idx = 3, start_idx = 1, end_idx = 4;
197 u64 mem, sz, paddr_hi = 0;
198 u64 offset = 0, paddr_lo = ULLONG_MAX;
199 u32 pcicsrbar = 0, pcicsrbar_sz;
200 u32 piwar = PIWAR_EN | PIWAR_PF | PIWAR_TGI_LOCAL |
201 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
202 const u64 *reg;
203 int len;
204 bool setup_inbound;
205
206 /*
207 * If this is kdump, we don't want to trigger a bunch of PCI
208 * errors by closing the window on in-flight DMA.
209 *
210 * We still run most of the function's logic so that things like
211 * hose->dma_window_size still get set.
212 */
213 setup_inbound = !is_kdump();
214
215 if (of_device_is_compatible(hose->dn, "fsl,bsc9132-pcie")) {
216 /*
217 * BSC9132 Rev1.0 has an issue where all the PEX inbound
218 * windows have implemented the default target value as 0xf
219 * for CCSR space.In all Freescale legacy devices the target
220 * of 0xf is reserved for local memory space. 9132 Rev1.0
221 * now has local mempry space mapped to target 0x0 instead of
222 * 0xf. Hence adding a workaround to remove the target 0xf
223 * defined for memory space from Inbound window attributes.
224 */
225 piwar &= ~PIWAR_TGI_LOCAL;
226 }
227
228 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
229 if (in_be32(&pci->block_rev1) >= PCIE_IP_REV_2_2) {
230 win_idx = 2;
231 start_idx = 0;
232 end_idx = 3;
233 }
234 }
235
236 /* Disable all windows (except powar0 since it's ignored) */
237 for(i = 1; i < 5; i++)
238 out_be32(&pci->pow[i].powar, 0);
239
240 if (setup_inbound) {
241 for (i = start_idx; i < end_idx; i++)
242 out_be32(&pci->piw[i].piwar, 0);
243 }
244
245 /* Setup outbound MEM window */
246 for(i = 0, j = 1; i < 3; i++) {
247 if (!(hose->mem_resources[i].flags & IORESOURCE_MEM))
248 continue;
249
250 paddr_lo = min(paddr_lo, (u64)hose->mem_resources[i].start);
251 paddr_hi = max(paddr_hi, (u64)hose->mem_resources[i].end);
252
253 /* We assume all memory resources have the same offset */
254 offset = hose->mem_offset[i];
255 n = setup_one_atmu(pci, j, &hose->mem_resources[i], offset);
256
257 if (n < 0 || j >= 5) {
258 pr_err("Ran out of outbound PCI ATMUs for resource %d!\n", i);
259 hose->mem_resources[i].flags |= IORESOURCE_DISABLED;
260 } else
261 j += n;
262 }
263
264 /* Setup outbound IO window */
265 if (hose->io_resource.flags & IORESOURCE_IO) {
266 if (j >= 5) {
267 pr_err("Ran out of outbound PCI ATMUs for IO resource\n");
268 } else {
269 pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, "
270 "phy base 0x%016llx.\n",
271 (u64)hose->io_resource.start,
272 (u64)resource_size(&hose->io_resource),
273 (u64)hose->io_base_phys);
274 out_be32(&pci->pow[j].potar, (hose->io_resource.start >> 12));
275 out_be32(&pci->pow[j].potear, 0);
276 out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12));
277 /* Enable, IO R/W */
278 out_be32(&pci->pow[j].powar, 0x80088000
279 | (ilog2(hose->io_resource.end
280 - hose->io_resource.start + 1) - 1));
281 }
282 }
283
284 /* convert to pci address space */
285 paddr_hi -= offset;
286 paddr_lo -= offset;
287
288 if (paddr_hi == paddr_lo) {
289 pr_err("%pOF: No outbound window space\n", hose->dn);
290 return;
291 }
292
293 if (paddr_lo == 0) {
294 pr_err("%pOF: No space for inbound window\n", hose->dn);
295 return;
296 }
297
298 /* setup PCSRBAR/PEXCSRBAR */
299 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, 0xffffffff);
300 early_read_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, &pcicsrbar_sz);
301 pcicsrbar_sz = ~pcicsrbar_sz + 1;
302
303 if (paddr_hi < (0x100000000ull - pcicsrbar_sz) ||
304 (paddr_lo > 0x100000000ull))
305 pcicsrbar = 0x100000000ull - pcicsrbar_sz;
306 else
307 pcicsrbar = (paddr_lo - pcicsrbar_sz) & -pcicsrbar_sz;
308 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, pcicsrbar);
309
310 paddr_lo = min(paddr_lo, (u64)pcicsrbar);
311
312 pr_info("%pOF: PCICSRBAR @ 0x%x\n", hose->dn, pcicsrbar);
313
314 /* Setup inbound mem window */
315 mem = memblock_end_of_DRAM();
316 pr_info("%s: end of DRAM %llx\n", __func__, mem);
317
318 /*
319 * The msi-address-64 property, if it exists, indicates the physical
320 * address of the MSIIR register. Normally, this register is located
321 * inside CCSR, so the ATMU that covers all of CCSR is used. But if
322 * this property exists, then we normally need to create a new ATMU
323 * for it. For now, however, we cheat. The only entity that creates
324 * this property is the Freescale hypervisor, and the address is
325 * specified in the partition configuration. Typically, the address
326 * is located in the page immediately after the end of DDR. If so, we
327 * can avoid allocating a new ATMU by extending the DDR ATMU by one
328 * page.
329 */
330 reg = of_get_property(hose->dn, "msi-address-64", &len);
331 if (reg && (len == sizeof(u64))) {
332 u64 address = be64_to_cpup(reg);
333
334 if ((address >= mem) && (address < (mem + PAGE_SIZE))) {
335 pr_info("%pOF: extending DDR ATMU to cover MSIIR", hose->dn);
336 mem += PAGE_SIZE;
337 } else {
338 /* TODO: Create a new ATMU for MSIIR */
339 pr_warn("%pOF: msi-address-64 address of %llx is "
340 "unsupported\n", hose->dn, address);
341 }
342 }
343
344 sz = min(mem, paddr_lo);
345 mem_log = ilog2(sz);
346
347 /* PCIe can overmap inbound & outbound since RX & TX are separated */
348 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
349 /* Size window to exact size if power-of-two or one size up */
350 if ((1ull << mem_log) != mem) {
351 mem_log++;
352 if ((1ull << mem_log) > mem)
353 pr_info("%pOF: Setting PCI inbound window "
354 "greater than memory size\n", hose->dn);
355 }
356
357 piwar |= ((mem_log - 1) & PIWAR_SZ_MASK);
358
359 if (setup_inbound) {
360 /* Setup inbound memory window */
361 out_be32(&pci->piw[win_idx].pitar, 0x00000000);
362 out_be32(&pci->piw[win_idx].piwbar, 0x00000000);
363 out_be32(&pci->piw[win_idx].piwar, piwar);
364 }
365
366 win_idx--;
367 hose->dma_window_base_cur = 0x00000000;
368 hose->dma_window_size = (resource_size_t)sz;
369
370 /*
371 * if we have >4G of memory setup second PCI inbound window to
372 * let devices that are 64-bit address capable to work w/o
373 * SWIOTLB and access the full range of memory
374 */
375 if (sz != mem) {
376 mem_log = ilog2(mem);
377
378 /* Size window up if we dont fit in exact power-of-2 */
379 if ((1ull << mem_log) != mem)
380 mem_log++;
381
382 piwar = (piwar & ~PIWAR_SZ_MASK) | (mem_log - 1);
383 pci64_dma_offset = 1ULL << mem_log;
384
385 if (setup_inbound) {
386 /* Setup inbound memory window */
387 out_be32(&pci->piw[win_idx].pitar, 0x00000000);
388 out_be32(&pci->piw[win_idx].piwbear,
389 pci64_dma_offset >> 44);
390 out_be32(&pci->piw[win_idx].piwbar,
391 pci64_dma_offset >> 12);
392 out_be32(&pci->piw[win_idx].piwar, piwar);
393 }
394
395 /*
396 * install our own dma_set_mask handler to fixup dma_ops
397 * and dma_offset
398 */
399 ppc_md.dma_set_mask = fsl_pci_dma_set_mask;
400
401 pr_info("%pOF: Setup 64-bit PCI DMA window\n", hose->dn);
402 }
403 } else {
404 u64 paddr = 0;
405
406 if (setup_inbound) {
407 /* Setup inbound memory window */
408 out_be32(&pci->piw[win_idx].pitar, paddr >> 12);
409 out_be32(&pci->piw[win_idx].piwbar, paddr >> 12);
410 out_be32(&pci->piw[win_idx].piwar,
411 (piwar | (mem_log - 1)));
412 }
413
414 win_idx--;
415 paddr += 1ull << mem_log;
416 sz -= 1ull << mem_log;
417
418 if (sz) {
419 mem_log = ilog2(sz);
420 piwar |= (mem_log - 1);
421
422 if (setup_inbound) {
423 out_be32(&pci->piw[win_idx].pitar,
424 paddr >> 12);
425 out_be32(&pci->piw[win_idx].piwbar,
426 paddr >> 12);
427 out_be32(&pci->piw[win_idx].piwar, piwar);
428 }
429
430 win_idx--;
431 paddr += 1ull << mem_log;
432 }
433
434 hose->dma_window_base_cur = 0x00000000;
435 hose->dma_window_size = (resource_size_t)paddr;
436 }
437
438 if (hose->dma_window_size < mem) {
439 #ifdef CONFIG_SWIOTLB
440 ppc_swiotlb_enable = 1;
441 #else
442 pr_err("%pOF: ERROR: Memory size exceeds PCI ATMU ability to "
443 "map - enable CONFIG_SWIOTLB to avoid dma errors.\n",
444 hose->dn);
445 #endif
446 /* adjusting outbound windows could reclaim space in mem map */
447 if (paddr_hi < 0xffffffffull)
448 pr_warn("%pOF: WARNING: Outbound window cfg leaves "
449 "gaps in memory map. Adjusting the memory map "
450 "could reduce unnecessary bounce buffering.\n",
451 hose->dn);
452
453 pr_info("%pOF: DMA window size is 0x%llx\n", hose->dn,
454 (u64)hose->dma_window_size);
455 }
456 }
457
setup_pci_cmd(struct pci_controller * hose)458 static void __init setup_pci_cmd(struct pci_controller *hose)
459 {
460 u16 cmd;
461 int cap_x;
462
463 early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
464 cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
465 | PCI_COMMAND_IO;
466 early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
467
468 cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX);
469 if (cap_x) {
470 int pci_x_cmd = cap_x + PCI_X_CMD;
471 cmd = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
472 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
473 early_write_config_word(hose, 0, 0, pci_x_cmd, cmd);
474 } else {
475 early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
476 }
477 }
478
fsl_pcibios_fixup_bus(struct pci_bus * bus)479 void fsl_pcibios_fixup_bus(struct pci_bus *bus)
480 {
481 struct pci_controller *hose = pci_bus_to_host(bus);
482 int i, is_pcie = 0, no_link;
483
484 /* The root complex bridge comes up with bogus resources,
485 * we copy the PHB ones in.
486 *
487 * With the current generic PCI code, the PHB bus no longer
488 * has bus->resource[0..4] set, so things are a bit more
489 * tricky.
490 */
491
492 if (fsl_pcie_bus_fixup)
493 is_pcie = early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP);
494 no_link = !!(hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK);
495
496 if (bus->parent == hose->bus && (is_pcie || no_link)) {
497 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; ++i) {
498 struct resource *res = bus->resource[i];
499 struct resource *par;
500
501 if (!res)
502 continue;
503 if (i == 0)
504 par = &hose->io_resource;
505 else if (i < 4)
506 par = &hose->mem_resources[i-1];
507 else par = NULL;
508
509 res->start = par ? par->start : 0;
510 res->end = par ? par->end : 0;
511 res->flags = par ? par->flags : 0;
512 }
513 }
514 }
515
fsl_add_bridge(struct platform_device * pdev,int is_primary)516 int fsl_add_bridge(struct platform_device *pdev, int is_primary)
517 {
518 int len;
519 struct pci_controller *hose;
520 struct resource rsrc;
521 const int *bus_range;
522 u8 hdr_type, progif;
523 u32 class_code;
524 struct device_node *dev;
525 struct ccsr_pci __iomem *pci;
526 u16 temp;
527 u32 svr = mfspr(SPRN_SVR);
528
529 dev = pdev->dev.of_node;
530
531 if (!of_device_is_available(dev)) {
532 pr_warn("%pOF: disabled\n", dev);
533 return -ENODEV;
534 }
535
536 pr_debug("Adding PCI host bridge %pOF\n", dev);
537
538 /* Fetch host bridge registers address */
539 if (of_address_to_resource(dev, 0, &rsrc)) {
540 printk(KERN_WARNING "Can't get pci register base!");
541 return -ENOMEM;
542 }
543
544 /* Get bus range if any */
545 bus_range = of_get_property(dev, "bus-range", &len);
546 if (bus_range == NULL || len < 2 * sizeof(int))
547 printk(KERN_WARNING "Can't get bus-range for %pOF, assume"
548 " bus 0\n", dev);
549
550 pci_add_flags(PCI_REASSIGN_ALL_BUS);
551 hose = pcibios_alloc_controller(dev);
552 if (!hose)
553 return -ENOMEM;
554
555 /* set platform device as the parent */
556 hose->parent = &pdev->dev;
557 hose->first_busno = bus_range ? bus_range[0] : 0x0;
558 hose->last_busno = bus_range ? bus_range[1] : 0xff;
559
560 pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
561 (u64)rsrc.start, (u64)resource_size(&rsrc));
562
563 pci = hose->private_data = ioremap(rsrc.start, resource_size(&rsrc));
564 if (!hose->private_data)
565 goto no_bridge;
566
567 setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
568 PPC_INDIRECT_TYPE_BIG_ENDIAN);
569
570 if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0)
571 hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;
572
573 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
574 /* use fsl_indirect_read_config for PCIe */
575 hose->ops = &fsl_indirect_pcie_ops;
576 /* For PCIE read HEADER_TYPE to identify controller mode */
577 early_read_config_byte(hose, 0, 0, PCI_HEADER_TYPE, &hdr_type);
578 if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE)
579 goto no_bridge;
580
581 } else {
582 /* For PCI read PROG to identify controller mode */
583 early_read_config_byte(hose, 0, 0, PCI_CLASS_PROG, &progif);
584 if ((progif & 1) &&
585 !of_property_read_bool(dev, "fsl,pci-agent-force-enum"))
586 goto no_bridge;
587 }
588
589 setup_pci_cmd(hose);
590
591 /* check PCI express link status */
592 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
593 hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG |
594 PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
595 if (fsl_pcie_check_link(hose))
596 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
597 /* Fix Class Code to PCI_CLASS_BRIDGE_PCI_NORMAL for pre-3.0 controller */
598 if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0) {
599 early_read_config_dword(hose, 0, 0, PCIE_FSL_CSR_CLASSCODE, &class_code);
600 class_code &= 0xff;
601 class_code |= PCI_CLASS_BRIDGE_PCI_NORMAL << 8;
602 early_write_config_dword(hose, 0, 0, PCIE_FSL_CSR_CLASSCODE, class_code);
603 }
604 } else {
605 /*
606 * Set PBFR(PCI Bus Function Register)[10] = 1 to
607 * disable the combining of crossing cacheline
608 * boundary requests into one burst transaction.
609 * PCI-X operation is not affected.
610 * Fix erratum PCI 5 on MPC8548
611 */
612 #define PCI_BUS_FUNCTION 0x44
613 #define PCI_BUS_FUNCTION_MDS 0x400 /* Master disable streaming */
614 if (((SVR_SOC_VER(svr) == SVR_8543) ||
615 (SVR_SOC_VER(svr) == SVR_8545) ||
616 (SVR_SOC_VER(svr) == SVR_8547) ||
617 (SVR_SOC_VER(svr) == SVR_8548)) &&
618 !early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX)) {
619 early_read_config_word(hose, 0, 0,
620 PCI_BUS_FUNCTION, &temp);
621 temp |= PCI_BUS_FUNCTION_MDS;
622 early_write_config_word(hose, 0, 0,
623 PCI_BUS_FUNCTION, temp);
624 }
625 }
626
627 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
628 "Firmware bus number: %d->%d\n",
629 (unsigned long long)rsrc.start, hose->first_busno,
630 hose->last_busno);
631
632 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
633 hose, hose->cfg_addr, hose->cfg_data);
634
635 /* Interpret the "ranges" property */
636 /* This also maps the I/O region and sets isa_io/mem_base */
637 pci_process_bridge_OF_ranges(hose, dev, is_primary);
638
639 /* Setup PEX window registers */
640 setup_pci_atmu(hose);
641
642 /* Set up controller operations */
643 setup_swiotlb_ops(hose);
644
645 return 0;
646
647 no_bridge:
648 iounmap(hose->private_data);
649 /* unmap cfg_data & cfg_addr separately if not on same page */
650 if (((unsigned long)hose->cfg_data & PAGE_MASK) !=
651 ((unsigned long)hose->cfg_addr & PAGE_MASK))
652 iounmap(hose->cfg_data);
653 iounmap(hose->cfg_addr);
654 pcibios_free_controller(hose);
655 return -ENODEV;
656 }
657 #endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */
658
659 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID,
660 quirk_fsl_pcie_early);
661
662 #if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x)
663 struct mpc83xx_pcie_priv {
664 void __iomem *cfg_type0;
665 void __iomem *cfg_type1;
666 u32 dev_base;
667 };
668
669 struct pex_inbound_window {
670 u32 ar;
671 u32 tar;
672 u32 barl;
673 u32 barh;
674 };
675
676 /*
677 * With the convention of u-boot, the PCIE outbound window 0 serves
678 * as configuration transactions outbound.
679 */
680 #define PEX_OUTWIN0_BAR 0xCA4
681 #define PEX_OUTWIN0_TAL 0xCA8
682 #define PEX_OUTWIN0_TAH 0xCAC
683 #define PEX_RC_INWIN_BASE 0xE60
684 #define PEX_RCIWARn_EN 0x1
685
mpc83xx_pcie_exclude_device(struct pci_bus * bus,unsigned int devfn)686 static int mpc83xx_pcie_exclude_device(struct pci_bus *bus, unsigned int devfn)
687 {
688 struct pci_controller *hose = pci_bus_to_host(bus);
689
690 if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK)
691 return PCIBIOS_DEVICE_NOT_FOUND;
692 /*
693 * Workaround for the HW bug: for Type 0 configure transactions the
694 * PCI-E controller does not check the device number bits and just
695 * assumes that the device number bits are 0.
696 */
697 if (bus->number == hose->first_busno ||
698 bus->primary == hose->first_busno) {
699 if (devfn & 0xf8)
700 return PCIBIOS_DEVICE_NOT_FOUND;
701 }
702
703 if (ppc_md.pci_exclude_device) {
704 if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
705 return PCIBIOS_DEVICE_NOT_FOUND;
706 }
707
708 return PCIBIOS_SUCCESSFUL;
709 }
710
mpc83xx_pcie_remap_cfg(struct pci_bus * bus,unsigned int devfn,int offset)711 static void __iomem *mpc83xx_pcie_remap_cfg(struct pci_bus *bus,
712 unsigned int devfn, int offset)
713 {
714 struct pci_controller *hose = pci_bus_to_host(bus);
715 struct mpc83xx_pcie_priv *pcie = hose->dn->data;
716 u32 dev_base = bus->number << 24 | devfn << 16;
717 int ret;
718
719 ret = mpc83xx_pcie_exclude_device(bus, devfn);
720 if (ret)
721 return NULL;
722
723 offset &= 0xfff;
724
725 /* Type 0 */
726 if (bus->number == hose->first_busno)
727 return pcie->cfg_type0 + offset;
728
729 if (pcie->dev_base == dev_base)
730 goto mapped;
731
732 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, dev_base);
733
734 pcie->dev_base = dev_base;
735 mapped:
736 return pcie->cfg_type1 + offset;
737 }
738
mpc83xx_pcie_write_config(struct pci_bus * bus,unsigned int devfn,int offset,int len,u32 val)739 static int mpc83xx_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
740 int offset, int len, u32 val)
741 {
742 struct pci_controller *hose = pci_bus_to_host(bus);
743
744 /* PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS */
745 if (offset == PCI_PRIMARY_BUS && bus->number == hose->first_busno)
746 val &= 0xffffff00;
747
748 return pci_generic_config_write(bus, devfn, offset, len, val);
749 }
750
751 static struct pci_ops mpc83xx_pcie_ops = {
752 .map_bus = mpc83xx_pcie_remap_cfg,
753 .read = pci_generic_config_read,
754 .write = mpc83xx_pcie_write_config,
755 };
756
mpc83xx_pcie_setup(struct pci_controller * hose,struct resource * reg)757 static int __init mpc83xx_pcie_setup(struct pci_controller *hose,
758 struct resource *reg)
759 {
760 struct mpc83xx_pcie_priv *pcie;
761 u32 cfg_bar;
762 int ret = -ENOMEM;
763
764 pcie = zalloc_maybe_bootmem(sizeof(*pcie), GFP_KERNEL);
765 if (!pcie)
766 return ret;
767
768 pcie->cfg_type0 = ioremap(reg->start, resource_size(reg));
769 if (!pcie->cfg_type0)
770 goto err0;
771
772 cfg_bar = in_le32(pcie->cfg_type0 + PEX_OUTWIN0_BAR);
773 if (!cfg_bar) {
774 /* PCI-E isn't configured. */
775 ret = -ENODEV;
776 goto err1;
777 }
778
779 pcie->cfg_type1 = ioremap(cfg_bar, 0x1000);
780 if (!pcie->cfg_type1)
781 goto err1;
782
783 WARN_ON(hose->dn->data);
784 hose->dn->data = pcie;
785 hose->ops = &mpc83xx_pcie_ops;
786 hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;
787
788 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0);
789 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0);
790
791 if (fsl_pcie_check_link(hose))
792 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
793
794 return 0;
795 err1:
796 iounmap(pcie->cfg_type0);
797 err0:
798 kfree(pcie);
799 return ret;
800
801 }
802
mpc83xx_add_bridge(struct device_node * dev)803 int __init mpc83xx_add_bridge(struct device_node *dev)
804 {
805 int ret;
806 int len;
807 struct pci_controller *hose;
808 struct resource rsrc_reg;
809 struct resource rsrc_cfg;
810 const int *bus_range;
811 int primary;
812
813 is_mpc83xx_pci = 1;
814
815 if (!of_device_is_available(dev)) {
816 pr_warn("%pOF: disabled by the firmware.\n",
817 dev);
818 return -ENODEV;
819 }
820 pr_debug("Adding PCI host bridge %pOF\n", dev);
821
822 /* Fetch host bridge registers address */
823 if (of_address_to_resource(dev, 0, &rsrc_reg)) {
824 printk(KERN_WARNING "Can't get pci register base!\n");
825 return -ENOMEM;
826 }
827
828 memset(&rsrc_cfg, 0, sizeof(rsrc_cfg));
829
830 if (of_address_to_resource(dev, 1, &rsrc_cfg)) {
831 printk(KERN_WARNING
832 "No pci config register base in dev tree, "
833 "using default\n");
834 /*
835 * MPC83xx supports up to two host controllers
836 * one at 0x8500 has config space registers at 0x8300
837 * one at 0x8600 has config space registers at 0x8380
838 */
839 if ((rsrc_reg.start & 0xfffff) == 0x8500)
840 rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8300;
841 else if ((rsrc_reg.start & 0xfffff) == 0x8600)
842 rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8380;
843 }
844 /*
845 * Controller at offset 0x8500 is primary
846 */
847 if ((rsrc_reg.start & 0xfffff) == 0x8500)
848 primary = 1;
849 else
850 primary = 0;
851
852 /* Get bus range if any */
853 bus_range = of_get_property(dev, "bus-range", &len);
854 if (bus_range == NULL || len < 2 * sizeof(int)) {
855 printk(KERN_WARNING "Can't get bus-range for %pOF, assume"
856 " bus 0\n", dev);
857 }
858
859 pci_add_flags(PCI_REASSIGN_ALL_BUS);
860 hose = pcibios_alloc_controller(dev);
861 if (!hose)
862 return -ENOMEM;
863
864 hose->first_busno = bus_range ? bus_range[0] : 0;
865 hose->last_busno = bus_range ? bus_range[1] : 0xff;
866
867 if (of_device_is_compatible(dev, "fsl,mpc8314-pcie")) {
868 ret = mpc83xx_pcie_setup(hose, &rsrc_reg);
869 if (ret)
870 goto err0;
871 } else {
872 setup_indirect_pci(hose, rsrc_cfg.start,
873 rsrc_cfg.start + 4, 0);
874 }
875
876 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
877 "Firmware bus number: %d->%d\n",
878 (unsigned long long)rsrc_reg.start, hose->first_busno,
879 hose->last_busno);
880
881 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
882 hose, hose->cfg_addr, hose->cfg_data);
883
884 /* Interpret the "ranges" property */
885 /* This also maps the I/O region and sets isa_io/mem_base */
886 pci_process_bridge_OF_ranges(hose, dev, primary);
887
888 return 0;
889 err0:
890 pcibios_free_controller(hose);
891 return ret;
892 }
893 #endif /* CONFIG_PPC_83xx */
894
fsl_pci_immrbar_base(struct pci_controller * hose)895 u64 fsl_pci_immrbar_base(struct pci_controller *hose)
896 {
897 #ifdef CONFIG_PPC_83xx
898 if (is_mpc83xx_pci) {
899 struct mpc83xx_pcie_priv *pcie = hose->dn->data;
900 struct pex_inbound_window *in;
901 int i;
902
903 /* Walk the Root Complex Inbound windows to match IMMR base */
904 in = pcie->cfg_type0 + PEX_RC_INWIN_BASE;
905 for (i = 0; i < 4; i++) {
906 /* not enabled, skip */
907 if (!(in_le32(&in[i].ar) & PEX_RCIWARn_EN))
908 continue;
909
910 if (get_immrbase() == in_le32(&in[i].tar))
911 return (u64)in_le32(&in[i].barh) << 32 |
912 in_le32(&in[i].barl);
913 }
914
915 printk(KERN_WARNING "could not find PCI BAR matching IMMR\n");
916 }
917 #endif
918
919 #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
920 if (!is_mpc83xx_pci) {
921 u32 base;
922
923 pci_bus_read_config_dword(hose->bus,
924 PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base);
925
926 /*
927 * For PEXCSRBAR, bit 3-0 indicate prefetchable and
928 * address type. So when getting base address, these
929 * bits should be masked
930 */
931 base &= PCI_BASE_ADDRESS_MEM_MASK;
932
933 return base;
934 }
935 #endif
936
937 return 0;
938 }
939
940 #ifdef CONFIG_E500
mcheck_handle_load(struct pt_regs * regs,u32 inst)941 static int mcheck_handle_load(struct pt_regs *regs, u32 inst)
942 {
943 unsigned int rd, ra, rb, d;
944
945 rd = get_rt(inst);
946 ra = get_ra(inst);
947 rb = get_rb(inst);
948 d = get_d(inst);
949
950 switch (get_op(inst)) {
951 case 31:
952 switch (get_xop(inst)) {
953 case OP_31_XOP_LWZX:
954 case OP_31_XOP_LWBRX:
955 regs->gpr[rd] = 0xffffffff;
956 break;
957
958 case OP_31_XOP_LWZUX:
959 regs->gpr[rd] = 0xffffffff;
960 regs->gpr[ra] += regs->gpr[rb];
961 break;
962
963 case OP_31_XOP_LBZX:
964 regs->gpr[rd] = 0xff;
965 break;
966
967 case OP_31_XOP_LBZUX:
968 regs->gpr[rd] = 0xff;
969 regs->gpr[ra] += regs->gpr[rb];
970 break;
971
972 case OP_31_XOP_LHZX:
973 case OP_31_XOP_LHBRX:
974 regs->gpr[rd] = 0xffff;
975 break;
976
977 case OP_31_XOP_LHZUX:
978 regs->gpr[rd] = 0xffff;
979 regs->gpr[ra] += regs->gpr[rb];
980 break;
981
982 case OP_31_XOP_LHAX:
983 regs->gpr[rd] = ~0UL;
984 break;
985
986 case OP_31_XOP_LHAUX:
987 regs->gpr[rd] = ~0UL;
988 regs->gpr[ra] += regs->gpr[rb];
989 break;
990
991 default:
992 return 0;
993 }
994 break;
995
996 case OP_LWZ:
997 regs->gpr[rd] = 0xffffffff;
998 break;
999
1000 case OP_LWZU:
1001 regs->gpr[rd] = 0xffffffff;
1002 regs->gpr[ra] += (s16)d;
1003 break;
1004
1005 case OP_LBZ:
1006 regs->gpr[rd] = 0xff;
1007 break;
1008
1009 case OP_LBZU:
1010 regs->gpr[rd] = 0xff;
1011 regs->gpr[ra] += (s16)d;
1012 break;
1013
1014 case OP_LHZ:
1015 regs->gpr[rd] = 0xffff;
1016 break;
1017
1018 case OP_LHZU:
1019 regs->gpr[rd] = 0xffff;
1020 regs->gpr[ra] += (s16)d;
1021 break;
1022
1023 case OP_LHA:
1024 regs->gpr[rd] = ~0UL;
1025 break;
1026
1027 case OP_LHAU:
1028 regs->gpr[rd] = ~0UL;
1029 regs->gpr[ra] += (s16)d;
1030 break;
1031
1032 default:
1033 return 0;
1034 }
1035
1036 return 1;
1037 }
1038
is_in_pci_mem_space(phys_addr_t addr)1039 static int is_in_pci_mem_space(phys_addr_t addr)
1040 {
1041 struct pci_controller *hose;
1042 struct resource *res;
1043 int i;
1044
1045 list_for_each_entry(hose, &hose_list, list_node) {
1046 if (!(hose->indirect_type & PPC_INDIRECT_TYPE_EXT_REG))
1047 continue;
1048
1049 for (i = 0; i < 3; i++) {
1050 res = &hose->mem_resources[i];
1051 if ((res->flags & IORESOURCE_MEM) &&
1052 addr >= res->start && addr <= res->end)
1053 return 1;
1054 }
1055 }
1056 return 0;
1057 }
1058
fsl_pci_mcheck_exception(struct pt_regs * regs)1059 int fsl_pci_mcheck_exception(struct pt_regs *regs)
1060 {
1061 u32 inst;
1062 int ret;
1063 phys_addr_t addr = 0;
1064
1065 /* Let KVM/QEMU deal with the exception */
1066 if (regs->msr & MSR_GS)
1067 return 0;
1068
1069 #ifdef CONFIG_PHYS_64BIT
1070 addr = mfspr(SPRN_MCARU);
1071 addr <<= 32;
1072 #endif
1073 addr += mfspr(SPRN_MCAR);
1074
1075 if (is_in_pci_mem_space(addr)) {
1076 if (user_mode(regs)) {
1077 pagefault_disable();
1078 ret = get_user(inst, (__u32 __user *)regs->nip);
1079 pagefault_enable();
1080 } else {
1081 ret = probe_kernel_address((void *)regs->nip, inst);
1082 }
1083
1084 if (!ret && mcheck_handle_load(regs, inst)) {
1085 regs->nip += 4;
1086 return 1;
1087 }
1088 }
1089
1090 return 0;
1091 }
1092 #endif
1093
1094 #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
1095 static const struct of_device_id pci_ids[] = {
1096 { .compatible = "fsl,mpc8540-pci", },
1097 { .compatible = "fsl,mpc8548-pcie", },
1098 { .compatible = "fsl,mpc8610-pci", },
1099 { .compatible = "fsl,mpc8641-pcie", },
1100 { .compatible = "fsl,qoriq-pcie", },
1101 { .compatible = "fsl,qoriq-pcie-v2.1", },
1102 { .compatible = "fsl,qoriq-pcie-v2.2", },
1103 { .compatible = "fsl,qoriq-pcie-v2.3", },
1104 { .compatible = "fsl,qoriq-pcie-v2.4", },
1105 { .compatible = "fsl,qoriq-pcie-v3.0", },
1106
1107 /*
1108 * The following entries are for compatibility with older device
1109 * trees.
1110 */
1111 { .compatible = "fsl,p1022-pcie", },
1112 { .compatible = "fsl,p4080-pcie", },
1113
1114 {},
1115 };
1116
1117 struct device_node *fsl_pci_primary;
1118
fsl_pci_assign_primary(void)1119 void fsl_pci_assign_primary(void)
1120 {
1121 struct device_node *np;
1122
1123 /* Callers can specify the primary bus using other means. */
1124 if (fsl_pci_primary)
1125 return;
1126
1127 /* If a PCI host bridge contains an ISA node, it's primary. */
1128 np = of_find_node_by_type(NULL, "isa");
1129 while ((fsl_pci_primary = of_get_parent(np))) {
1130 of_node_put(np);
1131 np = fsl_pci_primary;
1132
1133 if (of_match_node(pci_ids, np) && of_device_is_available(np))
1134 return;
1135 }
1136
1137 /*
1138 * If there's no PCI host bridge with ISA, arbitrarily
1139 * designate one as primary. This can go away once
1140 * various bugs with primary-less systems are fixed.
1141 */
1142 for_each_matching_node(np, pci_ids) {
1143 if (of_device_is_available(np)) {
1144 fsl_pci_primary = np;
1145 of_node_put(np);
1146 return;
1147 }
1148 }
1149 }
1150
1151 #ifdef CONFIG_PM_SLEEP
fsl_pci_pme_handle(int irq,void * dev_id)1152 static irqreturn_t fsl_pci_pme_handle(int irq, void *dev_id)
1153 {
1154 struct pci_controller *hose = dev_id;
1155 struct ccsr_pci __iomem *pci = hose->private_data;
1156 u32 dr;
1157
1158 dr = in_be32(&pci->pex_pme_mes_dr);
1159 if (!dr)
1160 return IRQ_NONE;
1161
1162 out_be32(&pci->pex_pme_mes_dr, dr);
1163
1164 return IRQ_HANDLED;
1165 }
1166
fsl_pci_pme_probe(struct pci_controller * hose)1167 static int fsl_pci_pme_probe(struct pci_controller *hose)
1168 {
1169 struct ccsr_pci __iomem *pci;
1170 struct pci_dev *dev;
1171 int pme_irq;
1172 int res;
1173 u16 pms;
1174
1175 /* Get hose's pci_dev */
1176 dev = list_first_entry(&hose->bus->devices, typeof(*dev), bus_list);
1177
1178 /* PME Disable */
1179 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pms);
1180 pms &= ~PCI_PM_CTRL_PME_ENABLE;
1181 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pms);
1182
1183 pme_irq = irq_of_parse_and_map(hose->dn, 0);
1184 if (!pme_irq) {
1185 dev_err(&dev->dev, "Failed to map PME interrupt.\n");
1186
1187 return -ENXIO;
1188 }
1189
1190 res = devm_request_irq(hose->parent, pme_irq,
1191 fsl_pci_pme_handle,
1192 IRQF_SHARED,
1193 "[PCI] PME", hose);
1194 if (res < 0) {
1195 dev_err(&dev->dev, "Unable to request irq %d for PME\n", pme_irq);
1196 irq_dispose_mapping(pme_irq);
1197
1198 return -ENODEV;
1199 }
1200
1201 pci = hose->private_data;
1202
1203 /* Enable PTOD, ENL23D & EXL23D */
1204 clrbits32(&pci->pex_pme_mes_disr,
1205 PME_DISR_EN_PTOD | PME_DISR_EN_ENL23D | PME_DISR_EN_EXL23D);
1206
1207 out_be32(&pci->pex_pme_mes_ier, 0);
1208 setbits32(&pci->pex_pme_mes_ier,
1209 PME_DISR_EN_PTOD | PME_DISR_EN_ENL23D | PME_DISR_EN_EXL23D);
1210
1211 /* PME Enable */
1212 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pms);
1213 pms |= PCI_PM_CTRL_PME_ENABLE;
1214 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pms);
1215
1216 return 0;
1217 }
1218
send_pme_turnoff_message(struct pci_controller * hose)1219 static void send_pme_turnoff_message(struct pci_controller *hose)
1220 {
1221 struct ccsr_pci __iomem *pci = hose->private_data;
1222 u32 dr;
1223 int i;
1224
1225 /* Send PME_Turn_Off Message Request */
1226 setbits32(&pci->pex_pmcr, PEX_PMCR_PTOMR);
1227
1228 /* Wait trun off done */
1229 for (i = 0; i < 150; i++) {
1230 dr = in_be32(&pci->pex_pme_mes_dr);
1231 if (dr) {
1232 out_be32(&pci->pex_pme_mes_dr, dr);
1233 break;
1234 }
1235
1236 udelay(1000);
1237 }
1238 }
1239
fsl_pci_syscore_do_suspend(struct pci_controller * hose)1240 static void fsl_pci_syscore_do_suspend(struct pci_controller *hose)
1241 {
1242 send_pme_turnoff_message(hose);
1243 }
1244
fsl_pci_syscore_suspend(void)1245 static int fsl_pci_syscore_suspend(void)
1246 {
1247 struct pci_controller *hose, *tmp;
1248
1249 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1250 fsl_pci_syscore_do_suspend(hose);
1251
1252 return 0;
1253 }
1254
fsl_pci_syscore_do_resume(struct pci_controller * hose)1255 static void fsl_pci_syscore_do_resume(struct pci_controller *hose)
1256 {
1257 struct ccsr_pci __iomem *pci = hose->private_data;
1258 u32 dr;
1259 int i;
1260
1261 /* Send Exit L2 State Message */
1262 setbits32(&pci->pex_pmcr, PEX_PMCR_EXL2S);
1263
1264 /* Wait exit done */
1265 for (i = 0; i < 150; i++) {
1266 dr = in_be32(&pci->pex_pme_mes_dr);
1267 if (dr) {
1268 out_be32(&pci->pex_pme_mes_dr, dr);
1269 break;
1270 }
1271
1272 udelay(1000);
1273 }
1274
1275 setup_pci_atmu(hose);
1276 }
1277
fsl_pci_syscore_resume(void)1278 static void fsl_pci_syscore_resume(void)
1279 {
1280 struct pci_controller *hose, *tmp;
1281
1282 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1283 fsl_pci_syscore_do_resume(hose);
1284 }
1285
1286 static struct syscore_ops pci_syscore_pm_ops = {
1287 .suspend = fsl_pci_syscore_suspend,
1288 .resume = fsl_pci_syscore_resume,
1289 };
1290 #endif
1291
fsl_pcibios_fixup_phb(struct pci_controller * phb)1292 void fsl_pcibios_fixup_phb(struct pci_controller *phb)
1293 {
1294 #ifdef CONFIG_PM_SLEEP
1295 fsl_pci_pme_probe(phb);
1296 #endif
1297 }
1298
add_err_dev(struct platform_device * pdev)1299 static int add_err_dev(struct platform_device *pdev)
1300 {
1301 struct platform_device *errdev;
1302 struct mpc85xx_edac_pci_plat_data pd = {
1303 .of_node = pdev->dev.of_node
1304 };
1305
1306 errdev = platform_device_register_resndata(&pdev->dev,
1307 "mpc85xx-pci-edac",
1308 PLATFORM_DEVID_AUTO,
1309 pdev->resource,
1310 pdev->num_resources,
1311 &pd, sizeof(pd));
1312
1313 return PTR_ERR_OR_ZERO(errdev);
1314 }
1315
fsl_pci_probe(struct platform_device * pdev)1316 static int fsl_pci_probe(struct platform_device *pdev)
1317 {
1318 struct device_node *node;
1319 int ret;
1320
1321 node = pdev->dev.of_node;
1322 ret = fsl_add_bridge(pdev, fsl_pci_primary == node);
1323 if (ret)
1324 return ret;
1325
1326 ret = add_err_dev(pdev);
1327 if (ret)
1328 dev_err(&pdev->dev, "couldn't register error device: %d\n",
1329 ret);
1330
1331 return 0;
1332 }
1333
1334 static struct platform_driver fsl_pci_driver = {
1335 .driver = {
1336 .name = "fsl-pci",
1337 .of_match_table = pci_ids,
1338 },
1339 .probe = fsl_pci_probe,
1340 };
1341
fsl_pci_init(void)1342 static int __init fsl_pci_init(void)
1343 {
1344 #ifdef CONFIG_PM_SLEEP
1345 register_syscore_ops(&pci_syscore_pm_ops);
1346 #endif
1347 return platform_driver_register(&fsl_pci_driver);
1348 }
1349 arch_initcall(fsl_pci_init);
1350 #endif
1351