1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * PowerPC64 port by Mike Corrigan and Dave Engebretsen
4 * {mikejc|engebret}@us.ibm.com
5 *
6 * Copyright (c) 2000 Mike Corrigan <mikejc@us.ibm.com>
7 *
8 * SMP scalability work:
9 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
10 *
11 * Module name: htab.c
12 *
13 * Description:
14 * PowerPC Hashed Page Table functions
15 */
16
17 #undef DEBUG
18 #undef DEBUG_LOW
19
20 #define pr_fmt(fmt) "hash-mmu: " fmt
21 #include <linux/spinlock.h>
22 #include <linux/errno.h>
23 #include <linux/sched/mm.h>
24 #include <linux/proc_fs.h>
25 #include <linux/stat.h>
26 #include <linux/sysctl.h>
27 #include <linux/export.h>
28 #include <linux/ctype.h>
29 #include <linux/cache.h>
30 #include <linux/init.h>
31 #include <linux/signal.h>
32 #include <linux/memblock.h>
33 #include <linux/context_tracking.h>
34 #include <linux/libfdt.h>
35 #include <linux/pkeys.h>
36 #include <linux/hugetlb.h>
37 #include <linux/cpu.h>
38
39 #include <asm/debugfs.h>
40 #include <asm/processor.h>
41 #include <asm/pgtable.h>
42 #include <asm/mmu.h>
43 #include <asm/mmu_context.h>
44 #include <asm/page.h>
45 #include <asm/types.h>
46 #include <linux/uaccess.h>
47 #include <asm/machdep.h>
48 #include <asm/prom.h>
49 #include <asm/io.h>
50 #include <asm/eeh.h>
51 #include <asm/tlb.h>
52 #include <asm/cacheflush.h>
53 #include <asm/cputable.h>
54 #include <asm/sections.h>
55 #include <asm/copro.h>
56 #include <asm/udbg.h>
57 #include <asm/code-patching.h>
58 #include <asm/fadump.h>
59 #include <asm/firmware.h>
60 #include <asm/tm.h>
61 #include <asm/trace.h>
62 #include <asm/ps3.h>
63 #include <asm/pte-walk.h>
64 #include <asm/asm-prototypes.h>
65 #include <asm/ultravisor.h>
66
67 #include <mm/mmu_decl.h>
68
69 #ifdef DEBUG
70 #define DBG(fmt...) udbg_printf(fmt)
71 #else
72 #define DBG(fmt...)
73 #endif
74
75 #ifdef DEBUG_LOW
76 #define DBG_LOW(fmt...) udbg_printf(fmt)
77 #else
78 #define DBG_LOW(fmt...)
79 #endif
80
81 #define KB (1024)
82 #define MB (1024*KB)
83 #define GB (1024L*MB)
84
85 /*
86 * Note: pte --> Linux PTE
87 * HPTE --> PowerPC Hashed Page Table Entry
88 *
89 * Execution context:
90 * htab_initialize is called with the MMU off (of course), but
91 * the kernel has been copied down to zero so it can directly
92 * reference global data. At this point it is very difficult
93 * to print debug info.
94 *
95 */
96
97 static unsigned long _SDR1;
98 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
99 EXPORT_SYMBOL_GPL(mmu_psize_defs);
100
101 u8 hpte_page_sizes[1 << LP_BITS];
102 EXPORT_SYMBOL_GPL(hpte_page_sizes);
103
104 struct hash_pte *htab_address;
105 unsigned long htab_size_bytes;
106 unsigned long htab_hash_mask;
107 EXPORT_SYMBOL_GPL(htab_hash_mask);
108 int mmu_linear_psize = MMU_PAGE_4K;
109 EXPORT_SYMBOL_GPL(mmu_linear_psize);
110 int mmu_virtual_psize = MMU_PAGE_4K;
111 int mmu_vmalloc_psize = MMU_PAGE_4K;
112 #ifdef CONFIG_SPARSEMEM_VMEMMAP
113 int mmu_vmemmap_psize = MMU_PAGE_4K;
114 #endif
115 int mmu_io_psize = MMU_PAGE_4K;
116 int mmu_kernel_ssize = MMU_SEGSIZE_256M;
117 EXPORT_SYMBOL_GPL(mmu_kernel_ssize);
118 int mmu_highuser_ssize = MMU_SEGSIZE_256M;
119 u16 mmu_slb_size = 64;
120 EXPORT_SYMBOL_GPL(mmu_slb_size);
121 #ifdef CONFIG_PPC_64K_PAGES
122 int mmu_ci_restrictions;
123 #endif
124 #ifdef CONFIG_DEBUG_PAGEALLOC
125 static u8 *linear_map_hash_slots;
126 static unsigned long linear_map_hash_count;
127 static DEFINE_SPINLOCK(linear_map_hash_lock);
128 #endif /* CONFIG_DEBUG_PAGEALLOC */
129 struct mmu_hash_ops mmu_hash_ops;
130 EXPORT_SYMBOL(mmu_hash_ops);
131
132 /*
133 * These are definitions of page sizes arrays to be used when none
134 * is provided by the firmware.
135 */
136
137 /*
138 * Fallback (4k pages only)
139 */
140 static struct mmu_psize_def mmu_psize_defaults[] = {
141 [MMU_PAGE_4K] = {
142 .shift = 12,
143 .sllp = 0,
144 .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1},
145 .avpnm = 0,
146 .tlbiel = 0,
147 },
148 };
149
150 /*
151 * POWER4, GPUL, POWER5
152 *
153 * Support for 16Mb large pages
154 */
155 static struct mmu_psize_def mmu_psize_defaults_gp[] = {
156 [MMU_PAGE_4K] = {
157 .shift = 12,
158 .sllp = 0,
159 .penc = {[MMU_PAGE_4K] = 0, [1 ... MMU_PAGE_COUNT - 1] = -1},
160 .avpnm = 0,
161 .tlbiel = 1,
162 },
163 [MMU_PAGE_16M] = {
164 .shift = 24,
165 .sllp = SLB_VSID_L,
166 .penc = {[0 ... MMU_PAGE_16M - 1] = -1, [MMU_PAGE_16M] = 0,
167 [MMU_PAGE_16M + 1 ... MMU_PAGE_COUNT - 1] = -1 },
168 .avpnm = 0x1UL,
169 .tlbiel = 0,
170 },
171 };
172
173 /*
174 * 'R' and 'C' update notes:
175 * - Under pHyp or KVM, the updatepp path will not set C, thus it *will*
176 * create writeable HPTEs without C set, because the hcall H_PROTECT
177 * that we use in that case will not update C
178 * - The above is however not a problem, because we also don't do that
179 * fancy "no flush" variant of eviction and we use H_REMOVE which will
180 * do the right thing and thus we don't have the race I described earlier
181 *
182 * - Under bare metal, we do have the race, so we need R and C set
183 * - We make sure R is always set and never lost
184 * - C is _PAGE_DIRTY, and *should* always be set for a writeable mapping
185 */
htab_convert_pte_flags(unsigned long pteflags)186 unsigned long htab_convert_pte_flags(unsigned long pteflags)
187 {
188 unsigned long rflags = 0;
189
190 /* _PAGE_EXEC -> NOEXEC */
191 if ((pteflags & _PAGE_EXEC) == 0)
192 rflags |= HPTE_R_N;
193 /*
194 * PPP bits:
195 * Linux uses slb key 0 for kernel and 1 for user.
196 * kernel RW areas are mapped with PPP=0b000
197 * User area is mapped with PPP=0b010 for read/write
198 * or PPP=0b011 for read-only (including writeable but clean pages).
199 */
200 if (pteflags & _PAGE_PRIVILEGED) {
201 /*
202 * Kernel read only mapped with ppp bits 0b110
203 */
204 if (!(pteflags & _PAGE_WRITE)) {
205 if (mmu_has_feature(MMU_FTR_KERNEL_RO))
206 rflags |= (HPTE_R_PP0 | 0x2);
207 else
208 rflags |= 0x3;
209 }
210 } else {
211 if (pteflags & _PAGE_RWX)
212 rflags |= 0x2;
213 if (!((pteflags & _PAGE_WRITE) && (pteflags & _PAGE_DIRTY)))
214 rflags |= 0x1;
215 }
216 /*
217 * We can't allow hardware to update hpte bits. Hence always
218 * set 'R' bit and set 'C' if it is a write fault
219 */
220 rflags |= HPTE_R_R;
221
222 if (pteflags & _PAGE_DIRTY)
223 rflags |= HPTE_R_C;
224 /*
225 * Add in WIG bits
226 */
227
228 if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_TOLERANT)
229 rflags |= HPTE_R_I;
230 else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT)
231 rflags |= (HPTE_R_I | HPTE_R_G);
232 else if ((pteflags & _PAGE_CACHE_CTL) == _PAGE_SAO)
233 rflags |= (HPTE_R_W | HPTE_R_I | HPTE_R_M);
234 else
235 /*
236 * Add memory coherence if cache inhibited is not set
237 */
238 rflags |= HPTE_R_M;
239
240 rflags |= pte_to_hpte_pkey_bits(pteflags);
241 return rflags;
242 }
243
htab_bolt_mapping(unsigned long vstart,unsigned long vend,unsigned long pstart,unsigned long prot,int psize,int ssize)244 int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
245 unsigned long pstart, unsigned long prot,
246 int psize, int ssize)
247 {
248 unsigned long vaddr, paddr;
249 unsigned int step, shift;
250 int ret = 0;
251
252 shift = mmu_psize_defs[psize].shift;
253 step = 1 << shift;
254
255 prot = htab_convert_pte_flags(prot);
256
257 DBG("htab_bolt_mapping(%lx..%lx -> %lx (%lx,%d,%d)\n",
258 vstart, vend, pstart, prot, psize, ssize);
259
260 for (vaddr = vstart, paddr = pstart; vaddr < vend;
261 vaddr += step, paddr += step) {
262 unsigned long hash, hpteg;
263 unsigned long vsid = get_kernel_vsid(vaddr, ssize);
264 unsigned long vpn = hpt_vpn(vaddr, vsid, ssize);
265 unsigned long tprot = prot;
266
267 /*
268 * If we hit a bad address return error.
269 */
270 if (!vsid)
271 return -1;
272 /* Make kernel text executable */
273 if (overlaps_kernel_text(vaddr, vaddr + step))
274 tprot &= ~HPTE_R_N;
275
276 /*
277 * If relocatable, check if it overlaps interrupt vectors that
278 * are copied down to real 0. For relocatable kernel
279 * (e.g. kdump case) we copy interrupt vectors down to real
280 * address 0. Mark that region as executable. This is
281 * because on p8 system with relocation on exception feature
282 * enabled, exceptions are raised with MMU (IR=DR=1) ON. Hence
283 * in order to execute the interrupt handlers in virtual
284 * mode the vector region need to be marked as executable.
285 */
286 if ((PHYSICAL_START > MEMORY_START) &&
287 overlaps_interrupt_vector_text(vaddr, vaddr + step))
288 tprot &= ~HPTE_R_N;
289
290 hash = hpt_hash(vpn, shift, ssize);
291 hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
292
293 BUG_ON(!mmu_hash_ops.hpte_insert);
294 ret = mmu_hash_ops.hpte_insert(hpteg, vpn, paddr, tprot,
295 HPTE_V_BOLTED, psize, psize,
296 ssize);
297 if (ret == -1) {
298 /* Try to remove a non bolted entry */
299 ret = mmu_hash_ops.hpte_remove(hpteg);
300 if (ret != -1)
301 ret = mmu_hash_ops.hpte_insert(hpteg, vpn, paddr, tprot,
302 HPTE_V_BOLTED, psize, psize,
303 ssize);
304 }
305 if (ret < 0)
306 break;
307
308 cond_resched();
309 #ifdef CONFIG_DEBUG_PAGEALLOC
310 if (debug_pagealloc_enabled() &&
311 (paddr >> PAGE_SHIFT) < linear_map_hash_count)
312 linear_map_hash_slots[paddr >> PAGE_SHIFT] = ret | 0x80;
313 #endif /* CONFIG_DEBUG_PAGEALLOC */
314 }
315 return ret < 0 ? ret : 0;
316 }
317
htab_remove_mapping(unsigned long vstart,unsigned long vend,int psize,int ssize)318 int htab_remove_mapping(unsigned long vstart, unsigned long vend,
319 int psize, int ssize)
320 {
321 unsigned long vaddr;
322 unsigned int step, shift;
323 int rc;
324 int ret = 0;
325
326 shift = mmu_psize_defs[psize].shift;
327 step = 1 << shift;
328
329 if (!mmu_hash_ops.hpte_removebolted)
330 return -ENODEV;
331
332 for (vaddr = vstart; vaddr < vend; vaddr += step) {
333 rc = mmu_hash_ops.hpte_removebolted(vaddr, psize, ssize);
334 if (rc == -ENOENT) {
335 ret = -ENOENT;
336 continue;
337 }
338 if (rc < 0)
339 return rc;
340 }
341
342 return ret;
343 }
344
345 static bool disable_1tb_segments = false;
346
parse_disable_1tb_segments(char * p)347 static int __init parse_disable_1tb_segments(char *p)
348 {
349 disable_1tb_segments = true;
350 return 0;
351 }
352 early_param("disable_1tb_segments", parse_disable_1tb_segments);
353
htab_dt_scan_seg_sizes(unsigned long node,const char * uname,int depth,void * data)354 static int __init htab_dt_scan_seg_sizes(unsigned long node,
355 const char *uname, int depth,
356 void *data)
357 {
358 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
359 const __be32 *prop;
360 int size = 0;
361
362 /* We are scanning "cpu" nodes only */
363 if (type == NULL || strcmp(type, "cpu") != 0)
364 return 0;
365
366 prop = of_get_flat_dt_prop(node, "ibm,processor-segment-sizes", &size);
367 if (prop == NULL)
368 return 0;
369 for (; size >= 4; size -= 4, ++prop) {
370 if (be32_to_cpu(prop[0]) == 40) {
371 DBG("1T segment support detected\n");
372
373 if (disable_1tb_segments) {
374 DBG("1T segments disabled by command line\n");
375 break;
376 }
377
378 cur_cpu_spec->mmu_features |= MMU_FTR_1T_SEGMENT;
379 return 1;
380 }
381 }
382 cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B;
383 return 0;
384 }
385
get_idx_from_shift(unsigned int shift)386 static int __init get_idx_from_shift(unsigned int shift)
387 {
388 int idx = -1;
389
390 switch (shift) {
391 case 0xc:
392 idx = MMU_PAGE_4K;
393 break;
394 case 0x10:
395 idx = MMU_PAGE_64K;
396 break;
397 case 0x14:
398 idx = MMU_PAGE_1M;
399 break;
400 case 0x18:
401 idx = MMU_PAGE_16M;
402 break;
403 case 0x22:
404 idx = MMU_PAGE_16G;
405 break;
406 }
407 return idx;
408 }
409
htab_dt_scan_page_sizes(unsigned long node,const char * uname,int depth,void * data)410 static int __init htab_dt_scan_page_sizes(unsigned long node,
411 const char *uname, int depth,
412 void *data)
413 {
414 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
415 const __be32 *prop;
416 int size = 0;
417
418 /* We are scanning "cpu" nodes only */
419 if (type == NULL || strcmp(type, "cpu") != 0)
420 return 0;
421
422 prop = of_get_flat_dt_prop(node, "ibm,segment-page-sizes", &size);
423 if (!prop)
424 return 0;
425
426 pr_info("Page sizes from device-tree:\n");
427 size /= 4;
428 cur_cpu_spec->mmu_features &= ~(MMU_FTR_16M_PAGE);
429 while(size > 0) {
430 unsigned int base_shift = be32_to_cpu(prop[0]);
431 unsigned int slbenc = be32_to_cpu(prop[1]);
432 unsigned int lpnum = be32_to_cpu(prop[2]);
433 struct mmu_psize_def *def;
434 int idx, base_idx;
435
436 size -= 3; prop += 3;
437 base_idx = get_idx_from_shift(base_shift);
438 if (base_idx < 0) {
439 /* skip the pte encoding also */
440 prop += lpnum * 2; size -= lpnum * 2;
441 continue;
442 }
443 def = &mmu_psize_defs[base_idx];
444 if (base_idx == MMU_PAGE_16M)
445 cur_cpu_spec->mmu_features |= MMU_FTR_16M_PAGE;
446
447 def->shift = base_shift;
448 if (base_shift <= 23)
449 def->avpnm = 0;
450 else
451 def->avpnm = (1 << (base_shift - 23)) - 1;
452 def->sllp = slbenc;
453 /*
454 * We don't know for sure what's up with tlbiel, so
455 * for now we only set it for 4K and 64K pages
456 */
457 if (base_idx == MMU_PAGE_4K || base_idx == MMU_PAGE_64K)
458 def->tlbiel = 1;
459 else
460 def->tlbiel = 0;
461
462 while (size > 0 && lpnum) {
463 unsigned int shift = be32_to_cpu(prop[0]);
464 int penc = be32_to_cpu(prop[1]);
465
466 prop += 2; size -= 2;
467 lpnum--;
468
469 idx = get_idx_from_shift(shift);
470 if (idx < 0)
471 continue;
472
473 if (penc == -1)
474 pr_err("Invalid penc for base_shift=%d "
475 "shift=%d\n", base_shift, shift);
476
477 def->penc[idx] = penc;
478 pr_info("base_shift=%d: shift=%d, sllp=0x%04lx,"
479 " avpnm=0x%08lx, tlbiel=%d, penc=%d\n",
480 base_shift, shift, def->sllp,
481 def->avpnm, def->tlbiel, def->penc[idx]);
482 }
483 }
484
485 return 1;
486 }
487
488 #ifdef CONFIG_HUGETLB_PAGE
489 /*
490 * Scan for 16G memory blocks that have been set aside for huge pages
491 * and reserve those blocks for 16G huge pages.
492 */
htab_dt_scan_hugepage_blocks(unsigned long node,const char * uname,int depth,void * data)493 static int __init htab_dt_scan_hugepage_blocks(unsigned long node,
494 const char *uname, int depth,
495 void *data) {
496 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
497 const __be64 *addr_prop;
498 const __be32 *page_count_prop;
499 unsigned int expected_pages;
500 long unsigned int phys_addr;
501 long unsigned int block_size;
502
503 /* We are scanning "memory" nodes only */
504 if (type == NULL || strcmp(type, "memory") != 0)
505 return 0;
506
507 /*
508 * This property is the log base 2 of the number of virtual pages that
509 * will represent this memory block.
510 */
511 page_count_prop = of_get_flat_dt_prop(node, "ibm,expected#pages", NULL);
512 if (page_count_prop == NULL)
513 return 0;
514 expected_pages = (1 << be32_to_cpu(page_count_prop[0]));
515 addr_prop = of_get_flat_dt_prop(node, "reg", NULL);
516 if (addr_prop == NULL)
517 return 0;
518 phys_addr = be64_to_cpu(addr_prop[0]);
519 block_size = be64_to_cpu(addr_prop[1]);
520 if (block_size != (16 * GB))
521 return 0;
522 printk(KERN_INFO "Huge page(16GB) memory: "
523 "addr = 0x%lX size = 0x%lX pages = %d\n",
524 phys_addr, block_size, expected_pages);
525 if (phys_addr + block_size * expected_pages <= memblock_end_of_DRAM()) {
526 memblock_reserve(phys_addr, block_size * expected_pages);
527 pseries_add_gpage(phys_addr, block_size, expected_pages);
528 }
529 return 0;
530 }
531 #endif /* CONFIG_HUGETLB_PAGE */
532
mmu_psize_set_default_penc(void)533 static void mmu_psize_set_default_penc(void)
534 {
535 int bpsize, apsize;
536 for (bpsize = 0; bpsize < MMU_PAGE_COUNT; bpsize++)
537 for (apsize = 0; apsize < MMU_PAGE_COUNT; apsize++)
538 mmu_psize_defs[bpsize].penc[apsize] = -1;
539 }
540
541 #ifdef CONFIG_PPC_64K_PAGES
542
might_have_hea(void)543 static bool might_have_hea(void)
544 {
545 /*
546 * The HEA ethernet adapter requires awareness of the
547 * GX bus. Without that awareness we can easily assume
548 * we will never see an HEA ethernet device.
549 */
550 #ifdef CONFIG_IBMEBUS
551 return !cpu_has_feature(CPU_FTR_ARCH_207S) &&
552 firmware_has_feature(FW_FEATURE_SPLPAR);
553 #else
554 return false;
555 #endif
556 }
557
558 #endif /* #ifdef CONFIG_PPC_64K_PAGES */
559
htab_scan_page_sizes(void)560 static void __init htab_scan_page_sizes(void)
561 {
562 int rc;
563
564 /* se the invalid penc to -1 */
565 mmu_psize_set_default_penc();
566
567 /* Default to 4K pages only */
568 memcpy(mmu_psize_defs, mmu_psize_defaults,
569 sizeof(mmu_psize_defaults));
570
571 /*
572 * Try to find the available page sizes in the device-tree
573 */
574 rc = of_scan_flat_dt(htab_dt_scan_page_sizes, NULL);
575 if (rc == 0 && early_mmu_has_feature(MMU_FTR_16M_PAGE)) {
576 /*
577 * Nothing in the device-tree, but the CPU supports 16M pages,
578 * so let's fallback on a known size list for 16M capable CPUs.
579 */
580 memcpy(mmu_psize_defs, mmu_psize_defaults_gp,
581 sizeof(mmu_psize_defaults_gp));
582 }
583
584 #ifdef CONFIG_HUGETLB_PAGE
585 if (!hugetlb_disabled) {
586 /* Reserve 16G huge page memory sections for huge pages */
587 of_scan_flat_dt(htab_dt_scan_hugepage_blocks, NULL);
588 }
589 #endif /* CONFIG_HUGETLB_PAGE */
590 }
591
592 /*
593 * Fill in the hpte_page_sizes[] array.
594 * We go through the mmu_psize_defs[] array looking for all the
595 * supported base/actual page size combinations. Each combination
596 * has a unique pagesize encoding (penc) value in the low bits of
597 * the LP field of the HPTE. For actual page sizes less than 1MB,
598 * some of the upper LP bits are used for RPN bits, meaning that
599 * we need to fill in several entries in hpte_page_sizes[].
600 *
601 * In diagrammatic form, with r = RPN bits and z = page size bits:
602 * PTE LP actual page size
603 * rrrr rrrz >=8KB
604 * rrrr rrzz >=16KB
605 * rrrr rzzz >=32KB
606 * rrrr zzzz >=64KB
607 * ...
608 *
609 * The zzzz bits are implementation-specific but are chosen so that
610 * no encoding for a larger page size uses the same value in its
611 * low-order N bits as the encoding for the 2^(12+N) byte page size
612 * (if it exists).
613 */
init_hpte_page_sizes(void)614 static void init_hpte_page_sizes(void)
615 {
616 long int ap, bp;
617 long int shift, penc;
618
619 for (bp = 0; bp < MMU_PAGE_COUNT; ++bp) {
620 if (!mmu_psize_defs[bp].shift)
621 continue; /* not a supported page size */
622 for (ap = bp; ap < MMU_PAGE_COUNT; ++ap) {
623 penc = mmu_psize_defs[bp].penc[ap];
624 if (penc == -1 || !mmu_psize_defs[ap].shift)
625 continue;
626 shift = mmu_psize_defs[ap].shift - LP_SHIFT;
627 if (shift <= 0)
628 continue; /* should never happen */
629 /*
630 * For page sizes less than 1MB, this loop
631 * replicates the entry for all possible values
632 * of the rrrr bits.
633 */
634 while (penc < (1 << LP_BITS)) {
635 hpte_page_sizes[penc] = (ap << 4) | bp;
636 penc += 1 << shift;
637 }
638 }
639 }
640 }
641
htab_init_page_sizes(void)642 static void __init htab_init_page_sizes(void)
643 {
644 init_hpte_page_sizes();
645
646 if (!debug_pagealloc_enabled()) {
647 /*
648 * Pick a size for the linear mapping. Currently, we only
649 * support 16M, 1M and 4K which is the default
650 */
651 if (mmu_psize_defs[MMU_PAGE_16M].shift)
652 mmu_linear_psize = MMU_PAGE_16M;
653 else if (mmu_psize_defs[MMU_PAGE_1M].shift)
654 mmu_linear_psize = MMU_PAGE_1M;
655 }
656
657 #ifdef CONFIG_PPC_64K_PAGES
658 /*
659 * Pick a size for the ordinary pages. Default is 4K, we support
660 * 64K for user mappings and vmalloc if supported by the processor.
661 * We only use 64k for ioremap if the processor
662 * (and firmware) support cache-inhibited large pages.
663 * If not, we use 4k and set mmu_ci_restrictions so that
664 * hash_page knows to switch processes that use cache-inhibited
665 * mappings to 4k pages.
666 */
667 if (mmu_psize_defs[MMU_PAGE_64K].shift) {
668 mmu_virtual_psize = MMU_PAGE_64K;
669 mmu_vmalloc_psize = MMU_PAGE_64K;
670 if (mmu_linear_psize == MMU_PAGE_4K)
671 mmu_linear_psize = MMU_PAGE_64K;
672 if (mmu_has_feature(MMU_FTR_CI_LARGE_PAGE)) {
673 /*
674 * When running on pSeries using 64k pages for ioremap
675 * would stop us accessing the HEA ethernet. So if we
676 * have the chance of ever seeing one, stay at 4k.
677 */
678 if (!might_have_hea())
679 mmu_io_psize = MMU_PAGE_64K;
680 } else
681 mmu_ci_restrictions = 1;
682 }
683 #endif /* CONFIG_PPC_64K_PAGES */
684
685 #ifdef CONFIG_SPARSEMEM_VMEMMAP
686 /*
687 * We try to use 16M pages for vmemmap if that is supported
688 * and we have at least 1G of RAM at boot
689 */
690 if (mmu_psize_defs[MMU_PAGE_16M].shift &&
691 memblock_phys_mem_size() >= 0x40000000)
692 mmu_vmemmap_psize = MMU_PAGE_16M;
693 else
694 mmu_vmemmap_psize = mmu_virtual_psize;
695 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
696
697 printk(KERN_DEBUG "Page orders: linear mapping = %d, "
698 "virtual = %d, io = %d"
699 #ifdef CONFIG_SPARSEMEM_VMEMMAP
700 ", vmemmap = %d"
701 #endif
702 "\n",
703 mmu_psize_defs[mmu_linear_psize].shift,
704 mmu_psize_defs[mmu_virtual_psize].shift,
705 mmu_psize_defs[mmu_io_psize].shift
706 #ifdef CONFIG_SPARSEMEM_VMEMMAP
707 ,mmu_psize_defs[mmu_vmemmap_psize].shift
708 #endif
709 );
710 }
711
htab_dt_scan_pftsize(unsigned long node,const char * uname,int depth,void * data)712 static int __init htab_dt_scan_pftsize(unsigned long node,
713 const char *uname, int depth,
714 void *data)
715 {
716 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
717 const __be32 *prop;
718
719 /* We are scanning "cpu" nodes only */
720 if (type == NULL || strcmp(type, "cpu") != 0)
721 return 0;
722
723 prop = of_get_flat_dt_prop(node, "ibm,pft-size", NULL);
724 if (prop != NULL) {
725 /* pft_size[0] is the NUMA CEC cookie */
726 ppc64_pft_size = be32_to_cpu(prop[1]);
727 return 1;
728 }
729 return 0;
730 }
731
htab_shift_for_mem_size(unsigned long mem_size)732 unsigned htab_shift_for_mem_size(unsigned long mem_size)
733 {
734 unsigned memshift = __ilog2(mem_size);
735 unsigned pshift = mmu_psize_defs[mmu_virtual_psize].shift;
736 unsigned pteg_shift;
737
738 /* round mem_size up to next power of 2 */
739 if ((1UL << memshift) < mem_size)
740 memshift += 1;
741
742 /* aim for 2 pages / pteg */
743 pteg_shift = memshift - (pshift + 1);
744
745 /*
746 * 2^11 PTEGS of 128 bytes each, ie. 2^18 bytes is the minimum htab
747 * size permitted by the architecture.
748 */
749 return max(pteg_shift + 7, 18U);
750 }
751
htab_get_table_size(void)752 static unsigned long __init htab_get_table_size(void)
753 {
754 /*
755 * If hash size isn't already provided by the platform, we try to
756 * retrieve it from the device-tree. If it's not there neither, we
757 * calculate it now based on the total RAM size
758 */
759 if (ppc64_pft_size == 0)
760 of_scan_flat_dt(htab_dt_scan_pftsize, NULL);
761 if (ppc64_pft_size)
762 return 1UL << ppc64_pft_size;
763
764 return 1UL << htab_shift_for_mem_size(memblock_phys_mem_size());
765 }
766
767 #ifdef CONFIG_MEMORY_HOTPLUG
resize_hpt_for_hotplug(unsigned long new_mem_size)768 int resize_hpt_for_hotplug(unsigned long new_mem_size)
769 {
770 unsigned target_hpt_shift;
771
772 if (!mmu_hash_ops.resize_hpt)
773 return 0;
774
775 target_hpt_shift = htab_shift_for_mem_size(new_mem_size);
776
777 /*
778 * To avoid lots of HPT resizes if memory size is fluctuating
779 * across a boundary, we deliberately have some hysterisis
780 * here: we immediately increase the HPT size if the target
781 * shift exceeds the current shift, but we won't attempt to
782 * reduce unless the target shift is at least 2 below the
783 * current shift
784 */
785 if (target_hpt_shift > ppc64_pft_size ||
786 target_hpt_shift < ppc64_pft_size - 1)
787 return mmu_hash_ops.resize_hpt(target_hpt_shift);
788
789 return 0;
790 }
791
hash__create_section_mapping(unsigned long start,unsigned long end,int nid)792 int hash__create_section_mapping(unsigned long start, unsigned long end, int nid)
793 {
794 int rc;
795
796 if (end >= H_VMALLOC_START) {
797 pr_warn("Outside the supported range\n");
798 return -1;
799 }
800
801 rc = htab_bolt_mapping(start, end, __pa(start),
802 pgprot_val(PAGE_KERNEL), mmu_linear_psize,
803 mmu_kernel_ssize);
804
805 if (rc < 0) {
806 int rc2 = htab_remove_mapping(start, end, mmu_linear_psize,
807 mmu_kernel_ssize);
808 BUG_ON(rc2 && (rc2 != -ENOENT));
809 }
810 return rc;
811 }
812
hash__remove_section_mapping(unsigned long start,unsigned long end)813 int hash__remove_section_mapping(unsigned long start, unsigned long end)
814 {
815 int rc = htab_remove_mapping(start, end, mmu_linear_psize,
816 mmu_kernel_ssize);
817 WARN_ON(rc < 0);
818 return rc;
819 }
820 #endif /* CONFIG_MEMORY_HOTPLUG */
821
hash_init_partition_table(phys_addr_t hash_table,unsigned long htab_size)822 static void __init hash_init_partition_table(phys_addr_t hash_table,
823 unsigned long htab_size)
824 {
825 mmu_partition_table_init();
826
827 /*
828 * PS field (VRMA page size) is not used for LPID 0, hence set to 0.
829 * For now, UPRT is 0 and we have no segment table.
830 */
831 htab_size = __ilog2(htab_size) - 18;
832 mmu_partition_table_set_entry(0, hash_table | htab_size, 0, false);
833 pr_info("Partition table %p\n", partition_tb);
834 }
835
htab_initialize(void)836 static void __init htab_initialize(void)
837 {
838 unsigned long table;
839 unsigned long pteg_count;
840 unsigned long prot;
841 unsigned long base = 0, size = 0;
842 struct memblock_region *reg;
843
844 DBG(" -> htab_initialize()\n");
845
846 if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) {
847 mmu_kernel_ssize = MMU_SEGSIZE_1T;
848 mmu_highuser_ssize = MMU_SEGSIZE_1T;
849 printk(KERN_INFO "Using 1TB segments\n");
850 }
851
852 /*
853 * Calculate the required size of the htab. We want the number of
854 * PTEGs to equal one half the number of real pages.
855 */
856 htab_size_bytes = htab_get_table_size();
857 pteg_count = htab_size_bytes >> 7;
858
859 htab_hash_mask = pteg_count - 1;
860
861 if (firmware_has_feature(FW_FEATURE_LPAR) ||
862 firmware_has_feature(FW_FEATURE_PS3_LV1)) {
863 /* Using a hypervisor which owns the htab */
864 htab_address = NULL;
865 _SDR1 = 0;
866 #ifdef CONFIG_FA_DUMP
867 /*
868 * If firmware assisted dump is active firmware preserves
869 * the contents of htab along with entire partition memory.
870 * Clear the htab if firmware assisted dump is active so
871 * that we dont end up using old mappings.
872 */
873 if (is_fadump_active() && mmu_hash_ops.hpte_clear_all)
874 mmu_hash_ops.hpte_clear_all();
875 #endif
876 } else {
877 unsigned long limit = MEMBLOCK_ALLOC_ANYWHERE;
878
879 #ifdef CONFIG_PPC_CELL
880 /*
881 * Cell may require the hash table down low when using the
882 * Axon IOMMU in order to fit the dynamic region over it, see
883 * comments in cell/iommu.c
884 */
885 if (fdt_subnode_offset(initial_boot_params, 0, "axon") > 0) {
886 limit = 0x80000000;
887 pr_info("Hash table forced below 2G for Axon IOMMU\n");
888 }
889 #endif /* CONFIG_PPC_CELL */
890
891 table = memblock_phys_alloc_range(htab_size_bytes,
892 htab_size_bytes,
893 0, limit);
894 if (!table)
895 panic("ERROR: Failed to allocate %pa bytes below %pa\n",
896 &htab_size_bytes, &limit);
897
898 DBG("Hash table allocated at %lx, size: %lx\n", table,
899 htab_size_bytes);
900
901 htab_address = __va(table);
902
903 /* htab absolute addr + encoded htabsize */
904 _SDR1 = table + __ilog2(htab_size_bytes) - 18;
905
906 /* Initialize the HPT with no entries */
907 memset((void *)table, 0, htab_size_bytes);
908
909 if (!cpu_has_feature(CPU_FTR_ARCH_300))
910 /* Set SDR1 */
911 mtspr(SPRN_SDR1, _SDR1);
912 else
913 hash_init_partition_table(table, htab_size_bytes);
914 }
915
916 prot = pgprot_val(PAGE_KERNEL);
917
918 #ifdef CONFIG_DEBUG_PAGEALLOC
919 if (debug_pagealloc_enabled()) {
920 linear_map_hash_count = memblock_end_of_DRAM() >> PAGE_SHIFT;
921 linear_map_hash_slots = memblock_alloc_try_nid(
922 linear_map_hash_count, 1, MEMBLOCK_LOW_LIMIT,
923 ppc64_rma_size, NUMA_NO_NODE);
924 if (!linear_map_hash_slots)
925 panic("%s: Failed to allocate %lu bytes max_addr=%pa\n",
926 __func__, linear_map_hash_count, &ppc64_rma_size);
927 }
928 #endif /* CONFIG_DEBUG_PAGEALLOC */
929
930 /* create bolted the linear mapping in the hash table */
931 for_each_memblock(memory, reg) {
932 base = (unsigned long)__va(reg->base);
933 size = reg->size;
934
935 DBG("creating mapping for region: %lx..%lx (prot: %lx)\n",
936 base, size, prot);
937
938 if ((base + size) >= H_VMALLOC_START) {
939 pr_warn("Outside the supported range\n");
940 continue;
941 }
942
943 BUG_ON(htab_bolt_mapping(base, base + size, __pa(base),
944 prot, mmu_linear_psize, mmu_kernel_ssize));
945 }
946 memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
947
948 /*
949 * If we have a memory_limit and we've allocated TCEs then we need to
950 * explicitly map the TCE area at the top of RAM. We also cope with the
951 * case that the TCEs start below memory_limit.
952 * tce_alloc_start/end are 16MB aligned so the mapping should work
953 * for either 4K or 16MB pages.
954 */
955 if (tce_alloc_start) {
956 tce_alloc_start = (unsigned long)__va(tce_alloc_start);
957 tce_alloc_end = (unsigned long)__va(tce_alloc_end);
958
959 if (base + size >= tce_alloc_start)
960 tce_alloc_start = base + size + 1;
961
962 BUG_ON(htab_bolt_mapping(tce_alloc_start, tce_alloc_end,
963 __pa(tce_alloc_start), prot,
964 mmu_linear_psize, mmu_kernel_ssize));
965 }
966
967
968 DBG(" <- htab_initialize()\n");
969 }
970 #undef KB
971 #undef MB
972
hash__early_init_devtree(void)973 void __init hash__early_init_devtree(void)
974 {
975 /* Initialize segment sizes */
976 of_scan_flat_dt(htab_dt_scan_seg_sizes, NULL);
977
978 /* Initialize page sizes */
979 htab_scan_page_sizes();
980 }
981
982 static struct hash_mm_context init_hash_mm_context;
hash__early_init_mmu(void)983 void __init hash__early_init_mmu(void)
984 {
985 #ifndef CONFIG_PPC_64K_PAGES
986 /*
987 * We have code in __hash_page_4K() and elsewhere, which assumes it can
988 * do the following:
989 * new_pte |= (slot << H_PAGE_F_GIX_SHIFT) & (H_PAGE_F_SECOND | H_PAGE_F_GIX);
990 *
991 * Where the slot number is between 0-15, and values of 8-15 indicate
992 * the secondary bucket. For that code to work H_PAGE_F_SECOND and
993 * H_PAGE_F_GIX must occupy four contiguous bits in the PTE, and
994 * H_PAGE_F_SECOND must be placed above H_PAGE_F_GIX. Assert that here
995 * with a BUILD_BUG_ON().
996 */
997 BUILD_BUG_ON(H_PAGE_F_SECOND != (1ul << (H_PAGE_F_GIX_SHIFT + 3)));
998 #endif /* CONFIG_PPC_64K_PAGES */
999
1000 htab_init_page_sizes();
1001
1002 /*
1003 * initialize page table size
1004 */
1005 __pte_frag_nr = H_PTE_FRAG_NR;
1006 __pte_frag_size_shift = H_PTE_FRAG_SIZE_SHIFT;
1007 __pmd_frag_nr = H_PMD_FRAG_NR;
1008 __pmd_frag_size_shift = H_PMD_FRAG_SIZE_SHIFT;
1009
1010 __pte_index_size = H_PTE_INDEX_SIZE;
1011 __pmd_index_size = H_PMD_INDEX_SIZE;
1012 __pud_index_size = H_PUD_INDEX_SIZE;
1013 __pgd_index_size = H_PGD_INDEX_SIZE;
1014 __pud_cache_index = H_PUD_CACHE_INDEX;
1015 __pte_table_size = H_PTE_TABLE_SIZE;
1016 __pmd_table_size = H_PMD_TABLE_SIZE;
1017 __pud_table_size = H_PUD_TABLE_SIZE;
1018 __pgd_table_size = H_PGD_TABLE_SIZE;
1019 /*
1020 * 4k use hugepd format, so for hash set then to
1021 * zero
1022 */
1023 __pmd_val_bits = HASH_PMD_VAL_BITS;
1024 __pud_val_bits = HASH_PUD_VAL_BITS;
1025 __pgd_val_bits = HASH_PGD_VAL_BITS;
1026
1027 __kernel_virt_start = H_KERN_VIRT_START;
1028 __vmalloc_start = H_VMALLOC_START;
1029 __vmalloc_end = H_VMALLOC_END;
1030 __kernel_io_start = H_KERN_IO_START;
1031 __kernel_io_end = H_KERN_IO_END;
1032 vmemmap = (struct page *)H_VMEMMAP_START;
1033 ioremap_bot = IOREMAP_BASE;
1034
1035 #ifdef CONFIG_PCI
1036 pci_io_base = ISA_IO_BASE;
1037 #endif
1038
1039 /* Select appropriate backend */
1040 if (firmware_has_feature(FW_FEATURE_PS3_LV1))
1041 ps3_early_mm_init();
1042 else if (firmware_has_feature(FW_FEATURE_LPAR))
1043 hpte_init_pseries();
1044 else if (IS_ENABLED(CONFIG_PPC_NATIVE))
1045 hpte_init_native();
1046
1047 if (!mmu_hash_ops.hpte_insert)
1048 panic("hash__early_init_mmu: No MMU hash ops defined!\n");
1049
1050 /*
1051 * Initialize the MMU Hash table and create the linear mapping
1052 * of memory. Has to be done before SLB initialization as this is
1053 * currently where the page size encoding is obtained.
1054 */
1055 htab_initialize();
1056
1057 init_mm.context.hash_context = &init_hash_mm_context;
1058 mm_ctx_set_slb_addr_limit(&init_mm.context, SLB_ADDR_LIMIT_DEFAULT);
1059
1060 pr_info("Initializing hash mmu with SLB\n");
1061 /* Initialize SLB management */
1062 slb_initialize();
1063
1064 if (cpu_has_feature(CPU_FTR_ARCH_206)
1065 && cpu_has_feature(CPU_FTR_HVMODE))
1066 tlbiel_all();
1067 }
1068
1069 #ifdef CONFIG_SMP
hash__early_init_mmu_secondary(void)1070 void hash__early_init_mmu_secondary(void)
1071 {
1072 /* Initialize hash table for that CPU */
1073 if (!firmware_has_feature(FW_FEATURE_LPAR)) {
1074
1075 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1076 mtspr(SPRN_SDR1, _SDR1);
1077 else
1078 set_ptcr_when_no_uv(__pa(partition_tb) |
1079 (PATB_SIZE_SHIFT - 12));
1080 }
1081 /* Initialize SLB */
1082 slb_initialize();
1083
1084 if (cpu_has_feature(CPU_FTR_ARCH_206)
1085 && cpu_has_feature(CPU_FTR_HVMODE))
1086 tlbiel_all();
1087 }
1088 #endif /* CONFIG_SMP */
1089
1090 /*
1091 * Called by asm hashtable.S for doing lazy icache flush
1092 */
hash_page_do_lazy_icache(unsigned int pp,pte_t pte,int trap)1093 unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap)
1094 {
1095 struct page *page;
1096
1097 if (!pfn_valid(pte_pfn(pte)))
1098 return pp;
1099
1100 page = pte_page(pte);
1101
1102 /* page is dirty */
1103 if (!test_bit(PG_arch_1, &page->flags) && !PageReserved(page)) {
1104 if (trap == 0x400) {
1105 flush_dcache_icache_page(page);
1106 set_bit(PG_arch_1, &page->flags);
1107 } else
1108 pp |= HPTE_R_N;
1109 }
1110 return pp;
1111 }
1112
1113 #ifdef CONFIG_PPC_MM_SLICES
get_paca_psize(unsigned long addr)1114 static unsigned int get_paca_psize(unsigned long addr)
1115 {
1116 unsigned char *psizes;
1117 unsigned long index, mask_index;
1118
1119 if (addr < SLICE_LOW_TOP) {
1120 psizes = get_paca()->mm_ctx_low_slices_psize;
1121 index = GET_LOW_SLICE_INDEX(addr);
1122 } else {
1123 psizes = get_paca()->mm_ctx_high_slices_psize;
1124 index = GET_HIGH_SLICE_INDEX(addr);
1125 }
1126 mask_index = index & 0x1;
1127 return (psizes[index >> 1] >> (mask_index * 4)) & 0xF;
1128 }
1129
1130 #else
get_paca_psize(unsigned long addr)1131 unsigned int get_paca_psize(unsigned long addr)
1132 {
1133 return get_paca()->mm_ctx_user_psize;
1134 }
1135 #endif
1136
1137 /*
1138 * Demote a segment to using 4k pages.
1139 * For now this makes the whole process use 4k pages.
1140 */
1141 #ifdef CONFIG_PPC_64K_PAGES
demote_segment_4k(struct mm_struct * mm,unsigned long addr)1142 void demote_segment_4k(struct mm_struct *mm, unsigned long addr)
1143 {
1144 if (get_slice_psize(mm, addr) == MMU_PAGE_4K)
1145 return;
1146 slice_set_range_psize(mm, addr, 1, MMU_PAGE_4K);
1147 copro_flush_all_slbs(mm);
1148 if ((get_paca_psize(addr) != MMU_PAGE_4K) && (current->mm == mm)) {
1149
1150 copy_mm_to_paca(mm);
1151 slb_flush_and_restore_bolted();
1152 }
1153 }
1154 #endif /* CONFIG_PPC_64K_PAGES */
1155
1156 #ifdef CONFIG_PPC_SUBPAGE_PROT
1157 /*
1158 * This looks up a 2-bit protection code for a 4k subpage of a 64k page.
1159 * Userspace sets the subpage permissions using the subpage_prot system call.
1160 *
1161 * Result is 0: full permissions, _PAGE_RW: read-only,
1162 * _PAGE_RWX: no access.
1163 */
subpage_protection(struct mm_struct * mm,unsigned long ea)1164 static int subpage_protection(struct mm_struct *mm, unsigned long ea)
1165 {
1166 struct subpage_prot_table *spt = mm_ctx_subpage_prot(&mm->context);
1167 u32 spp = 0;
1168 u32 **sbpm, *sbpp;
1169
1170 if (!spt)
1171 return 0;
1172
1173 if (ea >= spt->maxaddr)
1174 return 0;
1175 if (ea < 0x100000000UL) {
1176 /* addresses below 4GB use spt->low_prot */
1177 sbpm = spt->low_prot;
1178 } else {
1179 sbpm = spt->protptrs[ea >> SBP_L3_SHIFT];
1180 if (!sbpm)
1181 return 0;
1182 }
1183 sbpp = sbpm[(ea >> SBP_L2_SHIFT) & (SBP_L2_COUNT - 1)];
1184 if (!sbpp)
1185 return 0;
1186 spp = sbpp[(ea >> PAGE_SHIFT) & (SBP_L1_COUNT - 1)];
1187
1188 /* extract 2-bit bitfield for this 4k subpage */
1189 spp >>= 30 - 2 * ((ea >> 12) & 0xf);
1190
1191 /*
1192 * 0 -> full premission
1193 * 1 -> Read only
1194 * 2 -> no access.
1195 * We return the flag that need to be cleared.
1196 */
1197 spp = ((spp & 2) ? _PAGE_RWX : 0) | ((spp & 1) ? _PAGE_WRITE : 0);
1198 return spp;
1199 }
1200
1201 #else /* CONFIG_PPC_SUBPAGE_PROT */
subpage_protection(struct mm_struct * mm,unsigned long ea)1202 static inline int subpage_protection(struct mm_struct *mm, unsigned long ea)
1203 {
1204 return 0;
1205 }
1206 #endif
1207
hash_failure_debug(unsigned long ea,unsigned long access,unsigned long vsid,unsigned long trap,int ssize,int psize,int lpsize,unsigned long pte)1208 void hash_failure_debug(unsigned long ea, unsigned long access,
1209 unsigned long vsid, unsigned long trap,
1210 int ssize, int psize, int lpsize, unsigned long pte)
1211 {
1212 if (!printk_ratelimit())
1213 return;
1214 pr_info("mm: Hashing failure ! EA=0x%lx access=0x%lx current=%s\n",
1215 ea, access, current->comm);
1216 pr_info(" trap=0x%lx vsid=0x%lx ssize=%d base psize=%d psize %d pte=0x%lx\n",
1217 trap, vsid, ssize, psize, lpsize, pte);
1218 }
1219
check_paca_psize(unsigned long ea,struct mm_struct * mm,int psize,bool user_region)1220 static void check_paca_psize(unsigned long ea, struct mm_struct *mm,
1221 int psize, bool user_region)
1222 {
1223 if (user_region) {
1224 if (psize != get_paca_psize(ea)) {
1225 copy_mm_to_paca(mm);
1226 slb_flush_and_restore_bolted();
1227 }
1228 } else if (get_paca()->vmalloc_sllp !=
1229 mmu_psize_defs[mmu_vmalloc_psize].sllp) {
1230 get_paca()->vmalloc_sllp =
1231 mmu_psize_defs[mmu_vmalloc_psize].sllp;
1232 slb_vmalloc_update();
1233 }
1234 }
1235
1236 /*
1237 * Result code is:
1238 * 0 - handled
1239 * 1 - normal page fault
1240 * -1 - critical hash insertion error
1241 * -2 - access not permitted by subpage protection mechanism
1242 */
hash_page_mm(struct mm_struct * mm,unsigned long ea,unsigned long access,unsigned long trap,unsigned long flags)1243 int hash_page_mm(struct mm_struct *mm, unsigned long ea,
1244 unsigned long access, unsigned long trap,
1245 unsigned long flags)
1246 {
1247 bool is_thp;
1248 enum ctx_state prev_state = exception_enter();
1249 pgd_t *pgdir;
1250 unsigned long vsid;
1251 pte_t *ptep;
1252 unsigned hugeshift;
1253 int rc, user_region = 0;
1254 int psize, ssize;
1255
1256 DBG_LOW("hash_page(ea=%016lx, access=%lx, trap=%lx\n",
1257 ea, access, trap);
1258 trace_hash_fault(ea, access, trap);
1259
1260 /* Get region & vsid */
1261 switch (get_region_id(ea)) {
1262 case USER_REGION_ID:
1263 user_region = 1;
1264 if (! mm) {
1265 DBG_LOW(" user region with no mm !\n");
1266 rc = 1;
1267 goto bail;
1268 }
1269 psize = get_slice_psize(mm, ea);
1270 ssize = user_segment_size(ea);
1271 vsid = get_user_vsid(&mm->context, ea, ssize);
1272 break;
1273 case VMALLOC_REGION_ID:
1274 vsid = get_kernel_vsid(ea, mmu_kernel_ssize);
1275 psize = mmu_vmalloc_psize;
1276 ssize = mmu_kernel_ssize;
1277 break;
1278
1279 case IO_REGION_ID:
1280 vsid = get_kernel_vsid(ea, mmu_kernel_ssize);
1281 psize = mmu_io_psize;
1282 ssize = mmu_kernel_ssize;
1283 break;
1284 default:
1285 /*
1286 * Not a valid range
1287 * Send the problem up to do_page_fault()
1288 */
1289 rc = 1;
1290 goto bail;
1291 }
1292 DBG_LOW(" mm=%p, mm->pgdir=%p, vsid=%016lx\n", mm, mm->pgd, vsid);
1293
1294 /* Bad address. */
1295 if (!vsid) {
1296 DBG_LOW("Bad address!\n");
1297 rc = 1;
1298 goto bail;
1299 }
1300 /* Get pgdir */
1301 pgdir = mm->pgd;
1302 if (pgdir == NULL) {
1303 rc = 1;
1304 goto bail;
1305 }
1306
1307 /* Check CPU locality */
1308 if (user_region && mm_is_thread_local(mm))
1309 flags |= HPTE_LOCAL_UPDATE;
1310
1311 #ifndef CONFIG_PPC_64K_PAGES
1312 /*
1313 * If we use 4K pages and our psize is not 4K, then we might
1314 * be hitting a special driver mapping, and need to align the
1315 * address before we fetch the PTE.
1316 *
1317 * It could also be a hugepage mapping, in which case this is
1318 * not necessary, but it's not harmful, either.
1319 */
1320 if (psize != MMU_PAGE_4K)
1321 ea &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
1322 #endif /* CONFIG_PPC_64K_PAGES */
1323
1324 /* Get PTE and page size from page tables */
1325 ptep = find_linux_pte(pgdir, ea, &is_thp, &hugeshift);
1326 if (ptep == NULL || !pte_present(*ptep)) {
1327 DBG_LOW(" no PTE !\n");
1328 rc = 1;
1329 goto bail;
1330 }
1331
1332 /* Add _PAGE_PRESENT to the required access perm */
1333 access |= _PAGE_PRESENT;
1334
1335 /*
1336 * Pre-check access permissions (will be re-checked atomically
1337 * in __hash_page_XX but this pre-check is a fast path
1338 */
1339 if (!check_pte_access(access, pte_val(*ptep))) {
1340 DBG_LOW(" no access !\n");
1341 rc = 1;
1342 goto bail;
1343 }
1344
1345 if (hugeshift) {
1346 if (is_thp)
1347 rc = __hash_page_thp(ea, access, vsid, (pmd_t *)ptep,
1348 trap, flags, ssize, psize);
1349 #ifdef CONFIG_HUGETLB_PAGE
1350 else
1351 rc = __hash_page_huge(ea, access, vsid, ptep, trap,
1352 flags, ssize, hugeshift, psize);
1353 #else
1354 else {
1355 /*
1356 * if we have hugeshift, and is not transhuge with
1357 * hugetlb disabled, something is really wrong.
1358 */
1359 rc = 1;
1360 WARN_ON(1);
1361 }
1362 #endif
1363 if (current->mm == mm)
1364 check_paca_psize(ea, mm, psize, user_region);
1365
1366 goto bail;
1367 }
1368
1369 #ifndef CONFIG_PPC_64K_PAGES
1370 DBG_LOW(" i-pte: %016lx\n", pte_val(*ptep));
1371 #else
1372 DBG_LOW(" i-pte: %016lx %016lx\n", pte_val(*ptep),
1373 pte_val(*(ptep + PTRS_PER_PTE)));
1374 #endif
1375 /* Do actual hashing */
1376 #ifdef CONFIG_PPC_64K_PAGES
1377 /* If H_PAGE_4K_PFN is set, make sure this is a 4k segment */
1378 if ((pte_val(*ptep) & H_PAGE_4K_PFN) && psize == MMU_PAGE_64K) {
1379 demote_segment_4k(mm, ea);
1380 psize = MMU_PAGE_4K;
1381 }
1382
1383 /*
1384 * If this PTE is non-cacheable and we have restrictions on
1385 * using non cacheable large pages, then we switch to 4k
1386 */
1387 if (mmu_ci_restrictions && psize == MMU_PAGE_64K && pte_ci(*ptep)) {
1388 if (user_region) {
1389 demote_segment_4k(mm, ea);
1390 psize = MMU_PAGE_4K;
1391 } else if (ea < VMALLOC_END) {
1392 /*
1393 * some driver did a non-cacheable mapping
1394 * in vmalloc space, so switch vmalloc
1395 * to 4k pages
1396 */
1397 printk(KERN_ALERT "Reducing vmalloc segment "
1398 "to 4kB pages because of "
1399 "non-cacheable mapping\n");
1400 psize = mmu_vmalloc_psize = MMU_PAGE_4K;
1401 copro_flush_all_slbs(mm);
1402 }
1403 }
1404
1405 #endif /* CONFIG_PPC_64K_PAGES */
1406
1407 if (current->mm == mm)
1408 check_paca_psize(ea, mm, psize, user_region);
1409
1410 #ifdef CONFIG_PPC_64K_PAGES
1411 if (psize == MMU_PAGE_64K)
1412 rc = __hash_page_64K(ea, access, vsid, ptep, trap,
1413 flags, ssize);
1414 else
1415 #endif /* CONFIG_PPC_64K_PAGES */
1416 {
1417 int spp = subpage_protection(mm, ea);
1418 if (access & spp)
1419 rc = -2;
1420 else
1421 rc = __hash_page_4K(ea, access, vsid, ptep, trap,
1422 flags, ssize, spp);
1423 }
1424
1425 /*
1426 * Dump some info in case of hash insertion failure, they should
1427 * never happen so it is really useful to know if/when they do
1428 */
1429 if (rc == -1)
1430 hash_failure_debug(ea, access, vsid, trap, ssize, psize,
1431 psize, pte_val(*ptep));
1432 #ifndef CONFIG_PPC_64K_PAGES
1433 DBG_LOW(" o-pte: %016lx\n", pte_val(*ptep));
1434 #else
1435 DBG_LOW(" o-pte: %016lx %016lx\n", pte_val(*ptep),
1436 pte_val(*(ptep + PTRS_PER_PTE)));
1437 #endif
1438 DBG_LOW(" -> rc=%d\n", rc);
1439
1440 bail:
1441 exception_exit(prev_state);
1442 return rc;
1443 }
1444 EXPORT_SYMBOL_GPL(hash_page_mm);
1445
hash_page(unsigned long ea,unsigned long access,unsigned long trap,unsigned long dsisr)1446 int hash_page(unsigned long ea, unsigned long access, unsigned long trap,
1447 unsigned long dsisr)
1448 {
1449 unsigned long flags = 0;
1450 struct mm_struct *mm = current->mm;
1451
1452 if ((get_region_id(ea) == VMALLOC_REGION_ID) ||
1453 (get_region_id(ea) == IO_REGION_ID))
1454 mm = &init_mm;
1455
1456 if (dsisr & DSISR_NOHPTE)
1457 flags |= HPTE_NOHPTE_UPDATE;
1458
1459 return hash_page_mm(mm, ea, access, trap, flags);
1460 }
1461 EXPORT_SYMBOL_GPL(hash_page);
1462
__hash_page(unsigned long trap,unsigned long ea,unsigned long dsisr,unsigned long msr)1463 int __hash_page(unsigned long trap, unsigned long ea, unsigned long dsisr,
1464 unsigned long msr)
1465 {
1466 unsigned long access = _PAGE_PRESENT | _PAGE_READ;
1467 unsigned long flags = 0;
1468 struct mm_struct *mm = current->mm;
1469 unsigned int region_id = get_region_id(ea);
1470
1471 if ((region_id == VMALLOC_REGION_ID) || (region_id == IO_REGION_ID))
1472 mm = &init_mm;
1473
1474 if (dsisr & DSISR_NOHPTE)
1475 flags |= HPTE_NOHPTE_UPDATE;
1476
1477 if (dsisr & DSISR_ISSTORE)
1478 access |= _PAGE_WRITE;
1479 /*
1480 * We set _PAGE_PRIVILEGED only when
1481 * kernel mode access kernel space.
1482 *
1483 * _PAGE_PRIVILEGED is NOT set
1484 * 1) when kernel mode access user space
1485 * 2) user space access kernel space.
1486 */
1487 access |= _PAGE_PRIVILEGED;
1488 if ((msr & MSR_PR) || (region_id == USER_REGION_ID))
1489 access &= ~_PAGE_PRIVILEGED;
1490
1491 if (trap == 0x400)
1492 access |= _PAGE_EXEC;
1493
1494 return hash_page_mm(mm, ea, access, trap, flags);
1495 }
1496
1497 #ifdef CONFIG_PPC_MM_SLICES
should_hash_preload(struct mm_struct * mm,unsigned long ea)1498 static bool should_hash_preload(struct mm_struct *mm, unsigned long ea)
1499 {
1500 int psize = get_slice_psize(mm, ea);
1501
1502 /* We only prefault standard pages for now */
1503 if (unlikely(psize != mm_ctx_user_psize(&mm->context)))
1504 return false;
1505
1506 /*
1507 * Don't prefault if subpage protection is enabled for the EA.
1508 */
1509 if (unlikely((psize == MMU_PAGE_4K) && subpage_protection(mm, ea)))
1510 return false;
1511
1512 return true;
1513 }
1514 #else
should_hash_preload(struct mm_struct * mm,unsigned long ea)1515 static bool should_hash_preload(struct mm_struct *mm, unsigned long ea)
1516 {
1517 return true;
1518 }
1519 #endif
1520
hash_preload(struct mm_struct * mm,unsigned long ea,bool is_exec,unsigned long trap)1521 static void hash_preload(struct mm_struct *mm, unsigned long ea,
1522 bool is_exec, unsigned long trap)
1523 {
1524 int hugepage_shift;
1525 unsigned long vsid;
1526 pgd_t *pgdir;
1527 pte_t *ptep;
1528 unsigned long flags;
1529 int rc, ssize, update_flags = 0;
1530 unsigned long access = _PAGE_PRESENT | _PAGE_READ | (is_exec ? _PAGE_EXEC : 0);
1531
1532 BUG_ON(get_region_id(ea) != USER_REGION_ID);
1533
1534 if (!should_hash_preload(mm, ea))
1535 return;
1536
1537 DBG_LOW("hash_preload(mm=%p, mm->pgdir=%p, ea=%016lx, access=%lx,"
1538 " trap=%lx\n", mm, mm->pgd, ea, access, trap);
1539
1540 /* Get Linux PTE if available */
1541 pgdir = mm->pgd;
1542 if (pgdir == NULL)
1543 return;
1544
1545 /* Get VSID */
1546 ssize = user_segment_size(ea);
1547 vsid = get_user_vsid(&mm->context, ea, ssize);
1548 if (!vsid)
1549 return;
1550 /*
1551 * Hash doesn't like irqs. Walking linux page table with irq disabled
1552 * saves us from holding multiple locks.
1553 */
1554 local_irq_save(flags);
1555
1556 /*
1557 * THP pages use update_mmu_cache_pmd. We don't do
1558 * hash preload there. Hence can ignore THP here
1559 */
1560 ptep = find_current_mm_pte(pgdir, ea, NULL, &hugepage_shift);
1561 if (!ptep)
1562 goto out_exit;
1563
1564 WARN_ON(hugepage_shift);
1565 #ifdef CONFIG_PPC_64K_PAGES
1566 /* If either H_PAGE_4K_PFN or cache inhibited is set (and we are on
1567 * a 64K kernel), then we don't preload, hash_page() will take
1568 * care of it once we actually try to access the page.
1569 * That way we don't have to duplicate all of the logic for segment
1570 * page size demotion here
1571 */
1572 if ((pte_val(*ptep) & H_PAGE_4K_PFN) || pte_ci(*ptep))
1573 goto out_exit;
1574 #endif /* CONFIG_PPC_64K_PAGES */
1575
1576 /* Is that local to this CPU ? */
1577 if (mm_is_thread_local(mm))
1578 update_flags |= HPTE_LOCAL_UPDATE;
1579
1580 /* Hash it in */
1581 #ifdef CONFIG_PPC_64K_PAGES
1582 if (mm_ctx_user_psize(&mm->context) == MMU_PAGE_64K)
1583 rc = __hash_page_64K(ea, access, vsid, ptep, trap,
1584 update_flags, ssize);
1585 else
1586 #endif /* CONFIG_PPC_64K_PAGES */
1587 rc = __hash_page_4K(ea, access, vsid, ptep, trap, update_flags,
1588 ssize, subpage_protection(mm, ea));
1589
1590 /* Dump some info in case of hash insertion failure, they should
1591 * never happen so it is really useful to know if/when they do
1592 */
1593 if (rc == -1)
1594 hash_failure_debug(ea, access, vsid, trap, ssize,
1595 mm_ctx_user_psize(&mm->context),
1596 mm_ctx_user_psize(&mm->context),
1597 pte_val(*ptep));
1598 out_exit:
1599 local_irq_restore(flags);
1600 }
1601
1602 /*
1603 * This is called at the end of handling a user page fault, when the
1604 * fault has been handled by updating a PTE in the linux page tables.
1605 * We use it to preload an HPTE into the hash table corresponding to
1606 * the updated linux PTE.
1607 *
1608 * This must always be called with the pte lock held.
1609 */
update_mmu_cache(struct vm_area_struct * vma,unsigned long address,pte_t * ptep)1610 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address,
1611 pte_t *ptep)
1612 {
1613 /*
1614 * We don't need to worry about _PAGE_PRESENT here because we are
1615 * called with either mm->page_table_lock held or ptl lock held
1616 */
1617 unsigned long trap;
1618 bool is_exec;
1619
1620 if (radix_enabled()) {
1621 prefetch((void *)address);
1622 return;
1623 }
1624
1625 /* We only want HPTEs for linux PTEs that have _PAGE_ACCESSED set */
1626 if (!pte_young(*ptep) || address >= TASK_SIZE)
1627 return;
1628
1629 /*
1630 * We try to figure out if we are coming from an instruction
1631 * access fault and pass that down to __hash_page so we avoid
1632 * double-faulting on execution of fresh text. We have to test
1633 * for regs NULL since init will get here first thing at boot.
1634 *
1635 * We also avoid filling the hash if not coming from a fault.
1636 */
1637
1638 trap = current->thread.regs ? TRAP(current->thread.regs) : 0UL;
1639 switch (trap) {
1640 case 0x300:
1641 is_exec = false;
1642 break;
1643 case 0x400:
1644 is_exec = true;
1645 break;
1646 default:
1647 return;
1648 }
1649
1650 hash_preload(vma->vm_mm, address, is_exec, trap);
1651 }
1652
1653 #ifdef CONFIG_PPC_MEM_KEYS
1654 /*
1655 * Return the protection key associated with the given address and the
1656 * mm_struct.
1657 */
get_mm_addr_key(struct mm_struct * mm,unsigned long address)1658 u16 get_mm_addr_key(struct mm_struct *mm, unsigned long address)
1659 {
1660 pte_t *ptep;
1661 u16 pkey = 0;
1662 unsigned long flags;
1663
1664 if (!mm || !mm->pgd)
1665 return 0;
1666
1667 local_irq_save(flags);
1668 ptep = find_linux_pte(mm->pgd, address, NULL, NULL);
1669 if (ptep)
1670 pkey = pte_to_pkey_bits(pte_val(READ_ONCE(*ptep)));
1671 local_irq_restore(flags);
1672
1673 return pkey;
1674 }
1675 #endif /* CONFIG_PPC_MEM_KEYS */
1676
1677 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
tm_flush_hash_page(int local)1678 static inline void tm_flush_hash_page(int local)
1679 {
1680 /*
1681 * Transactions are not aborted by tlbiel, only tlbie. Without, syncing a
1682 * page back to a block device w/PIO could pick up transactional data
1683 * (bad!) so we force an abort here. Before the sync the page will be
1684 * made read-only, which will flush_hash_page. BIG ISSUE here: if the
1685 * kernel uses a page from userspace without unmapping it first, it may
1686 * see the speculated version.
1687 */
1688 if (local && cpu_has_feature(CPU_FTR_TM) && current->thread.regs &&
1689 MSR_TM_ACTIVE(current->thread.regs->msr)) {
1690 tm_enable();
1691 tm_abort(TM_CAUSE_TLBI);
1692 }
1693 }
1694 #else
tm_flush_hash_page(int local)1695 static inline void tm_flush_hash_page(int local)
1696 {
1697 }
1698 #endif
1699
1700 /*
1701 * Return the global hash slot, corresponding to the given PTE, which contains
1702 * the HPTE.
1703 */
pte_get_hash_gslot(unsigned long vpn,unsigned long shift,int ssize,real_pte_t rpte,unsigned int subpg_index)1704 unsigned long pte_get_hash_gslot(unsigned long vpn, unsigned long shift,
1705 int ssize, real_pte_t rpte, unsigned int subpg_index)
1706 {
1707 unsigned long hash, gslot, hidx;
1708
1709 hash = hpt_hash(vpn, shift, ssize);
1710 hidx = __rpte_to_hidx(rpte, subpg_index);
1711 if (hidx & _PTEIDX_SECONDARY)
1712 hash = ~hash;
1713 gslot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1714 gslot += hidx & _PTEIDX_GROUP_IX;
1715 return gslot;
1716 }
1717
1718 /*
1719 * WARNING: This is called from hash_low_64.S, if you change this prototype,
1720 * do not forget to update the assembly call site !
1721 */
flush_hash_page(unsigned long vpn,real_pte_t pte,int psize,int ssize,unsigned long flags)1722 void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize, int ssize,
1723 unsigned long flags)
1724 {
1725 unsigned long index, shift, gslot;
1726 int local = flags & HPTE_LOCAL_UPDATE;
1727
1728 DBG_LOW("flush_hash_page(vpn=%016lx)\n", vpn);
1729 pte_iterate_hashed_subpages(pte, psize, vpn, index, shift) {
1730 gslot = pte_get_hash_gslot(vpn, shift, ssize, pte, index);
1731 DBG_LOW(" sub %ld: gslot=%lx\n", index, gslot);
1732 /*
1733 * We use same base page size and actual psize, because we don't
1734 * use these functions for hugepage
1735 */
1736 mmu_hash_ops.hpte_invalidate(gslot, vpn, psize, psize,
1737 ssize, local);
1738 } pte_iterate_hashed_end();
1739
1740 tm_flush_hash_page(local);
1741 }
1742
1743 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
flush_hash_hugepage(unsigned long vsid,unsigned long addr,pmd_t * pmdp,unsigned int psize,int ssize,unsigned long flags)1744 void flush_hash_hugepage(unsigned long vsid, unsigned long addr,
1745 pmd_t *pmdp, unsigned int psize, int ssize,
1746 unsigned long flags)
1747 {
1748 int i, max_hpte_count, valid;
1749 unsigned long s_addr;
1750 unsigned char *hpte_slot_array;
1751 unsigned long hidx, shift, vpn, hash, slot;
1752 int local = flags & HPTE_LOCAL_UPDATE;
1753
1754 s_addr = addr & HPAGE_PMD_MASK;
1755 hpte_slot_array = get_hpte_slot_array(pmdp);
1756 /*
1757 * IF we try to do a HUGE PTE update after a withdraw is done.
1758 * we will find the below NULL. This happens when we do
1759 * split_huge_pmd
1760 */
1761 if (!hpte_slot_array)
1762 return;
1763
1764 if (mmu_hash_ops.hugepage_invalidate) {
1765 mmu_hash_ops.hugepage_invalidate(vsid, s_addr, hpte_slot_array,
1766 psize, ssize, local);
1767 goto tm_abort;
1768 }
1769 /*
1770 * No bluk hpte removal support, invalidate each entry
1771 */
1772 shift = mmu_psize_defs[psize].shift;
1773 max_hpte_count = HPAGE_PMD_SIZE >> shift;
1774 for (i = 0; i < max_hpte_count; i++) {
1775 /*
1776 * 8 bits per each hpte entries
1777 * 000| [ secondary group (one bit) | hidx (3 bits) | valid bit]
1778 */
1779 valid = hpte_valid(hpte_slot_array, i);
1780 if (!valid)
1781 continue;
1782 hidx = hpte_hash_index(hpte_slot_array, i);
1783
1784 /* get the vpn */
1785 addr = s_addr + (i * (1ul << shift));
1786 vpn = hpt_vpn(addr, vsid, ssize);
1787 hash = hpt_hash(vpn, shift, ssize);
1788 if (hidx & _PTEIDX_SECONDARY)
1789 hash = ~hash;
1790
1791 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1792 slot += hidx & _PTEIDX_GROUP_IX;
1793 mmu_hash_ops.hpte_invalidate(slot, vpn, psize,
1794 MMU_PAGE_16M, ssize, local);
1795 }
1796 tm_abort:
1797 tm_flush_hash_page(local);
1798 }
1799 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1800
flush_hash_range(unsigned long number,int local)1801 void flush_hash_range(unsigned long number, int local)
1802 {
1803 if (mmu_hash_ops.flush_hash_range)
1804 mmu_hash_ops.flush_hash_range(number, local);
1805 else {
1806 int i;
1807 struct ppc64_tlb_batch *batch =
1808 this_cpu_ptr(&ppc64_tlb_batch);
1809
1810 for (i = 0; i < number; i++)
1811 flush_hash_page(batch->vpn[i], batch->pte[i],
1812 batch->psize, batch->ssize, local);
1813 }
1814 }
1815
1816 /*
1817 * low_hash_fault is called when we the low level hash code failed
1818 * to instert a PTE due to an hypervisor error
1819 */
low_hash_fault(struct pt_regs * regs,unsigned long address,int rc)1820 void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc)
1821 {
1822 enum ctx_state prev_state = exception_enter();
1823
1824 if (user_mode(regs)) {
1825 #ifdef CONFIG_PPC_SUBPAGE_PROT
1826 if (rc == -2)
1827 _exception(SIGSEGV, regs, SEGV_ACCERR, address);
1828 else
1829 #endif
1830 _exception(SIGBUS, regs, BUS_ADRERR, address);
1831 } else
1832 bad_page_fault(regs, address, SIGBUS);
1833
1834 exception_exit(prev_state);
1835 }
1836
hpte_insert_repeating(unsigned long hash,unsigned long vpn,unsigned long pa,unsigned long rflags,unsigned long vflags,int psize,int ssize)1837 long hpte_insert_repeating(unsigned long hash, unsigned long vpn,
1838 unsigned long pa, unsigned long rflags,
1839 unsigned long vflags, int psize, int ssize)
1840 {
1841 unsigned long hpte_group;
1842 long slot;
1843
1844 repeat:
1845 hpte_group = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1846
1847 /* Insert into the hash table, primary slot */
1848 slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags, vflags,
1849 psize, psize, ssize);
1850
1851 /* Primary is full, try the secondary */
1852 if (unlikely(slot == -1)) {
1853 hpte_group = (~hash & htab_hash_mask) * HPTES_PER_GROUP;
1854 slot = mmu_hash_ops.hpte_insert(hpte_group, vpn, pa, rflags,
1855 vflags | HPTE_V_SECONDARY,
1856 psize, psize, ssize);
1857 if (slot == -1) {
1858 if (mftb() & 0x1)
1859 hpte_group = (hash & htab_hash_mask) *
1860 HPTES_PER_GROUP;
1861
1862 mmu_hash_ops.hpte_remove(hpte_group);
1863 goto repeat;
1864 }
1865 }
1866
1867 return slot;
1868 }
1869
1870 #ifdef CONFIG_DEBUG_PAGEALLOC
kernel_map_linear_page(unsigned long vaddr,unsigned long lmi)1871 static void kernel_map_linear_page(unsigned long vaddr, unsigned long lmi)
1872 {
1873 unsigned long hash;
1874 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1875 unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
1876 unsigned long mode = htab_convert_pte_flags(pgprot_val(PAGE_KERNEL));
1877 long ret;
1878
1879 hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize);
1880
1881 /* Don't create HPTE entries for bad address */
1882 if (!vsid)
1883 return;
1884
1885 ret = hpte_insert_repeating(hash, vpn, __pa(vaddr), mode,
1886 HPTE_V_BOLTED,
1887 mmu_linear_psize, mmu_kernel_ssize);
1888
1889 BUG_ON (ret < 0);
1890 spin_lock(&linear_map_hash_lock);
1891 BUG_ON(linear_map_hash_slots[lmi] & 0x80);
1892 linear_map_hash_slots[lmi] = ret | 0x80;
1893 spin_unlock(&linear_map_hash_lock);
1894 }
1895
kernel_unmap_linear_page(unsigned long vaddr,unsigned long lmi)1896 static void kernel_unmap_linear_page(unsigned long vaddr, unsigned long lmi)
1897 {
1898 unsigned long hash, hidx, slot;
1899 unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
1900 unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
1901
1902 hash = hpt_hash(vpn, PAGE_SHIFT, mmu_kernel_ssize);
1903 spin_lock(&linear_map_hash_lock);
1904 BUG_ON(!(linear_map_hash_slots[lmi] & 0x80));
1905 hidx = linear_map_hash_slots[lmi] & 0x7f;
1906 linear_map_hash_slots[lmi] = 0;
1907 spin_unlock(&linear_map_hash_lock);
1908 if (hidx & _PTEIDX_SECONDARY)
1909 hash = ~hash;
1910 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
1911 slot += hidx & _PTEIDX_GROUP_IX;
1912 mmu_hash_ops.hpte_invalidate(slot, vpn, mmu_linear_psize,
1913 mmu_linear_psize,
1914 mmu_kernel_ssize, 0);
1915 }
1916
__kernel_map_pages(struct page * page,int numpages,int enable)1917 void __kernel_map_pages(struct page *page, int numpages, int enable)
1918 {
1919 unsigned long flags, vaddr, lmi;
1920 int i;
1921
1922 local_irq_save(flags);
1923 for (i = 0; i < numpages; i++, page++) {
1924 vaddr = (unsigned long)page_address(page);
1925 lmi = __pa(vaddr) >> PAGE_SHIFT;
1926 if (lmi >= linear_map_hash_count)
1927 continue;
1928 if (enable)
1929 kernel_map_linear_page(vaddr, lmi);
1930 else
1931 kernel_unmap_linear_page(vaddr, lmi);
1932 }
1933 local_irq_restore(flags);
1934 }
1935 #endif /* CONFIG_DEBUG_PAGEALLOC */
1936
hash__setup_initial_memory_limit(phys_addr_t first_memblock_base,phys_addr_t first_memblock_size)1937 void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base,
1938 phys_addr_t first_memblock_size)
1939 {
1940 /*
1941 * We don't currently support the first MEMBLOCK not mapping 0
1942 * physical on those processors
1943 */
1944 BUG_ON(first_memblock_base != 0);
1945
1946 /*
1947 * On virtualized systems the first entry is our RMA region aka VRMA,
1948 * non-virtualized 64-bit hash MMU systems don't have a limitation
1949 * on real mode access.
1950 *
1951 * For guests on platforms before POWER9, we clamp the it limit to 1G
1952 * to avoid some funky things such as RTAS bugs etc...
1953 *
1954 * On POWER9 we limit to 1TB in case the host erroneously told us that
1955 * the RMA was >1TB. Effective address bits 0:23 are treated as zero
1956 * (meaning the access is aliased to zero i.e. addr = addr % 1TB)
1957 * for virtual real mode addressing and so it doesn't make sense to
1958 * have an area larger than 1TB as it can't be addressed.
1959 */
1960 if (!early_cpu_has_feature(CPU_FTR_HVMODE)) {
1961 ppc64_rma_size = first_memblock_size;
1962 if (!early_cpu_has_feature(CPU_FTR_ARCH_300))
1963 ppc64_rma_size = min_t(u64, ppc64_rma_size, 0x40000000);
1964 else
1965 ppc64_rma_size = min_t(u64, ppc64_rma_size,
1966 1UL << SID_SHIFT_1T);
1967
1968 /* Finally limit subsequent allocations */
1969 memblock_set_current_limit(ppc64_rma_size);
1970 } else {
1971 ppc64_rma_size = ULONG_MAX;
1972 }
1973 }
1974
1975 #ifdef CONFIG_DEBUG_FS
1976
hpt_order_get(void * data,u64 * val)1977 static int hpt_order_get(void *data, u64 *val)
1978 {
1979 *val = ppc64_pft_size;
1980 return 0;
1981 }
1982
hpt_order_set(void * data,u64 val)1983 static int hpt_order_set(void *data, u64 val)
1984 {
1985 int ret;
1986
1987 if (!mmu_hash_ops.resize_hpt)
1988 return -ENODEV;
1989
1990 cpus_read_lock();
1991 ret = mmu_hash_ops.resize_hpt(val);
1992 cpus_read_unlock();
1993
1994 return ret;
1995 }
1996
1997 DEFINE_DEBUGFS_ATTRIBUTE(fops_hpt_order, hpt_order_get, hpt_order_set, "%llu\n");
1998
hash64_debugfs(void)1999 static int __init hash64_debugfs(void)
2000 {
2001 if (!debugfs_create_file_unsafe("hpt_order", 0600, powerpc_debugfs_root,
2002 NULL, &fops_hpt_order)) {
2003 pr_err("lpar: unable to create hpt_order debugsfs file\n");
2004 }
2005
2006 return 0;
2007 }
2008 machine_device_initcall(pseries, hash64_debugfs);
2009 #endif /* CONFIG_DEBUG_FS */
2010
print_system_hash_info(void)2011 void __init print_system_hash_info(void)
2012 {
2013 pr_info("ppc64_pft_size = 0x%llx\n", ppc64_pft_size);
2014
2015 if (htab_hash_mask)
2016 pr_info("htab_hash_mask = 0x%lx\n", htab_hash_mask);
2017 }
2018