1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * srmmu.c: SRMMU specific routines for memory management.
4 *
5 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
6 * Copyright (C) 1995,2002 Pete Zaitcev (zaitcev@yahoo.com)
7 * Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be)
8 * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
9 * Copyright (C) 1999,2000 Anton Blanchard (anton@samba.org)
10 */
11
12 #include <linux/seq_file.h>
13 #include <linux/spinlock.h>
14 #include <linux/memblock.h>
15 #include <linux/pagemap.h>
16 #include <linux/vmalloc.h>
17 #include <linux/kdebug.h>
18 #include <linux/export.h>
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/log2.h>
22 #include <linux/gfp.h>
23 #include <linux/fs.h>
24 #include <linux/mm.h>
25
26 #include <asm/mmu_context.h>
27 #include <asm/cacheflush.h>
28 #include <asm/tlbflush.h>
29 #include <asm/io-unit.h>
30 #include <asm/pgalloc.h>
31 #include <asm/pgtable.h>
32 #include <asm/bitext.h>
33 #include <asm/vaddrs.h>
34 #include <asm/cache.h>
35 #include <asm/traps.h>
36 #include <asm/oplib.h>
37 #include <asm/mbus.h>
38 #include <asm/page.h>
39 #include <asm/asi.h>
40 #include <asm/smp.h>
41 #include <asm/io.h>
42
43 /* Now the cpu specific definitions. */
44 #include <asm/turbosparc.h>
45 #include <asm/tsunami.h>
46 #include <asm/viking.h>
47 #include <asm/swift.h>
48 #include <asm/leon.h>
49 #include <asm/mxcc.h>
50 #include <asm/ross.h>
51
52 #include "mm_32.h"
53
54 enum mbus_module srmmu_modtype;
55 static unsigned int hwbug_bitmask;
56 int vac_cache_size;
57 EXPORT_SYMBOL(vac_cache_size);
58 int vac_line_size;
59
60 extern struct resource sparc_iomap;
61
62 extern unsigned long last_valid_pfn;
63
64 static pgd_t *srmmu_swapper_pg_dir;
65
66 const struct sparc32_cachetlb_ops *sparc32_cachetlb_ops;
67 EXPORT_SYMBOL(sparc32_cachetlb_ops);
68
69 #ifdef CONFIG_SMP
70 const struct sparc32_cachetlb_ops *local_ops;
71
72 #define FLUSH_BEGIN(mm)
73 #define FLUSH_END
74 #else
75 #define FLUSH_BEGIN(mm) if ((mm)->context != NO_CONTEXT) {
76 #define FLUSH_END }
77 #endif
78
79 int flush_page_for_dma_global = 1;
80
81 char *srmmu_name;
82
83 ctxd_t *srmmu_ctx_table_phys;
84 static ctxd_t *srmmu_context_table;
85
86 int viking_mxcc_present;
87 static DEFINE_SPINLOCK(srmmu_context_spinlock);
88
89 static int is_hypersparc;
90
91 static int srmmu_cache_pagetables;
92
93 /* these will be initialized in srmmu_nocache_calcsize() */
94 static unsigned long srmmu_nocache_size;
95 static unsigned long srmmu_nocache_end;
96
97 /* 1 bit <=> 256 bytes of nocache <=> 64 PTEs */
98 #define SRMMU_NOCACHE_BITMAP_SHIFT (PAGE_SHIFT - 4)
99
100 /* The context table is a nocache user with the biggest alignment needs. */
101 #define SRMMU_NOCACHE_ALIGN_MAX (sizeof(ctxd_t)*SRMMU_MAX_CONTEXTS)
102
103 void *srmmu_nocache_pool;
104 static struct bit_map srmmu_nocache_map;
105
srmmu_pmd_none(pmd_t pmd)106 static inline int srmmu_pmd_none(pmd_t pmd)
107 { return !(pmd_val(pmd) & 0xFFFFFFF); }
108
109 /* XXX should we hyper_flush_whole_icache here - Anton */
srmmu_ctxd_set(ctxd_t * ctxp,pgd_t * pgdp)110 static inline void srmmu_ctxd_set(ctxd_t *ctxp, pgd_t *pgdp)
111 {
112 pte_t pte;
113
114 pte = __pte((SRMMU_ET_PTD | (__nocache_pa(pgdp) >> 4)));
115 set_pte((pte_t *)ctxp, pte);
116 }
117
118 /*
119 * Locations of MSI Registers.
120 */
121 #define MSI_MBUS_ARBEN 0xe0001008 /* MBus Arbiter Enable register */
122
123 /*
124 * Useful bits in the MSI Registers.
125 */
126 #define MSI_ASYNC_MODE 0x80000000 /* Operate the MSI asynchronously */
127
msi_set_sync(void)128 static void msi_set_sync(void)
129 {
130 __asm__ __volatile__ ("lda [%0] %1, %%g3\n\t"
131 "andn %%g3, %2, %%g3\n\t"
132 "sta %%g3, [%0] %1\n\t" : :
133 "r" (MSI_MBUS_ARBEN),
134 "i" (ASI_M_CTL), "r" (MSI_ASYNC_MODE) : "g3");
135 }
136
pmd_set(pmd_t * pmdp,pte_t * ptep)137 void pmd_set(pmd_t *pmdp, pte_t *ptep)
138 {
139 unsigned long ptp; /* Physical address, shifted right by 4 */
140 int i;
141
142 ptp = __nocache_pa(ptep) >> 4;
143 for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++) {
144 set_pte((pte_t *)&pmdp->pmdv[i], __pte(SRMMU_ET_PTD | ptp));
145 ptp += (SRMMU_REAL_PTRS_PER_PTE * sizeof(pte_t) >> 4);
146 }
147 }
148
pmd_populate(struct mm_struct * mm,pmd_t * pmdp,struct page * ptep)149 void pmd_populate(struct mm_struct *mm, pmd_t *pmdp, struct page *ptep)
150 {
151 unsigned long ptp; /* Physical address, shifted right by 4 */
152 int i;
153
154 ptp = page_to_pfn(ptep) << (PAGE_SHIFT-4); /* watch for overflow */
155 for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++) {
156 set_pte((pte_t *)&pmdp->pmdv[i], __pte(SRMMU_ET_PTD | ptp));
157 ptp += (SRMMU_REAL_PTRS_PER_PTE * sizeof(pte_t) >> 4);
158 }
159 }
160
161 /* Find an entry in the third-level page table.. */
pte_offset_kernel(pmd_t * dir,unsigned long address)162 pte_t *pte_offset_kernel(pmd_t *dir, unsigned long address)
163 {
164 void *pte;
165
166 pte = __nocache_va((dir->pmdv[0] & SRMMU_PTD_PMASK) << 4);
167 return (pte_t *) pte +
168 ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1));
169 }
170
171 /*
172 * size: bytes to allocate in the nocache area.
173 * align: bytes, number to align at.
174 * Returns the virtual address of the allocated area.
175 */
__srmmu_get_nocache(int size,int align)176 static void *__srmmu_get_nocache(int size, int align)
177 {
178 int offset;
179 unsigned long addr;
180
181 if (size < SRMMU_NOCACHE_BITMAP_SHIFT) {
182 printk(KERN_ERR "Size 0x%x too small for nocache request\n",
183 size);
184 size = SRMMU_NOCACHE_BITMAP_SHIFT;
185 }
186 if (size & (SRMMU_NOCACHE_BITMAP_SHIFT - 1)) {
187 printk(KERN_ERR "Size 0x%x unaligned int nocache request\n",
188 size);
189 size += SRMMU_NOCACHE_BITMAP_SHIFT - 1;
190 }
191 BUG_ON(align > SRMMU_NOCACHE_ALIGN_MAX);
192
193 offset = bit_map_string_get(&srmmu_nocache_map,
194 size >> SRMMU_NOCACHE_BITMAP_SHIFT,
195 align >> SRMMU_NOCACHE_BITMAP_SHIFT);
196 if (offset == -1) {
197 printk(KERN_ERR "srmmu: out of nocache %d: %d/%d\n",
198 size, (int) srmmu_nocache_size,
199 srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT);
200 return NULL;
201 }
202
203 addr = SRMMU_NOCACHE_VADDR + (offset << SRMMU_NOCACHE_BITMAP_SHIFT);
204 return (void *)addr;
205 }
206
srmmu_get_nocache(int size,int align)207 void *srmmu_get_nocache(int size, int align)
208 {
209 void *tmp;
210
211 tmp = __srmmu_get_nocache(size, align);
212
213 if (tmp)
214 memset(tmp, 0, size);
215
216 return tmp;
217 }
218
srmmu_free_nocache(void * addr,int size)219 void srmmu_free_nocache(void *addr, int size)
220 {
221 unsigned long vaddr;
222 int offset;
223
224 vaddr = (unsigned long)addr;
225 if (vaddr < SRMMU_NOCACHE_VADDR) {
226 printk("Vaddr %lx is smaller than nocache base 0x%lx\n",
227 vaddr, (unsigned long)SRMMU_NOCACHE_VADDR);
228 BUG();
229 }
230 if (vaddr + size > srmmu_nocache_end) {
231 printk("Vaddr %lx is bigger than nocache end 0x%lx\n",
232 vaddr, srmmu_nocache_end);
233 BUG();
234 }
235 if (!is_power_of_2(size)) {
236 printk("Size 0x%x is not a power of 2\n", size);
237 BUG();
238 }
239 if (size < SRMMU_NOCACHE_BITMAP_SHIFT) {
240 printk("Size 0x%x is too small\n", size);
241 BUG();
242 }
243 if (vaddr & (size - 1)) {
244 printk("Vaddr %lx is not aligned to size 0x%x\n", vaddr, size);
245 BUG();
246 }
247
248 offset = (vaddr - SRMMU_NOCACHE_VADDR) >> SRMMU_NOCACHE_BITMAP_SHIFT;
249 size = size >> SRMMU_NOCACHE_BITMAP_SHIFT;
250
251 bit_map_clear(&srmmu_nocache_map, offset, size);
252 }
253
254 static void srmmu_early_allocate_ptable_skeleton(unsigned long start,
255 unsigned long end);
256
257 /* Return how much physical memory we have. */
probe_memory(void)258 static unsigned long __init probe_memory(void)
259 {
260 unsigned long total = 0;
261 int i;
262
263 for (i = 0; sp_banks[i].num_bytes; i++)
264 total += sp_banks[i].num_bytes;
265
266 return total;
267 }
268
269 /*
270 * Reserve nocache dynamically proportionally to the amount of
271 * system RAM. -- Tomas Szepe <szepe@pinerecords.com>, June 2002
272 */
srmmu_nocache_calcsize(void)273 static void __init srmmu_nocache_calcsize(void)
274 {
275 unsigned long sysmemavail = probe_memory() / 1024;
276 int srmmu_nocache_npages;
277
278 srmmu_nocache_npages =
279 sysmemavail / SRMMU_NOCACHE_ALCRATIO / 1024 * 256;
280
281 /* P3 XXX The 4x overuse: corroborated by /proc/meminfo. */
282 // if (srmmu_nocache_npages < 256) srmmu_nocache_npages = 256;
283 if (srmmu_nocache_npages < SRMMU_MIN_NOCACHE_PAGES)
284 srmmu_nocache_npages = SRMMU_MIN_NOCACHE_PAGES;
285
286 /* anything above 1280 blows up */
287 if (srmmu_nocache_npages > SRMMU_MAX_NOCACHE_PAGES)
288 srmmu_nocache_npages = SRMMU_MAX_NOCACHE_PAGES;
289
290 srmmu_nocache_size = srmmu_nocache_npages * PAGE_SIZE;
291 srmmu_nocache_end = SRMMU_NOCACHE_VADDR + srmmu_nocache_size;
292 }
293
srmmu_nocache_init(void)294 static void __init srmmu_nocache_init(void)
295 {
296 void *srmmu_nocache_bitmap;
297 unsigned int bitmap_bits;
298 pgd_t *pgd;
299 pmd_t *pmd;
300 pte_t *pte;
301 unsigned long paddr, vaddr;
302 unsigned long pteval;
303
304 bitmap_bits = srmmu_nocache_size >> SRMMU_NOCACHE_BITMAP_SHIFT;
305
306 srmmu_nocache_pool = memblock_alloc(srmmu_nocache_size,
307 SRMMU_NOCACHE_ALIGN_MAX);
308 if (!srmmu_nocache_pool)
309 panic("%s: Failed to allocate %lu bytes align=0x%x\n",
310 __func__, srmmu_nocache_size, SRMMU_NOCACHE_ALIGN_MAX);
311 memset(srmmu_nocache_pool, 0, srmmu_nocache_size);
312
313 srmmu_nocache_bitmap =
314 memblock_alloc(BITS_TO_LONGS(bitmap_bits) * sizeof(long),
315 SMP_CACHE_BYTES);
316 if (!srmmu_nocache_bitmap)
317 panic("%s: Failed to allocate %zu bytes\n", __func__,
318 BITS_TO_LONGS(bitmap_bits) * sizeof(long));
319 bit_map_init(&srmmu_nocache_map, srmmu_nocache_bitmap, bitmap_bits);
320
321 srmmu_swapper_pg_dir = __srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE, SRMMU_PGD_TABLE_SIZE);
322 memset(__nocache_fix(srmmu_swapper_pg_dir), 0, SRMMU_PGD_TABLE_SIZE);
323 init_mm.pgd = srmmu_swapper_pg_dir;
324
325 srmmu_early_allocate_ptable_skeleton(SRMMU_NOCACHE_VADDR, srmmu_nocache_end);
326
327 paddr = __pa((unsigned long)srmmu_nocache_pool);
328 vaddr = SRMMU_NOCACHE_VADDR;
329
330 while (vaddr < srmmu_nocache_end) {
331 pgd = pgd_offset_k(vaddr);
332 pmd = pmd_offset(__nocache_fix(pgd), vaddr);
333 pte = pte_offset_kernel(__nocache_fix(pmd), vaddr);
334
335 pteval = ((paddr >> 4) | SRMMU_ET_PTE | SRMMU_PRIV);
336
337 if (srmmu_cache_pagetables)
338 pteval |= SRMMU_CACHE;
339
340 set_pte(__nocache_fix(pte), __pte(pteval));
341
342 vaddr += PAGE_SIZE;
343 paddr += PAGE_SIZE;
344 }
345
346 flush_cache_all();
347 flush_tlb_all();
348 }
349
get_pgd_fast(void)350 pgd_t *get_pgd_fast(void)
351 {
352 pgd_t *pgd = NULL;
353
354 pgd = __srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE, SRMMU_PGD_TABLE_SIZE);
355 if (pgd) {
356 pgd_t *init = pgd_offset_k(0);
357 memset(pgd, 0, USER_PTRS_PER_PGD * sizeof(pgd_t));
358 memcpy(pgd + USER_PTRS_PER_PGD, init + USER_PTRS_PER_PGD,
359 (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
360 }
361
362 return pgd;
363 }
364
365 /*
366 * Hardware needs alignment to 256 only, but we align to whole page size
367 * to reduce fragmentation problems due to the buddy principle.
368 * XXX Provide actual fragmentation statistics in /proc.
369 *
370 * Alignments up to the page size are the same for physical and virtual
371 * addresses of the nocache area.
372 */
pte_alloc_one(struct mm_struct * mm)373 pgtable_t pte_alloc_one(struct mm_struct *mm)
374 {
375 unsigned long pte;
376 struct page *page;
377
378 if ((pte = (unsigned long)pte_alloc_one_kernel(mm)) == 0)
379 return NULL;
380 page = pfn_to_page(__nocache_pa(pte) >> PAGE_SHIFT);
381 if (!pgtable_pte_page_ctor(page)) {
382 return NULL;
383 }
384 return page;
385 }
386
pte_free(struct mm_struct * mm,pgtable_t pte)387 void pte_free(struct mm_struct *mm, pgtable_t pte)
388 {
389 unsigned long p;
390
391 pgtable_pte_page_dtor(pte);
392 p = (unsigned long)page_address(pte); /* Cached address (for test) */
393 if (p == 0)
394 BUG();
395 p = page_to_pfn(pte) << PAGE_SHIFT; /* Physical address */
396
397 /* free non cached virtual address*/
398 srmmu_free_nocache(__nocache_va(p), PTE_SIZE);
399 }
400
401 /* context handling - a dynamically sized pool is used */
402 #define NO_CONTEXT -1
403
404 struct ctx_list {
405 struct ctx_list *next;
406 struct ctx_list *prev;
407 unsigned int ctx_number;
408 struct mm_struct *ctx_mm;
409 };
410
411 static struct ctx_list *ctx_list_pool;
412 static struct ctx_list ctx_free;
413 static struct ctx_list ctx_used;
414
415 /* At boot time we determine the number of contexts */
416 static int num_contexts;
417
remove_from_ctx_list(struct ctx_list * entry)418 static inline void remove_from_ctx_list(struct ctx_list *entry)
419 {
420 entry->next->prev = entry->prev;
421 entry->prev->next = entry->next;
422 }
423
add_to_ctx_list(struct ctx_list * head,struct ctx_list * entry)424 static inline void add_to_ctx_list(struct ctx_list *head, struct ctx_list *entry)
425 {
426 entry->next = head;
427 (entry->prev = head->prev)->next = entry;
428 head->prev = entry;
429 }
430 #define add_to_free_ctxlist(entry) add_to_ctx_list(&ctx_free, entry)
431 #define add_to_used_ctxlist(entry) add_to_ctx_list(&ctx_used, entry)
432
433
alloc_context(struct mm_struct * old_mm,struct mm_struct * mm)434 static inline void alloc_context(struct mm_struct *old_mm, struct mm_struct *mm)
435 {
436 struct ctx_list *ctxp;
437
438 ctxp = ctx_free.next;
439 if (ctxp != &ctx_free) {
440 remove_from_ctx_list(ctxp);
441 add_to_used_ctxlist(ctxp);
442 mm->context = ctxp->ctx_number;
443 ctxp->ctx_mm = mm;
444 return;
445 }
446 ctxp = ctx_used.next;
447 if (ctxp->ctx_mm == old_mm)
448 ctxp = ctxp->next;
449 if (ctxp == &ctx_used)
450 panic("out of mmu contexts");
451 flush_cache_mm(ctxp->ctx_mm);
452 flush_tlb_mm(ctxp->ctx_mm);
453 remove_from_ctx_list(ctxp);
454 add_to_used_ctxlist(ctxp);
455 ctxp->ctx_mm->context = NO_CONTEXT;
456 ctxp->ctx_mm = mm;
457 mm->context = ctxp->ctx_number;
458 }
459
free_context(int context)460 static inline void free_context(int context)
461 {
462 struct ctx_list *ctx_old;
463
464 ctx_old = ctx_list_pool + context;
465 remove_from_ctx_list(ctx_old);
466 add_to_free_ctxlist(ctx_old);
467 }
468
sparc_context_init(int numctx)469 static void __init sparc_context_init(int numctx)
470 {
471 int ctx;
472 unsigned long size;
473
474 size = numctx * sizeof(struct ctx_list);
475 ctx_list_pool = memblock_alloc(size, SMP_CACHE_BYTES);
476 if (!ctx_list_pool)
477 panic("%s: Failed to allocate %lu bytes\n", __func__, size);
478
479 for (ctx = 0; ctx < numctx; ctx++) {
480 struct ctx_list *clist;
481
482 clist = (ctx_list_pool + ctx);
483 clist->ctx_number = ctx;
484 clist->ctx_mm = NULL;
485 }
486 ctx_free.next = ctx_free.prev = &ctx_free;
487 ctx_used.next = ctx_used.prev = &ctx_used;
488 for (ctx = 0; ctx < numctx; ctx++)
489 add_to_free_ctxlist(ctx_list_pool + ctx);
490 }
491
switch_mm(struct mm_struct * old_mm,struct mm_struct * mm,struct task_struct * tsk)492 void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm,
493 struct task_struct *tsk)
494 {
495 unsigned long flags;
496
497 if (mm->context == NO_CONTEXT) {
498 spin_lock_irqsave(&srmmu_context_spinlock, flags);
499 alloc_context(old_mm, mm);
500 spin_unlock_irqrestore(&srmmu_context_spinlock, flags);
501 srmmu_ctxd_set(&srmmu_context_table[mm->context], mm->pgd);
502 }
503
504 if (sparc_cpu_model == sparc_leon)
505 leon_switch_mm();
506
507 if (is_hypersparc)
508 hyper_flush_whole_icache();
509
510 srmmu_set_context(mm->context);
511 }
512
513 /* Low level IO area allocation on the SRMMU. */
srmmu_mapioaddr(unsigned long physaddr,unsigned long virt_addr,int bus_type)514 static inline void srmmu_mapioaddr(unsigned long physaddr,
515 unsigned long virt_addr, int bus_type)
516 {
517 pgd_t *pgdp;
518 pmd_t *pmdp;
519 pte_t *ptep;
520 unsigned long tmp;
521
522 physaddr &= PAGE_MASK;
523 pgdp = pgd_offset_k(virt_addr);
524 pmdp = pmd_offset(pgdp, virt_addr);
525 ptep = pte_offset_kernel(pmdp, virt_addr);
526 tmp = (physaddr >> 4) | SRMMU_ET_PTE;
527
528 /* I need to test whether this is consistent over all
529 * sun4m's. The bus_type represents the upper 4 bits of
530 * 36-bit physical address on the I/O space lines...
531 */
532 tmp |= (bus_type << 28);
533 tmp |= SRMMU_PRIV;
534 __flush_page_to_ram(virt_addr);
535 set_pte(ptep, __pte(tmp));
536 }
537
srmmu_mapiorange(unsigned int bus,unsigned long xpa,unsigned long xva,unsigned int len)538 void srmmu_mapiorange(unsigned int bus, unsigned long xpa,
539 unsigned long xva, unsigned int len)
540 {
541 while (len != 0) {
542 len -= PAGE_SIZE;
543 srmmu_mapioaddr(xpa, xva, bus);
544 xva += PAGE_SIZE;
545 xpa += PAGE_SIZE;
546 }
547 flush_tlb_all();
548 }
549
srmmu_unmapioaddr(unsigned long virt_addr)550 static inline void srmmu_unmapioaddr(unsigned long virt_addr)
551 {
552 pgd_t *pgdp;
553 pmd_t *pmdp;
554 pte_t *ptep;
555
556 pgdp = pgd_offset_k(virt_addr);
557 pmdp = pmd_offset(pgdp, virt_addr);
558 ptep = pte_offset_kernel(pmdp, virt_addr);
559
560 /* No need to flush uncacheable page. */
561 __pte_clear(ptep);
562 }
563
srmmu_unmapiorange(unsigned long virt_addr,unsigned int len)564 void srmmu_unmapiorange(unsigned long virt_addr, unsigned int len)
565 {
566 while (len != 0) {
567 len -= PAGE_SIZE;
568 srmmu_unmapioaddr(virt_addr);
569 virt_addr += PAGE_SIZE;
570 }
571 flush_tlb_all();
572 }
573
574 /* tsunami.S */
575 extern void tsunami_flush_cache_all(void);
576 extern void tsunami_flush_cache_mm(struct mm_struct *mm);
577 extern void tsunami_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
578 extern void tsunami_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
579 extern void tsunami_flush_page_to_ram(unsigned long page);
580 extern void tsunami_flush_page_for_dma(unsigned long page);
581 extern void tsunami_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
582 extern void tsunami_flush_tlb_all(void);
583 extern void tsunami_flush_tlb_mm(struct mm_struct *mm);
584 extern void tsunami_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
585 extern void tsunami_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
586 extern void tsunami_setup_blockops(void);
587
588 /* swift.S */
589 extern void swift_flush_cache_all(void);
590 extern void swift_flush_cache_mm(struct mm_struct *mm);
591 extern void swift_flush_cache_range(struct vm_area_struct *vma,
592 unsigned long start, unsigned long end);
593 extern void swift_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
594 extern void swift_flush_page_to_ram(unsigned long page);
595 extern void swift_flush_page_for_dma(unsigned long page);
596 extern void swift_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
597 extern void swift_flush_tlb_all(void);
598 extern void swift_flush_tlb_mm(struct mm_struct *mm);
599 extern void swift_flush_tlb_range(struct vm_area_struct *vma,
600 unsigned long start, unsigned long end);
601 extern void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
602
603 #if 0 /* P3: deadwood to debug precise flushes on Swift. */
604 void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
605 {
606 int cctx, ctx1;
607
608 page &= PAGE_MASK;
609 if ((ctx1 = vma->vm_mm->context) != -1) {
610 cctx = srmmu_get_context();
611 /* Is context # ever different from current context? P3 */
612 if (cctx != ctx1) {
613 printk("flush ctx %02x curr %02x\n", ctx1, cctx);
614 srmmu_set_context(ctx1);
615 swift_flush_page(page);
616 __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
617 "r" (page), "i" (ASI_M_FLUSH_PROBE));
618 srmmu_set_context(cctx);
619 } else {
620 /* Rm. prot. bits from virt. c. */
621 /* swift_flush_cache_all(); */
622 /* swift_flush_cache_page(vma, page); */
623 swift_flush_page(page);
624
625 __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
626 "r" (page), "i" (ASI_M_FLUSH_PROBE));
627 /* same as above: srmmu_flush_tlb_page() */
628 }
629 }
630 }
631 #endif
632
633 /*
634 * The following are all MBUS based SRMMU modules, and therefore could
635 * be found in a multiprocessor configuration. On the whole, these
636 * chips seems to be much more touchy about DVMA and page tables
637 * with respect to cache coherency.
638 */
639
640 /* viking.S */
641 extern void viking_flush_cache_all(void);
642 extern void viking_flush_cache_mm(struct mm_struct *mm);
643 extern void viking_flush_cache_range(struct vm_area_struct *vma, unsigned long start,
644 unsigned long end);
645 extern void viking_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
646 extern void viking_flush_page_to_ram(unsigned long page);
647 extern void viking_flush_page_for_dma(unsigned long page);
648 extern void viking_flush_sig_insns(struct mm_struct *mm, unsigned long addr);
649 extern void viking_flush_page(unsigned long page);
650 extern void viking_mxcc_flush_page(unsigned long page);
651 extern void viking_flush_tlb_all(void);
652 extern void viking_flush_tlb_mm(struct mm_struct *mm);
653 extern void viking_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
654 unsigned long end);
655 extern void viking_flush_tlb_page(struct vm_area_struct *vma,
656 unsigned long page);
657 extern void sun4dsmp_flush_tlb_all(void);
658 extern void sun4dsmp_flush_tlb_mm(struct mm_struct *mm);
659 extern void sun4dsmp_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
660 unsigned long end);
661 extern void sun4dsmp_flush_tlb_page(struct vm_area_struct *vma,
662 unsigned long page);
663
664 /* hypersparc.S */
665 extern void hypersparc_flush_cache_all(void);
666 extern void hypersparc_flush_cache_mm(struct mm_struct *mm);
667 extern void hypersparc_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
668 extern void hypersparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
669 extern void hypersparc_flush_page_to_ram(unsigned long page);
670 extern void hypersparc_flush_page_for_dma(unsigned long page);
671 extern void hypersparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
672 extern void hypersparc_flush_tlb_all(void);
673 extern void hypersparc_flush_tlb_mm(struct mm_struct *mm);
674 extern void hypersparc_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
675 extern void hypersparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
676 extern void hypersparc_setup_blockops(void);
677
678 /*
679 * NOTE: All of this startup code assumes the low 16mb (approx.) of
680 * kernel mappings are done with one single contiguous chunk of
681 * ram. On small ram machines (classics mainly) we only get
682 * around 8mb mapped for us.
683 */
684
early_pgtable_allocfail(char * type)685 static void __init early_pgtable_allocfail(char *type)
686 {
687 prom_printf("inherit_prom_mappings: Cannot alloc kernel %s.\n", type);
688 prom_halt();
689 }
690
srmmu_early_allocate_ptable_skeleton(unsigned long start,unsigned long end)691 static void __init srmmu_early_allocate_ptable_skeleton(unsigned long start,
692 unsigned long end)
693 {
694 pgd_t *pgdp;
695 pmd_t *pmdp;
696 pte_t *ptep;
697
698 while (start < end) {
699 pgdp = pgd_offset_k(start);
700 if (pgd_none(*(pgd_t *)__nocache_fix(pgdp))) {
701 pmdp = __srmmu_get_nocache(
702 SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
703 if (pmdp == NULL)
704 early_pgtable_allocfail("pmd");
705 memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE);
706 pgd_set(__nocache_fix(pgdp), pmdp);
707 }
708 pmdp = pmd_offset(__nocache_fix(pgdp), start);
709 if (srmmu_pmd_none(*(pmd_t *)__nocache_fix(pmdp))) {
710 ptep = __srmmu_get_nocache(PTE_SIZE, PTE_SIZE);
711 if (ptep == NULL)
712 early_pgtable_allocfail("pte");
713 memset(__nocache_fix(ptep), 0, PTE_SIZE);
714 pmd_set(__nocache_fix(pmdp), ptep);
715 }
716 if (start > (0xffffffffUL - PMD_SIZE))
717 break;
718 start = (start + PMD_SIZE) & PMD_MASK;
719 }
720 }
721
srmmu_allocate_ptable_skeleton(unsigned long start,unsigned long end)722 static void __init srmmu_allocate_ptable_skeleton(unsigned long start,
723 unsigned long end)
724 {
725 pgd_t *pgdp;
726 pmd_t *pmdp;
727 pte_t *ptep;
728
729 while (start < end) {
730 pgdp = pgd_offset_k(start);
731 if (pgd_none(*pgdp)) {
732 pmdp = __srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
733 if (pmdp == NULL)
734 early_pgtable_allocfail("pmd");
735 memset(pmdp, 0, SRMMU_PMD_TABLE_SIZE);
736 pgd_set(pgdp, pmdp);
737 }
738 pmdp = pmd_offset(pgdp, start);
739 if (srmmu_pmd_none(*pmdp)) {
740 ptep = __srmmu_get_nocache(PTE_SIZE,
741 PTE_SIZE);
742 if (ptep == NULL)
743 early_pgtable_allocfail("pte");
744 memset(ptep, 0, PTE_SIZE);
745 pmd_set(pmdp, ptep);
746 }
747 if (start > (0xffffffffUL - PMD_SIZE))
748 break;
749 start = (start + PMD_SIZE) & PMD_MASK;
750 }
751 }
752
753 /* These flush types are not available on all chips... */
srmmu_probe(unsigned long vaddr)754 static inline unsigned long srmmu_probe(unsigned long vaddr)
755 {
756 unsigned long retval;
757
758 if (sparc_cpu_model != sparc_leon) {
759
760 vaddr &= PAGE_MASK;
761 __asm__ __volatile__("lda [%1] %2, %0\n\t" :
762 "=r" (retval) :
763 "r" (vaddr | 0x400), "i" (ASI_M_FLUSH_PROBE));
764 } else {
765 retval = leon_swprobe(vaddr, NULL);
766 }
767 return retval;
768 }
769
770 /*
771 * This is much cleaner than poking around physical address space
772 * looking at the prom's page table directly which is what most
773 * other OS's do. Yuck... this is much better.
774 */
srmmu_inherit_prom_mappings(unsigned long start,unsigned long end)775 static void __init srmmu_inherit_prom_mappings(unsigned long start,
776 unsigned long end)
777 {
778 unsigned long probed;
779 unsigned long addr;
780 pgd_t *pgdp;
781 pmd_t *pmdp;
782 pte_t *ptep;
783 int what; /* 0 = normal-pte, 1 = pmd-level pte, 2 = pgd-level pte */
784
785 while (start <= end) {
786 if (start == 0)
787 break; /* probably wrap around */
788 if (start == 0xfef00000)
789 start = KADB_DEBUGGER_BEGVM;
790 probed = srmmu_probe(start);
791 if (!probed) {
792 /* continue probing until we find an entry */
793 start += PAGE_SIZE;
794 continue;
795 }
796
797 /* A red snapper, see what it really is. */
798 what = 0;
799 addr = start - PAGE_SIZE;
800
801 if (!(start & ~(SRMMU_REAL_PMD_MASK))) {
802 if (srmmu_probe(addr + SRMMU_REAL_PMD_SIZE) == probed)
803 what = 1;
804 }
805
806 if (!(start & ~(SRMMU_PGDIR_MASK))) {
807 if (srmmu_probe(addr + SRMMU_PGDIR_SIZE) == probed)
808 what = 2;
809 }
810
811 pgdp = pgd_offset_k(start);
812 if (what == 2) {
813 *(pgd_t *)__nocache_fix(pgdp) = __pgd(probed);
814 start += SRMMU_PGDIR_SIZE;
815 continue;
816 }
817 if (pgd_none(*(pgd_t *)__nocache_fix(pgdp))) {
818 pmdp = __srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE,
819 SRMMU_PMD_TABLE_SIZE);
820 if (pmdp == NULL)
821 early_pgtable_allocfail("pmd");
822 memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE);
823 pgd_set(__nocache_fix(pgdp), pmdp);
824 }
825 pmdp = pmd_offset(__nocache_fix(pgdp), start);
826 if (srmmu_pmd_none(*(pmd_t *)__nocache_fix(pmdp))) {
827 ptep = __srmmu_get_nocache(PTE_SIZE, PTE_SIZE);
828 if (ptep == NULL)
829 early_pgtable_allocfail("pte");
830 memset(__nocache_fix(ptep), 0, PTE_SIZE);
831 pmd_set(__nocache_fix(pmdp), ptep);
832 }
833 if (what == 1) {
834 /* We bend the rule where all 16 PTPs in a pmd_t point
835 * inside the same PTE page, and we leak a perfectly
836 * good hardware PTE piece. Alternatives seem worse.
837 */
838 unsigned int x; /* Index of HW PMD in soft cluster */
839 unsigned long *val;
840 x = (start >> PMD_SHIFT) & 15;
841 val = &pmdp->pmdv[x];
842 *(unsigned long *)__nocache_fix(val) = probed;
843 start += SRMMU_REAL_PMD_SIZE;
844 continue;
845 }
846 ptep = pte_offset_kernel(__nocache_fix(pmdp), start);
847 *(pte_t *)__nocache_fix(ptep) = __pte(probed);
848 start += PAGE_SIZE;
849 }
850 }
851
852 #define KERNEL_PTE(page_shifted) ((page_shifted)|SRMMU_CACHE|SRMMU_PRIV|SRMMU_VALID)
853
854 /* Create a third-level SRMMU 16MB page mapping. */
do_large_mapping(unsigned long vaddr,unsigned long phys_base)855 static void __init do_large_mapping(unsigned long vaddr, unsigned long phys_base)
856 {
857 pgd_t *pgdp = pgd_offset_k(vaddr);
858 unsigned long big_pte;
859
860 big_pte = KERNEL_PTE(phys_base >> 4);
861 *(pgd_t *)__nocache_fix(pgdp) = __pgd(big_pte);
862 }
863
864 /* Map sp_bank entry SP_ENTRY, starting at virtual address VBASE. */
map_spbank(unsigned long vbase,int sp_entry)865 static unsigned long __init map_spbank(unsigned long vbase, int sp_entry)
866 {
867 unsigned long pstart = (sp_banks[sp_entry].base_addr & SRMMU_PGDIR_MASK);
868 unsigned long vstart = (vbase & SRMMU_PGDIR_MASK);
869 unsigned long vend = SRMMU_PGDIR_ALIGN(vbase + sp_banks[sp_entry].num_bytes);
870 /* Map "low" memory only */
871 const unsigned long min_vaddr = PAGE_OFFSET;
872 const unsigned long max_vaddr = PAGE_OFFSET + SRMMU_MAXMEM;
873
874 if (vstart < min_vaddr || vstart >= max_vaddr)
875 return vstart;
876
877 if (vend > max_vaddr || vend < min_vaddr)
878 vend = max_vaddr;
879
880 while (vstart < vend) {
881 do_large_mapping(vstart, pstart);
882 vstart += SRMMU_PGDIR_SIZE; pstart += SRMMU_PGDIR_SIZE;
883 }
884 return vstart;
885 }
886
map_kernel(void)887 static void __init map_kernel(void)
888 {
889 int i;
890
891 if (phys_base > 0) {
892 do_large_mapping(PAGE_OFFSET, phys_base);
893 }
894
895 for (i = 0; sp_banks[i].num_bytes != 0; i++) {
896 map_spbank((unsigned long)__va(sp_banks[i].base_addr), i);
897 }
898 }
899
900 void (*poke_srmmu)(void) = NULL;
901
srmmu_paging_init(void)902 void __init srmmu_paging_init(void)
903 {
904 int i;
905 phandle cpunode;
906 char node_str[128];
907 pgd_t *pgd;
908 pmd_t *pmd;
909 pte_t *pte;
910 unsigned long pages_avail;
911
912 init_mm.context = (unsigned long) NO_CONTEXT;
913 sparc_iomap.start = SUN4M_IOBASE_VADDR; /* 16MB of IOSPACE on all sun4m's. */
914
915 if (sparc_cpu_model == sun4d)
916 num_contexts = 65536; /* We know it is Viking */
917 else {
918 /* Find the number of contexts on the srmmu. */
919 cpunode = prom_getchild(prom_root_node);
920 num_contexts = 0;
921 while (cpunode != 0) {
922 prom_getstring(cpunode, "device_type", node_str, sizeof(node_str));
923 if (!strcmp(node_str, "cpu")) {
924 num_contexts = prom_getintdefault(cpunode, "mmu-nctx", 0x8);
925 break;
926 }
927 cpunode = prom_getsibling(cpunode);
928 }
929 }
930
931 if (!num_contexts) {
932 prom_printf("Something wrong, can't find cpu node in paging_init.\n");
933 prom_halt();
934 }
935
936 pages_avail = 0;
937 last_valid_pfn = bootmem_init(&pages_avail);
938
939 srmmu_nocache_calcsize();
940 srmmu_nocache_init();
941 srmmu_inherit_prom_mappings(0xfe400000, (LINUX_OPPROM_ENDVM - PAGE_SIZE));
942 map_kernel();
943
944 /* ctx table has to be physically aligned to its size */
945 srmmu_context_table = __srmmu_get_nocache(num_contexts * sizeof(ctxd_t), num_contexts * sizeof(ctxd_t));
946 srmmu_ctx_table_phys = (ctxd_t *)__nocache_pa(srmmu_context_table);
947
948 for (i = 0; i < num_contexts; i++)
949 srmmu_ctxd_set((ctxd_t *)__nocache_fix(&srmmu_context_table[i]), srmmu_swapper_pg_dir);
950
951 flush_cache_all();
952 srmmu_set_ctable_ptr((unsigned long)srmmu_ctx_table_phys);
953 #ifdef CONFIG_SMP
954 /* Stop from hanging here... */
955 local_ops->tlb_all();
956 #else
957 flush_tlb_all();
958 #endif
959 poke_srmmu();
960
961 srmmu_allocate_ptable_skeleton(sparc_iomap.start, IOBASE_END);
962 srmmu_allocate_ptable_skeleton(DVMA_VADDR, DVMA_END);
963
964 srmmu_allocate_ptable_skeleton(
965 __fix_to_virt(__end_of_fixed_addresses - 1), FIXADDR_TOP);
966 srmmu_allocate_ptable_skeleton(PKMAP_BASE, PKMAP_END);
967
968 pgd = pgd_offset_k(PKMAP_BASE);
969 pmd = pmd_offset(pgd, PKMAP_BASE);
970 pte = pte_offset_kernel(pmd, PKMAP_BASE);
971 pkmap_page_table = pte;
972
973 flush_cache_all();
974 flush_tlb_all();
975
976 sparc_context_init(num_contexts);
977
978 kmap_init();
979
980 {
981 unsigned long zones_size[MAX_NR_ZONES];
982 unsigned long zholes_size[MAX_NR_ZONES];
983 unsigned long npages;
984 int znum;
985
986 for (znum = 0; znum < MAX_NR_ZONES; znum++)
987 zones_size[znum] = zholes_size[znum] = 0;
988
989 npages = max_low_pfn - pfn_base;
990
991 zones_size[ZONE_DMA] = npages;
992 zholes_size[ZONE_DMA] = npages - pages_avail;
993
994 npages = highend_pfn - max_low_pfn;
995 zones_size[ZONE_HIGHMEM] = npages;
996 zholes_size[ZONE_HIGHMEM] = npages - calc_highpages();
997
998 free_area_init_node(0, zones_size, pfn_base, zholes_size);
999 }
1000 }
1001
mmu_info(struct seq_file * m)1002 void mmu_info(struct seq_file *m)
1003 {
1004 seq_printf(m,
1005 "MMU type\t: %s\n"
1006 "contexts\t: %d\n"
1007 "nocache total\t: %ld\n"
1008 "nocache used\t: %d\n",
1009 srmmu_name,
1010 num_contexts,
1011 srmmu_nocache_size,
1012 srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT);
1013 }
1014
init_new_context(struct task_struct * tsk,struct mm_struct * mm)1015 int init_new_context(struct task_struct *tsk, struct mm_struct *mm)
1016 {
1017 mm->context = NO_CONTEXT;
1018 return 0;
1019 }
1020
destroy_context(struct mm_struct * mm)1021 void destroy_context(struct mm_struct *mm)
1022 {
1023 unsigned long flags;
1024
1025 if (mm->context != NO_CONTEXT) {
1026 flush_cache_mm(mm);
1027 srmmu_ctxd_set(&srmmu_context_table[mm->context], srmmu_swapper_pg_dir);
1028 flush_tlb_mm(mm);
1029 spin_lock_irqsave(&srmmu_context_spinlock, flags);
1030 free_context(mm->context);
1031 spin_unlock_irqrestore(&srmmu_context_spinlock, flags);
1032 mm->context = NO_CONTEXT;
1033 }
1034 }
1035
1036 /* Init various srmmu chip types. */
srmmu_is_bad(void)1037 static void __init srmmu_is_bad(void)
1038 {
1039 prom_printf("Could not determine SRMMU chip type.\n");
1040 prom_halt();
1041 }
1042
init_vac_layout(void)1043 static void __init init_vac_layout(void)
1044 {
1045 phandle nd;
1046 int cache_lines;
1047 char node_str[128];
1048 #ifdef CONFIG_SMP
1049 int cpu = 0;
1050 unsigned long max_size = 0;
1051 unsigned long min_line_size = 0x10000000;
1052 #endif
1053
1054 nd = prom_getchild(prom_root_node);
1055 while ((nd = prom_getsibling(nd)) != 0) {
1056 prom_getstring(nd, "device_type", node_str, sizeof(node_str));
1057 if (!strcmp(node_str, "cpu")) {
1058 vac_line_size = prom_getint(nd, "cache-line-size");
1059 if (vac_line_size == -1) {
1060 prom_printf("can't determine cache-line-size, halting.\n");
1061 prom_halt();
1062 }
1063 cache_lines = prom_getint(nd, "cache-nlines");
1064 if (cache_lines == -1) {
1065 prom_printf("can't determine cache-nlines, halting.\n");
1066 prom_halt();
1067 }
1068
1069 vac_cache_size = cache_lines * vac_line_size;
1070 #ifdef CONFIG_SMP
1071 if (vac_cache_size > max_size)
1072 max_size = vac_cache_size;
1073 if (vac_line_size < min_line_size)
1074 min_line_size = vac_line_size;
1075 //FIXME: cpus not contiguous!!
1076 cpu++;
1077 if (cpu >= nr_cpu_ids || !cpu_online(cpu))
1078 break;
1079 #else
1080 break;
1081 #endif
1082 }
1083 }
1084 if (nd == 0) {
1085 prom_printf("No CPU nodes found, halting.\n");
1086 prom_halt();
1087 }
1088 #ifdef CONFIG_SMP
1089 vac_cache_size = max_size;
1090 vac_line_size = min_line_size;
1091 #endif
1092 printk("SRMMU: Using VAC size of %d bytes, line size %d bytes.\n",
1093 (int)vac_cache_size, (int)vac_line_size);
1094 }
1095
poke_hypersparc(void)1096 static void poke_hypersparc(void)
1097 {
1098 volatile unsigned long clear;
1099 unsigned long mreg = srmmu_get_mmureg();
1100
1101 hyper_flush_unconditional_combined();
1102
1103 mreg &= ~(HYPERSPARC_CWENABLE);
1104 mreg |= (HYPERSPARC_CENABLE | HYPERSPARC_WBENABLE);
1105 mreg |= (HYPERSPARC_CMODE);
1106
1107 srmmu_set_mmureg(mreg);
1108
1109 #if 0 /* XXX I think this is bad news... -DaveM */
1110 hyper_clear_all_tags();
1111 #endif
1112
1113 put_ross_icr(HYPERSPARC_ICCR_FTD | HYPERSPARC_ICCR_ICE);
1114 hyper_flush_whole_icache();
1115 clear = srmmu_get_faddr();
1116 clear = srmmu_get_fstatus();
1117 }
1118
1119 static const struct sparc32_cachetlb_ops hypersparc_ops = {
1120 .cache_all = hypersparc_flush_cache_all,
1121 .cache_mm = hypersparc_flush_cache_mm,
1122 .cache_page = hypersparc_flush_cache_page,
1123 .cache_range = hypersparc_flush_cache_range,
1124 .tlb_all = hypersparc_flush_tlb_all,
1125 .tlb_mm = hypersparc_flush_tlb_mm,
1126 .tlb_page = hypersparc_flush_tlb_page,
1127 .tlb_range = hypersparc_flush_tlb_range,
1128 .page_to_ram = hypersparc_flush_page_to_ram,
1129 .sig_insns = hypersparc_flush_sig_insns,
1130 .page_for_dma = hypersparc_flush_page_for_dma,
1131 };
1132
init_hypersparc(void)1133 static void __init init_hypersparc(void)
1134 {
1135 srmmu_name = "ROSS HyperSparc";
1136 srmmu_modtype = HyperSparc;
1137
1138 init_vac_layout();
1139
1140 is_hypersparc = 1;
1141 sparc32_cachetlb_ops = &hypersparc_ops;
1142
1143 poke_srmmu = poke_hypersparc;
1144
1145 hypersparc_setup_blockops();
1146 }
1147
poke_swift(void)1148 static void poke_swift(void)
1149 {
1150 unsigned long mreg;
1151
1152 /* Clear any crap from the cache or else... */
1153 swift_flush_cache_all();
1154
1155 /* Enable I & D caches */
1156 mreg = srmmu_get_mmureg();
1157 mreg |= (SWIFT_IE | SWIFT_DE);
1158 /*
1159 * The Swift branch folding logic is completely broken. At
1160 * trap time, if things are just right, if can mistakenly
1161 * think that a trap is coming from kernel mode when in fact
1162 * it is coming from user mode (it mis-executes the branch in
1163 * the trap code). So you see things like crashme completely
1164 * hosing your machine which is completely unacceptable. Turn
1165 * this shit off... nice job Fujitsu.
1166 */
1167 mreg &= ~(SWIFT_BF);
1168 srmmu_set_mmureg(mreg);
1169 }
1170
1171 static const struct sparc32_cachetlb_ops swift_ops = {
1172 .cache_all = swift_flush_cache_all,
1173 .cache_mm = swift_flush_cache_mm,
1174 .cache_page = swift_flush_cache_page,
1175 .cache_range = swift_flush_cache_range,
1176 .tlb_all = swift_flush_tlb_all,
1177 .tlb_mm = swift_flush_tlb_mm,
1178 .tlb_page = swift_flush_tlb_page,
1179 .tlb_range = swift_flush_tlb_range,
1180 .page_to_ram = swift_flush_page_to_ram,
1181 .sig_insns = swift_flush_sig_insns,
1182 .page_for_dma = swift_flush_page_for_dma,
1183 };
1184
1185 #define SWIFT_MASKID_ADDR 0x10003018
init_swift(void)1186 static void __init init_swift(void)
1187 {
1188 unsigned long swift_rev;
1189
1190 __asm__ __volatile__("lda [%1] %2, %0\n\t"
1191 "srl %0, 0x18, %0\n\t" :
1192 "=r" (swift_rev) :
1193 "r" (SWIFT_MASKID_ADDR), "i" (ASI_M_BYPASS));
1194 srmmu_name = "Fujitsu Swift";
1195 switch (swift_rev) {
1196 case 0x11:
1197 case 0x20:
1198 case 0x23:
1199 case 0x30:
1200 srmmu_modtype = Swift_lots_o_bugs;
1201 hwbug_bitmask |= (HWBUG_KERN_ACCBROKEN | HWBUG_KERN_CBITBROKEN);
1202 /*
1203 * Gee george, I wonder why Sun is so hush hush about
1204 * this hardware bug... really braindamage stuff going
1205 * on here. However I think we can find a way to avoid
1206 * all of the workaround overhead under Linux. Basically,
1207 * any page fault can cause kernel pages to become user
1208 * accessible (the mmu gets confused and clears some of
1209 * the ACC bits in kernel ptes). Aha, sounds pretty
1210 * horrible eh? But wait, after extensive testing it appears
1211 * that if you use pgd_t level large kernel pte's (like the
1212 * 4MB pages on the Pentium) the bug does not get tripped
1213 * at all. This avoids almost all of the major overhead.
1214 * Welcome to a world where your vendor tells you to,
1215 * "apply this kernel patch" instead of "sorry for the
1216 * broken hardware, send it back and we'll give you
1217 * properly functioning parts"
1218 */
1219 break;
1220 case 0x25:
1221 case 0x31:
1222 srmmu_modtype = Swift_bad_c;
1223 hwbug_bitmask |= HWBUG_KERN_CBITBROKEN;
1224 /*
1225 * You see Sun allude to this hardware bug but never
1226 * admit things directly, they'll say things like,
1227 * "the Swift chip cache problems" or similar.
1228 */
1229 break;
1230 default:
1231 srmmu_modtype = Swift_ok;
1232 break;
1233 }
1234
1235 sparc32_cachetlb_ops = &swift_ops;
1236 flush_page_for_dma_global = 0;
1237
1238 /*
1239 * Are you now convinced that the Swift is one of the
1240 * biggest VLSI abortions of all time? Bravo Fujitsu!
1241 * Fujitsu, the !#?!%$'d up processor people. I bet if
1242 * you examined the microcode of the Swift you'd find
1243 * XXX's all over the place.
1244 */
1245 poke_srmmu = poke_swift;
1246 }
1247
turbosparc_flush_cache_all(void)1248 static void turbosparc_flush_cache_all(void)
1249 {
1250 flush_user_windows();
1251 turbosparc_idflash_clear();
1252 }
1253
turbosparc_flush_cache_mm(struct mm_struct * mm)1254 static void turbosparc_flush_cache_mm(struct mm_struct *mm)
1255 {
1256 FLUSH_BEGIN(mm)
1257 flush_user_windows();
1258 turbosparc_idflash_clear();
1259 FLUSH_END
1260 }
1261
turbosparc_flush_cache_range(struct vm_area_struct * vma,unsigned long start,unsigned long end)1262 static void turbosparc_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
1263 {
1264 FLUSH_BEGIN(vma->vm_mm)
1265 flush_user_windows();
1266 turbosparc_idflash_clear();
1267 FLUSH_END
1268 }
1269
turbosparc_flush_cache_page(struct vm_area_struct * vma,unsigned long page)1270 static void turbosparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page)
1271 {
1272 FLUSH_BEGIN(vma->vm_mm)
1273 flush_user_windows();
1274 if (vma->vm_flags & VM_EXEC)
1275 turbosparc_flush_icache();
1276 turbosparc_flush_dcache();
1277 FLUSH_END
1278 }
1279
1280 /* TurboSparc is copy-back, if we turn it on, but this does not work. */
turbosparc_flush_page_to_ram(unsigned long page)1281 static void turbosparc_flush_page_to_ram(unsigned long page)
1282 {
1283 #ifdef TURBOSPARC_WRITEBACK
1284 volatile unsigned long clear;
1285
1286 if (srmmu_probe(page))
1287 turbosparc_flush_page_cache(page);
1288 clear = srmmu_get_fstatus();
1289 #endif
1290 }
1291
turbosparc_flush_sig_insns(struct mm_struct * mm,unsigned long insn_addr)1292 static void turbosparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr)
1293 {
1294 }
1295
turbosparc_flush_page_for_dma(unsigned long page)1296 static void turbosparc_flush_page_for_dma(unsigned long page)
1297 {
1298 turbosparc_flush_dcache();
1299 }
1300
turbosparc_flush_tlb_all(void)1301 static void turbosparc_flush_tlb_all(void)
1302 {
1303 srmmu_flush_whole_tlb();
1304 }
1305
turbosparc_flush_tlb_mm(struct mm_struct * mm)1306 static void turbosparc_flush_tlb_mm(struct mm_struct *mm)
1307 {
1308 FLUSH_BEGIN(mm)
1309 srmmu_flush_whole_tlb();
1310 FLUSH_END
1311 }
1312
turbosparc_flush_tlb_range(struct vm_area_struct * vma,unsigned long start,unsigned long end)1313 static void turbosparc_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
1314 {
1315 FLUSH_BEGIN(vma->vm_mm)
1316 srmmu_flush_whole_tlb();
1317 FLUSH_END
1318 }
1319
turbosparc_flush_tlb_page(struct vm_area_struct * vma,unsigned long page)1320 static void turbosparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
1321 {
1322 FLUSH_BEGIN(vma->vm_mm)
1323 srmmu_flush_whole_tlb();
1324 FLUSH_END
1325 }
1326
1327
poke_turbosparc(void)1328 static void poke_turbosparc(void)
1329 {
1330 unsigned long mreg = srmmu_get_mmureg();
1331 unsigned long ccreg;
1332
1333 /* Clear any crap from the cache or else... */
1334 turbosparc_flush_cache_all();
1335 /* Temporarily disable I & D caches */
1336 mreg &= ~(TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE);
1337 mreg &= ~(TURBOSPARC_PCENABLE); /* Don't check parity */
1338 srmmu_set_mmureg(mreg);
1339
1340 ccreg = turbosparc_get_ccreg();
1341
1342 #ifdef TURBOSPARC_WRITEBACK
1343 ccreg |= (TURBOSPARC_SNENABLE); /* Do DVMA snooping in Dcache */
1344 ccreg &= ~(TURBOSPARC_uS2 | TURBOSPARC_WTENABLE);
1345 /* Write-back D-cache, emulate VLSI
1346 * abortion number three, not number one */
1347 #else
1348 /* For now let's play safe, optimize later */
1349 ccreg |= (TURBOSPARC_SNENABLE | TURBOSPARC_WTENABLE);
1350 /* Do DVMA snooping in Dcache, Write-thru D-cache */
1351 ccreg &= ~(TURBOSPARC_uS2);
1352 /* Emulate VLSI abortion number three, not number one */
1353 #endif
1354
1355 switch (ccreg & 7) {
1356 case 0: /* No SE cache */
1357 case 7: /* Test mode */
1358 break;
1359 default:
1360 ccreg |= (TURBOSPARC_SCENABLE);
1361 }
1362 turbosparc_set_ccreg(ccreg);
1363
1364 mreg |= (TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE); /* I & D caches on */
1365 mreg |= (TURBOSPARC_ICSNOOP); /* Icache snooping on */
1366 srmmu_set_mmureg(mreg);
1367 }
1368
1369 static const struct sparc32_cachetlb_ops turbosparc_ops = {
1370 .cache_all = turbosparc_flush_cache_all,
1371 .cache_mm = turbosparc_flush_cache_mm,
1372 .cache_page = turbosparc_flush_cache_page,
1373 .cache_range = turbosparc_flush_cache_range,
1374 .tlb_all = turbosparc_flush_tlb_all,
1375 .tlb_mm = turbosparc_flush_tlb_mm,
1376 .tlb_page = turbosparc_flush_tlb_page,
1377 .tlb_range = turbosparc_flush_tlb_range,
1378 .page_to_ram = turbosparc_flush_page_to_ram,
1379 .sig_insns = turbosparc_flush_sig_insns,
1380 .page_for_dma = turbosparc_flush_page_for_dma,
1381 };
1382
init_turbosparc(void)1383 static void __init init_turbosparc(void)
1384 {
1385 srmmu_name = "Fujitsu TurboSparc";
1386 srmmu_modtype = TurboSparc;
1387 sparc32_cachetlb_ops = &turbosparc_ops;
1388 poke_srmmu = poke_turbosparc;
1389 }
1390
poke_tsunami(void)1391 static void poke_tsunami(void)
1392 {
1393 unsigned long mreg = srmmu_get_mmureg();
1394
1395 tsunami_flush_icache();
1396 tsunami_flush_dcache();
1397 mreg &= ~TSUNAMI_ITD;
1398 mreg |= (TSUNAMI_IENAB | TSUNAMI_DENAB);
1399 srmmu_set_mmureg(mreg);
1400 }
1401
1402 static const struct sparc32_cachetlb_ops tsunami_ops = {
1403 .cache_all = tsunami_flush_cache_all,
1404 .cache_mm = tsunami_flush_cache_mm,
1405 .cache_page = tsunami_flush_cache_page,
1406 .cache_range = tsunami_flush_cache_range,
1407 .tlb_all = tsunami_flush_tlb_all,
1408 .tlb_mm = tsunami_flush_tlb_mm,
1409 .tlb_page = tsunami_flush_tlb_page,
1410 .tlb_range = tsunami_flush_tlb_range,
1411 .page_to_ram = tsunami_flush_page_to_ram,
1412 .sig_insns = tsunami_flush_sig_insns,
1413 .page_for_dma = tsunami_flush_page_for_dma,
1414 };
1415
init_tsunami(void)1416 static void __init init_tsunami(void)
1417 {
1418 /*
1419 * Tsunami's pretty sane, Sun and TI actually got it
1420 * somewhat right this time. Fujitsu should have
1421 * taken some lessons from them.
1422 */
1423
1424 srmmu_name = "TI Tsunami";
1425 srmmu_modtype = Tsunami;
1426 sparc32_cachetlb_ops = &tsunami_ops;
1427 poke_srmmu = poke_tsunami;
1428
1429 tsunami_setup_blockops();
1430 }
1431
poke_viking(void)1432 static void poke_viking(void)
1433 {
1434 unsigned long mreg = srmmu_get_mmureg();
1435 static int smp_catch;
1436
1437 if (viking_mxcc_present) {
1438 unsigned long mxcc_control = mxcc_get_creg();
1439
1440 mxcc_control |= (MXCC_CTL_ECE | MXCC_CTL_PRE | MXCC_CTL_MCE);
1441 mxcc_control &= ~(MXCC_CTL_RRC);
1442 mxcc_set_creg(mxcc_control);
1443
1444 /*
1445 * We don't need memory parity checks.
1446 * XXX This is a mess, have to dig out later. ecd.
1447 viking_mxcc_turn_off_parity(&mreg, &mxcc_control);
1448 */
1449
1450 /* We do cache ptables on MXCC. */
1451 mreg |= VIKING_TCENABLE;
1452 } else {
1453 unsigned long bpreg;
1454
1455 mreg &= ~(VIKING_TCENABLE);
1456 if (smp_catch++) {
1457 /* Must disable mixed-cmd mode here for other cpu's. */
1458 bpreg = viking_get_bpreg();
1459 bpreg &= ~(VIKING_ACTION_MIX);
1460 viking_set_bpreg(bpreg);
1461
1462 /* Just in case PROM does something funny. */
1463 msi_set_sync();
1464 }
1465 }
1466
1467 mreg |= VIKING_SPENABLE;
1468 mreg |= (VIKING_ICENABLE | VIKING_DCENABLE);
1469 mreg |= VIKING_SBENABLE;
1470 mreg &= ~(VIKING_ACENABLE);
1471 srmmu_set_mmureg(mreg);
1472 }
1473
1474 static struct sparc32_cachetlb_ops viking_ops __ro_after_init = {
1475 .cache_all = viking_flush_cache_all,
1476 .cache_mm = viking_flush_cache_mm,
1477 .cache_page = viking_flush_cache_page,
1478 .cache_range = viking_flush_cache_range,
1479 .tlb_all = viking_flush_tlb_all,
1480 .tlb_mm = viking_flush_tlb_mm,
1481 .tlb_page = viking_flush_tlb_page,
1482 .tlb_range = viking_flush_tlb_range,
1483 .page_to_ram = viking_flush_page_to_ram,
1484 .sig_insns = viking_flush_sig_insns,
1485 .page_for_dma = viking_flush_page_for_dma,
1486 };
1487
1488 #ifdef CONFIG_SMP
1489 /* On sun4d the cpu broadcasts local TLB flushes, so we can just
1490 * perform the local TLB flush and all the other cpus will see it.
1491 * But, unfortunately, there is a bug in the sun4d XBUS backplane
1492 * that requires that we add some synchronization to these flushes.
1493 *
1494 * The bug is that the fifo which keeps track of all the pending TLB
1495 * broadcasts in the system is an entry or two too small, so if we
1496 * have too many going at once we'll overflow that fifo and lose a TLB
1497 * flush resulting in corruption.
1498 *
1499 * Our workaround is to take a global spinlock around the TLB flushes,
1500 * which guarentees we won't ever have too many pending. It's a big
1501 * hammer, but a semaphore like system to make sure we only have N TLB
1502 * flushes going at once will require SMP locking anyways so there's
1503 * no real value in trying any harder than this.
1504 */
1505 static struct sparc32_cachetlb_ops viking_sun4d_smp_ops __ro_after_init = {
1506 .cache_all = viking_flush_cache_all,
1507 .cache_mm = viking_flush_cache_mm,
1508 .cache_page = viking_flush_cache_page,
1509 .cache_range = viking_flush_cache_range,
1510 .tlb_all = sun4dsmp_flush_tlb_all,
1511 .tlb_mm = sun4dsmp_flush_tlb_mm,
1512 .tlb_page = sun4dsmp_flush_tlb_page,
1513 .tlb_range = sun4dsmp_flush_tlb_range,
1514 .page_to_ram = viking_flush_page_to_ram,
1515 .sig_insns = viking_flush_sig_insns,
1516 .page_for_dma = viking_flush_page_for_dma,
1517 };
1518 #endif
1519
init_viking(void)1520 static void __init init_viking(void)
1521 {
1522 unsigned long mreg = srmmu_get_mmureg();
1523
1524 /* Ahhh, the viking. SRMMU VLSI abortion number two... */
1525 if (mreg & VIKING_MMODE) {
1526 srmmu_name = "TI Viking";
1527 viking_mxcc_present = 0;
1528 msi_set_sync();
1529
1530 /*
1531 * We need this to make sure old viking takes no hits
1532 * on it's cache for dma snoops to workaround the
1533 * "load from non-cacheable memory" interrupt bug.
1534 * This is only necessary because of the new way in
1535 * which we use the IOMMU.
1536 */
1537 viking_ops.page_for_dma = viking_flush_page;
1538 #ifdef CONFIG_SMP
1539 viking_sun4d_smp_ops.page_for_dma = viking_flush_page;
1540 #endif
1541 flush_page_for_dma_global = 0;
1542 } else {
1543 srmmu_name = "TI Viking/MXCC";
1544 viking_mxcc_present = 1;
1545 srmmu_cache_pagetables = 1;
1546 }
1547
1548 sparc32_cachetlb_ops = (const struct sparc32_cachetlb_ops *)
1549 &viking_ops;
1550 #ifdef CONFIG_SMP
1551 if (sparc_cpu_model == sun4d)
1552 sparc32_cachetlb_ops = (const struct sparc32_cachetlb_ops *)
1553 &viking_sun4d_smp_ops;
1554 #endif
1555
1556 poke_srmmu = poke_viking;
1557 }
1558
1559 /* Probe for the srmmu chip version. */
get_srmmu_type(void)1560 static void __init get_srmmu_type(void)
1561 {
1562 unsigned long mreg, psr;
1563 unsigned long mod_typ, mod_rev, psr_typ, psr_vers;
1564
1565 srmmu_modtype = SRMMU_INVAL_MOD;
1566 hwbug_bitmask = 0;
1567
1568 mreg = srmmu_get_mmureg(); psr = get_psr();
1569 mod_typ = (mreg & 0xf0000000) >> 28;
1570 mod_rev = (mreg & 0x0f000000) >> 24;
1571 psr_typ = (psr >> 28) & 0xf;
1572 psr_vers = (psr >> 24) & 0xf;
1573
1574 /* First, check for sparc-leon. */
1575 if (sparc_cpu_model == sparc_leon) {
1576 init_leon();
1577 return;
1578 }
1579
1580 /* Second, check for HyperSparc or Cypress. */
1581 if (mod_typ == 1) {
1582 switch (mod_rev) {
1583 case 7:
1584 /* UP or MP Hypersparc */
1585 init_hypersparc();
1586 break;
1587 case 0:
1588 case 2:
1589 case 10:
1590 case 11:
1591 case 12:
1592 case 13:
1593 case 14:
1594 case 15:
1595 default:
1596 prom_printf("Sparc-Linux Cypress support does not longer exit.\n");
1597 prom_halt();
1598 break;
1599 }
1600 return;
1601 }
1602
1603 /* Now Fujitsu TurboSparc. It might happen that it is
1604 * in Swift emulation mode, so we will check later...
1605 */
1606 if (psr_typ == 0 && psr_vers == 5) {
1607 init_turbosparc();
1608 return;
1609 }
1610
1611 /* Next check for Fujitsu Swift. */
1612 if (psr_typ == 0 && psr_vers == 4) {
1613 phandle cpunode;
1614 char node_str[128];
1615
1616 /* Look if it is not a TurboSparc emulating Swift... */
1617 cpunode = prom_getchild(prom_root_node);
1618 while ((cpunode = prom_getsibling(cpunode)) != 0) {
1619 prom_getstring(cpunode, "device_type", node_str, sizeof(node_str));
1620 if (!strcmp(node_str, "cpu")) {
1621 if (!prom_getintdefault(cpunode, "psr-implementation", 1) &&
1622 prom_getintdefault(cpunode, "psr-version", 1) == 5) {
1623 init_turbosparc();
1624 return;
1625 }
1626 break;
1627 }
1628 }
1629
1630 init_swift();
1631 return;
1632 }
1633
1634 /* Now the Viking family of srmmu. */
1635 if (psr_typ == 4 &&
1636 ((psr_vers == 0) ||
1637 ((psr_vers == 1) && (mod_typ == 0) && (mod_rev == 0)))) {
1638 init_viking();
1639 return;
1640 }
1641
1642 /* Finally the Tsunami. */
1643 if (psr_typ == 4 && psr_vers == 1 && (mod_typ || mod_rev)) {
1644 init_tsunami();
1645 return;
1646 }
1647
1648 /* Oh well */
1649 srmmu_is_bad();
1650 }
1651
1652 #ifdef CONFIG_SMP
1653 /* Local cross-calls. */
smp_flush_page_for_dma(unsigned long page)1654 static void smp_flush_page_for_dma(unsigned long page)
1655 {
1656 xc1((smpfunc_t) local_ops->page_for_dma, page);
1657 local_ops->page_for_dma(page);
1658 }
1659
smp_flush_cache_all(void)1660 static void smp_flush_cache_all(void)
1661 {
1662 xc0((smpfunc_t) local_ops->cache_all);
1663 local_ops->cache_all();
1664 }
1665
smp_flush_tlb_all(void)1666 static void smp_flush_tlb_all(void)
1667 {
1668 xc0((smpfunc_t) local_ops->tlb_all);
1669 local_ops->tlb_all();
1670 }
1671
smp_flush_cache_mm(struct mm_struct * mm)1672 static void smp_flush_cache_mm(struct mm_struct *mm)
1673 {
1674 if (mm->context != NO_CONTEXT) {
1675 cpumask_t cpu_mask;
1676 cpumask_copy(&cpu_mask, mm_cpumask(mm));
1677 cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1678 if (!cpumask_empty(&cpu_mask))
1679 xc1((smpfunc_t) local_ops->cache_mm, (unsigned long) mm);
1680 local_ops->cache_mm(mm);
1681 }
1682 }
1683
smp_flush_tlb_mm(struct mm_struct * mm)1684 static void smp_flush_tlb_mm(struct mm_struct *mm)
1685 {
1686 if (mm->context != NO_CONTEXT) {
1687 cpumask_t cpu_mask;
1688 cpumask_copy(&cpu_mask, mm_cpumask(mm));
1689 cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1690 if (!cpumask_empty(&cpu_mask)) {
1691 xc1((smpfunc_t) local_ops->tlb_mm, (unsigned long) mm);
1692 if (atomic_read(&mm->mm_users) == 1 && current->active_mm == mm)
1693 cpumask_copy(mm_cpumask(mm),
1694 cpumask_of(smp_processor_id()));
1695 }
1696 local_ops->tlb_mm(mm);
1697 }
1698 }
1699
smp_flush_cache_range(struct vm_area_struct * vma,unsigned long start,unsigned long end)1700 static void smp_flush_cache_range(struct vm_area_struct *vma,
1701 unsigned long start,
1702 unsigned long end)
1703 {
1704 struct mm_struct *mm = vma->vm_mm;
1705
1706 if (mm->context != NO_CONTEXT) {
1707 cpumask_t cpu_mask;
1708 cpumask_copy(&cpu_mask, mm_cpumask(mm));
1709 cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1710 if (!cpumask_empty(&cpu_mask))
1711 xc3((smpfunc_t) local_ops->cache_range,
1712 (unsigned long) vma, start, end);
1713 local_ops->cache_range(vma, start, end);
1714 }
1715 }
1716
smp_flush_tlb_range(struct vm_area_struct * vma,unsigned long start,unsigned long end)1717 static void smp_flush_tlb_range(struct vm_area_struct *vma,
1718 unsigned long start,
1719 unsigned long end)
1720 {
1721 struct mm_struct *mm = vma->vm_mm;
1722
1723 if (mm->context != NO_CONTEXT) {
1724 cpumask_t cpu_mask;
1725 cpumask_copy(&cpu_mask, mm_cpumask(mm));
1726 cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1727 if (!cpumask_empty(&cpu_mask))
1728 xc3((smpfunc_t) local_ops->tlb_range,
1729 (unsigned long) vma, start, end);
1730 local_ops->tlb_range(vma, start, end);
1731 }
1732 }
1733
smp_flush_cache_page(struct vm_area_struct * vma,unsigned long page)1734 static void smp_flush_cache_page(struct vm_area_struct *vma, unsigned long page)
1735 {
1736 struct mm_struct *mm = vma->vm_mm;
1737
1738 if (mm->context != NO_CONTEXT) {
1739 cpumask_t cpu_mask;
1740 cpumask_copy(&cpu_mask, mm_cpumask(mm));
1741 cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1742 if (!cpumask_empty(&cpu_mask))
1743 xc2((smpfunc_t) local_ops->cache_page,
1744 (unsigned long) vma, page);
1745 local_ops->cache_page(vma, page);
1746 }
1747 }
1748
smp_flush_tlb_page(struct vm_area_struct * vma,unsigned long page)1749 static void smp_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
1750 {
1751 struct mm_struct *mm = vma->vm_mm;
1752
1753 if (mm->context != NO_CONTEXT) {
1754 cpumask_t cpu_mask;
1755 cpumask_copy(&cpu_mask, mm_cpumask(mm));
1756 cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1757 if (!cpumask_empty(&cpu_mask))
1758 xc2((smpfunc_t) local_ops->tlb_page,
1759 (unsigned long) vma, page);
1760 local_ops->tlb_page(vma, page);
1761 }
1762 }
1763
smp_flush_page_to_ram(unsigned long page)1764 static void smp_flush_page_to_ram(unsigned long page)
1765 {
1766 /* Current theory is that those who call this are the one's
1767 * who have just dirtied their cache with the pages contents
1768 * in kernel space, therefore we only run this on local cpu.
1769 *
1770 * XXX This experiment failed, research further... -DaveM
1771 */
1772 #if 1
1773 xc1((smpfunc_t) local_ops->page_to_ram, page);
1774 #endif
1775 local_ops->page_to_ram(page);
1776 }
1777
smp_flush_sig_insns(struct mm_struct * mm,unsigned long insn_addr)1778 static void smp_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr)
1779 {
1780 cpumask_t cpu_mask;
1781 cpumask_copy(&cpu_mask, mm_cpumask(mm));
1782 cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
1783 if (!cpumask_empty(&cpu_mask))
1784 xc2((smpfunc_t) local_ops->sig_insns,
1785 (unsigned long) mm, insn_addr);
1786 local_ops->sig_insns(mm, insn_addr);
1787 }
1788
1789 static struct sparc32_cachetlb_ops smp_cachetlb_ops __ro_after_init = {
1790 .cache_all = smp_flush_cache_all,
1791 .cache_mm = smp_flush_cache_mm,
1792 .cache_page = smp_flush_cache_page,
1793 .cache_range = smp_flush_cache_range,
1794 .tlb_all = smp_flush_tlb_all,
1795 .tlb_mm = smp_flush_tlb_mm,
1796 .tlb_page = smp_flush_tlb_page,
1797 .tlb_range = smp_flush_tlb_range,
1798 .page_to_ram = smp_flush_page_to_ram,
1799 .sig_insns = smp_flush_sig_insns,
1800 .page_for_dma = smp_flush_page_for_dma,
1801 };
1802 #endif
1803
1804 /* Load up routines and constants for sun4m and sun4d mmu */
load_mmu(void)1805 void __init load_mmu(void)
1806 {
1807 /* Functions */
1808 get_srmmu_type();
1809
1810 #ifdef CONFIG_SMP
1811 /* El switcheroo... */
1812 local_ops = sparc32_cachetlb_ops;
1813
1814 if (sparc_cpu_model == sun4d || sparc_cpu_model == sparc_leon) {
1815 smp_cachetlb_ops.tlb_all = local_ops->tlb_all;
1816 smp_cachetlb_ops.tlb_mm = local_ops->tlb_mm;
1817 smp_cachetlb_ops.tlb_range = local_ops->tlb_range;
1818 smp_cachetlb_ops.tlb_page = local_ops->tlb_page;
1819 }
1820
1821 if (poke_srmmu == poke_viking) {
1822 /* Avoid unnecessary cross calls. */
1823 smp_cachetlb_ops.cache_all = local_ops->cache_all;
1824 smp_cachetlb_ops.cache_mm = local_ops->cache_mm;
1825 smp_cachetlb_ops.cache_range = local_ops->cache_range;
1826 smp_cachetlb_ops.cache_page = local_ops->cache_page;
1827
1828 smp_cachetlb_ops.page_to_ram = local_ops->page_to_ram;
1829 smp_cachetlb_ops.sig_insns = local_ops->sig_insns;
1830 smp_cachetlb_ops.page_for_dma = local_ops->page_for_dma;
1831 }
1832
1833 /* It really is const after this point. */
1834 sparc32_cachetlb_ops = (const struct sparc32_cachetlb_ops *)
1835 &smp_cachetlb_ops;
1836 #endif
1837
1838 if (sparc_cpu_model == sun4d)
1839 ld_mmu_iounit();
1840 else
1841 ld_mmu_iommu();
1842 #ifdef CONFIG_SMP
1843 if (sparc_cpu_model == sun4d)
1844 sun4d_init_smp();
1845 else if (sparc_cpu_model == sparc_leon)
1846 leon_init_smp();
1847 else
1848 sun4m_init_smp();
1849 #endif
1850 }
1851