1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 *
4 * Copyright (C) 2011-2012 John Crispin <john@phrozen.org>
5 * Copyright (C) 2013-2015 Lantiq Beteiligungs-GmbH & Co.KG
6 */
7
8 #include <linux/ioport.h>
9 #include <linux/export.h>
10 #include <linux/clkdev.h>
11 #include <linux/spinlock.h>
12 #include <linux/of.h>
13 #include <linux/of_platform.h>
14 #include <linux/of_address.h>
15
16 #include <lantiq_soc.h>
17
18 #include "../clk.h"
19 #include "../prom.h"
20
21 /* clock control register for legacy */
22 #define CGU_IFCCR 0x0018
23 #define CGU_IFCCR_VR9 0x0024
24 /* system clock register for legacy */
25 #define CGU_SYS 0x0010
26 /* pci control register */
27 #define CGU_PCICR 0x0034
28 #define CGU_PCICR_VR9 0x0038
29 /* ephy configuration register */
30 #define CGU_EPHY 0x10
31
32 /* Legacy PMU register for ar9, ase, danube */
33 /* power control register */
34 #define PMU_PWDCR 0x1C
35 /* power status register */
36 #define PMU_PWDSR 0x20
37 /* power control register */
38 #define PMU_PWDCR1 0x24
39 /* power status register */
40 #define PMU_PWDSR1 0x28
41 /* power control register */
42 #define PWDCR(x) ((x) ? (PMU_PWDCR1) : (PMU_PWDCR))
43 /* power status register */
44 #define PWDSR(x) ((x) ? (PMU_PWDSR1) : (PMU_PWDSR))
45
46
47 /* PMU register for ar10 and grx390 */
48
49 /* First register set */
50 #define PMU_CLK_SR 0x20 /* status */
51 #define PMU_CLK_CR_A 0x24 /* Enable */
52 #define PMU_CLK_CR_B 0x28 /* Disable */
53 /* Second register set */
54 #define PMU_CLK_SR1 0x30 /* status */
55 #define PMU_CLK_CR1_A 0x34 /* Enable */
56 #define PMU_CLK_CR1_B 0x38 /* Disable */
57 /* Third register set */
58 #define PMU_ANA_SR 0x40 /* status */
59 #define PMU_ANA_CR_A 0x44 /* Enable */
60 #define PMU_ANA_CR_B 0x48 /* Disable */
61
62 /* Status */
63 static u32 pmu_clk_sr[] = {
64 PMU_CLK_SR,
65 PMU_CLK_SR1,
66 PMU_ANA_SR,
67 };
68
69 /* Enable */
70 static u32 pmu_clk_cr_a[] = {
71 PMU_CLK_CR_A,
72 PMU_CLK_CR1_A,
73 PMU_ANA_CR_A,
74 };
75
76 /* Disable */
77 static u32 pmu_clk_cr_b[] = {
78 PMU_CLK_CR_B,
79 PMU_CLK_CR1_B,
80 PMU_ANA_CR_B,
81 };
82
83 #define PWDCR_EN_XRX(x) (pmu_clk_cr_a[(x)])
84 #define PWDCR_DIS_XRX(x) (pmu_clk_cr_b[(x)])
85 #define PWDSR_XRX(x) (pmu_clk_sr[(x)])
86
87 /* clock gates that we can en/disable */
88 #define PMU_USB0_P BIT(0)
89 #define PMU_ASE_SDIO BIT(2) /* ASE special */
90 #define PMU_PCI BIT(4)
91 #define PMU_DMA BIT(5)
92 #define PMU_USB0 BIT(6)
93 #define PMU_ASC0 BIT(7)
94 #define PMU_EPHY BIT(7) /* ase */
95 #define PMU_USIF BIT(7) /* from vr9 until grx390 */
96 #define PMU_SPI BIT(8)
97 #define PMU_DFE BIT(9)
98 #define PMU_EBU BIT(10)
99 #define PMU_STP BIT(11)
100 #define PMU_GPT BIT(12)
101 #define PMU_AHBS BIT(13) /* vr9 */
102 #define PMU_FPI BIT(14)
103 #define PMU_AHBM BIT(15)
104 #define PMU_SDIO BIT(16) /* danube, ar9, vr9 */
105 #define PMU_ASC1 BIT(17)
106 #define PMU_PPE_QSB BIT(18)
107 #define PMU_PPE_SLL01 BIT(19)
108 #define PMU_DEU BIT(20)
109 #define PMU_PPE_TC BIT(21)
110 #define PMU_PPE_EMA BIT(22)
111 #define PMU_PPE_DPLUM BIT(23)
112 #define PMU_PPE_DP BIT(23)
113 #define PMU_PPE_DPLUS BIT(24)
114 #define PMU_USB1_P BIT(26)
115 #define PMU_USB1 BIT(27)
116 #define PMU_SWITCH BIT(28)
117 #define PMU_PPE_TOP BIT(29)
118 #define PMU_GPHY BIT(30)
119 #define PMU_PCIE_CLK BIT(31)
120
121 #define PMU1_PCIE_PHY BIT(0) /* vr9-specific,moved in ar10/grx390 */
122 #define PMU1_PCIE_CTL BIT(1)
123 #define PMU1_PCIE_PDI BIT(4)
124 #define PMU1_PCIE_MSI BIT(5)
125 #define PMU1_CKE BIT(6)
126 #define PMU1_PCIE1_CTL BIT(17)
127 #define PMU1_PCIE1_PDI BIT(20)
128 #define PMU1_PCIE1_MSI BIT(21)
129 #define PMU1_PCIE2_CTL BIT(25)
130 #define PMU1_PCIE2_PDI BIT(26)
131 #define PMU1_PCIE2_MSI BIT(27)
132
133 #define PMU_ANALOG_USB0_P BIT(0)
134 #define PMU_ANALOG_USB1_P BIT(1)
135 #define PMU_ANALOG_PCIE0_P BIT(8)
136 #define PMU_ANALOG_PCIE1_P BIT(9)
137 #define PMU_ANALOG_PCIE2_P BIT(10)
138 #define PMU_ANALOG_DSL_AFE BIT(16)
139 #define PMU_ANALOG_DCDC_2V5 BIT(17)
140 #define PMU_ANALOG_DCDC_1VX BIT(18)
141 #define PMU_ANALOG_DCDC_1V0 BIT(19)
142
143 #define pmu_w32(x, y) ltq_w32((x), pmu_membase + (y))
144 #define pmu_r32(x) ltq_r32(pmu_membase + (x))
145
146 static void __iomem *pmu_membase;
147 void __iomem *ltq_cgu_membase;
148 void __iomem *ltq_ebu_membase;
149
150 static u32 ifccr = CGU_IFCCR;
151 static u32 pcicr = CGU_PCICR;
152
153 static DEFINE_SPINLOCK(g_pmu_lock);
154
155 /* legacy function kept alive to ease clkdev transition */
ltq_pmu_enable(unsigned int module)156 void ltq_pmu_enable(unsigned int module)
157 {
158 int retry = 1000000;
159
160 spin_lock(&g_pmu_lock);
161 pmu_w32(pmu_r32(PMU_PWDCR) & ~module, PMU_PWDCR);
162 do {} while (--retry && (pmu_r32(PMU_PWDSR) & module));
163 spin_unlock(&g_pmu_lock);
164
165 if (!retry)
166 panic("activating PMU module failed!");
167 }
168 EXPORT_SYMBOL(ltq_pmu_enable);
169
170 /* legacy function kept alive to ease clkdev transition */
ltq_pmu_disable(unsigned int module)171 void ltq_pmu_disable(unsigned int module)
172 {
173 int retry = 1000000;
174
175 spin_lock(&g_pmu_lock);
176 pmu_w32(pmu_r32(PMU_PWDCR) | module, PMU_PWDCR);
177 do {} while (--retry && (!(pmu_r32(PMU_PWDSR) & module)));
178 spin_unlock(&g_pmu_lock);
179
180 if (!retry)
181 pr_warn("deactivating PMU module failed!");
182 }
183 EXPORT_SYMBOL(ltq_pmu_disable);
184
185 /* enable a hw clock */
cgu_enable(struct clk * clk)186 static int cgu_enable(struct clk *clk)
187 {
188 ltq_cgu_w32(ltq_cgu_r32(ifccr) | clk->bits, ifccr);
189 return 0;
190 }
191
192 /* disable a hw clock */
cgu_disable(struct clk * clk)193 static void cgu_disable(struct clk *clk)
194 {
195 ltq_cgu_w32(ltq_cgu_r32(ifccr) & ~clk->bits, ifccr);
196 }
197
198 /* enable a clock gate */
pmu_enable(struct clk * clk)199 static int pmu_enable(struct clk *clk)
200 {
201 int retry = 1000000;
202
203 if (of_machine_is_compatible("lantiq,ar10")
204 || of_machine_is_compatible("lantiq,grx390")) {
205 pmu_w32(clk->bits, PWDCR_EN_XRX(clk->module));
206 do {} while (--retry &&
207 (!(pmu_r32(PWDSR_XRX(clk->module)) & clk->bits)));
208
209 } else {
210 spin_lock(&g_pmu_lock);
211 pmu_w32(pmu_r32(PWDCR(clk->module)) & ~clk->bits,
212 PWDCR(clk->module));
213 do {} while (--retry &&
214 (pmu_r32(PWDSR(clk->module)) & clk->bits));
215 spin_unlock(&g_pmu_lock);
216 }
217
218 if (!retry)
219 panic("activating PMU module failed!");
220
221 return 0;
222 }
223
224 /* disable a clock gate */
pmu_disable(struct clk * clk)225 static void pmu_disable(struct clk *clk)
226 {
227 int retry = 1000000;
228
229 if (of_machine_is_compatible("lantiq,ar10")
230 || of_machine_is_compatible("lantiq,grx390")) {
231 pmu_w32(clk->bits, PWDCR_DIS_XRX(clk->module));
232 do {} while (--retry &&
233 (pmu_r32(PWDSR_XRX(clk->module)) & clk->bits));
234 } else {
235 spin_lock(&g_pmu_lock);
236 pmu_w32(pmu_r32(PWDCR(clk->module)) | clk->bits,
237 PWDCR(clk->module));
238 do {} while (--retry &&
239 (!(pmu_r32(PWDSR(clk->module)) & clk->bits)));
240 spin_unlock(&g_pmu_lock);
241 }
242
243 if (!retry)
244 pr_warn("deactivating PMU module failed!");
245 }
246
247 /* the pci enable helper */
pci_enable(struct clk * clk)248 static int pci_enable(struct clk *clk)
249 {
250 unsigned int val = ltq_cgu_r32(ifccr);
251 /* set bus clock speed */
252 if (of_machine_is_compatible("lantiq,ar9") ||
253 of_machine_is_compatible("lantiq,vr9")) {
254 val &= ~0x1f00000;
255 if (clk->rate == CLOCK_33M)
256 val |= 0xe00000;
257 else
258 val |= 0x700000; /* 62.5M */
259 } else {
260 val &= ~0xf00000;
261 if (clk->rate == CLOCK_33M)
262 val |= 0x800000;
263 else
264 val |= 0x400000; /* 62.5M */
265 }
266 ltq_cgu_w32(val, ifccr);
267 pmu_enable(clk);
268 return 0;
269 }
270
271 /* enable the external clock as a source */
pci_ext_enable(struct clk * clk)272 static int pci_ext_enable(struct clk *clk)
273 {
274 ltq_cgu_w32(ltq_cgu_r32(ifccr) & ~(1 << 16), ifccr);
275 ltq_cgu_w32((1 << 30), pcicr);
276 return 0;
277 }
278
279 /* disable the external clock as a source */
pci_ext_disable(struct clk * clk)280 static void pci_ext_disable(struct clk *clk)
281 {
282 ltq_cgu_w32(ltq_cgu_r32(ifccr) | (1 << 16), ifccr);
283 ltq_cgu_w32((1 << 31) | (1 << 30), pcicr);
284 }
285
286 /* enable a clockout source */
clkout_enable(struct clk * clk)287 static int clkout_enable(struct clk *clk)
288 {
289 int i;
290
291 /* get the correct rate */
292 for (i = 0; i < 4; i++) {
293 if (clk->rates[i] == clk->rate) {
294 int shift = 14 - (2 * clk->module);
295 int enable = 7 - clk->module;
296 unsigned int val = ltq_cgu_r32(ifccr);
297
298 val &= ~(3 << shift);
299 val |= i << shift;
300 val |= enable;
301 ltq_cgu_w32(val, ifccr);
302 return 0;
303 }
304 }
305 return -1;
306 }
307
308 /* manage the clock gates via PMU */
clkdev_add_pmu(const char * dev,const char * con,bool deactivate,unsigned int module,unsigned int bits)309 static void clkdev_add_pmu(const char *dev, const char *con, bool deactivate,
310 unsigned int module, unsigned int bits)
311 {
312 struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
313
314 if (!clk)
315 return;
316 clk->cl.dev_id = dev;
317 clk->cl.con_id = con;
318 clk->cl.clk = clk;
319 clk->enable = pmu_enable;
320 clk->disable = pmu_disable;
321 clk->module = module;
322 clk->bits = bits;
323 if (deactivate) {
324 /*
325 * Disable it during the initialization. Module should enable
326 * when used
327 */
328 pmu_disable(clk);
329 }
330 clkdev_add(&clk->cl);
331 }
332
333 /* manage the clock generator */
clkdev_add_cgu(const char * dev,const char * con,unsigned int bits)334 static void clkdev_add_cgu(const char *dev, const char *con,
335 unsigned int bits)
336 {
337 struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
338
339 if (!clk)
340 return;
341 clk->cl.dev_id = dev;
342 clk->cl.con_id = con;
343 clk->cl.clk = clk;
344 clk->enable = cgu_enable;
345 clk->disable = cgu_disable;
346 clk->bits = bits;
347 clkdev_add(&clk->cl);
348 }
349
350 /* pci needs its own enable function as the setup is a bit more complex */
351 static unsigned long valid_pci_rates[] = {CLOCK_33M, CLOCK_62_5M, 0};
352
clkdev_add_pci(void)353 static void clkdev_add_pci(void)
354 {
355 struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
356 struct clk *clk_ext = kzalloc(sizeof(struct clk), GFP_KERNEL);
357
358 /* main pci clock */
359 if (clk) {
360 clk->cl.dev_id = "17000000.pci";
361 clk->cl.con_id = NULL;
362 clk->cl.clk = clk;
363 clk->rate = CLOCK_33M;
364 clk->rates = valid_pci_rates;
365 clk->enable = pci_enable;
366 clk->disable = pmu_disable;
367 clk->module = 0;
368 clk->bits = PMU_PCI;
369 clkdev_add(&clk->cl);
370 }
371
372 /* use internal/external bus clock */
373 if (clk_ext) {
374 clk_ext->cl.dev_id = "17000000.pci";
375 clk_ext->cl.con_id = "external";
376 clk_ext->cl.clk = clk_ext;
377 clk_ext->enable = pci_ext_enable;
378 clk_ext->disable = pci_ext_disable;
379 clkdev_add(&clk_ext->cl);
380 }
381 }
382
383 /* xway socs can generate clocks on gpio pins */
384 static unsigned long valid_clkout_rates[4][5] = {
385 {CLOCK_32_768K, CLOCK_1_536M, CLOCK_2_5M, CLOCK_12M, 0},
386 {CLOCK_40M, CLOCK_12M, CLOCK_24M, CLOCK_48M, 0},
387 {CLOCK_25M, CLOCK_40M, CLOCK_30M, CLOCK_60M, 0},
388 {CLOCK_12M, CLOCK_50M, CLOCK_32_768K, CLOCK_25M, 0},
389 };
390
clkdev_add_clkout(void)391 static void clkdev_add_clkout(void)
392 {
393 int i;
394
395 for (i = 0; i < 4; i++) {
396 struct clk *clk;
397 char *name;
398
399 name = kzalloc(sizeof("clkout0"), GFP_KERNEL);
400 if (!name)
401 continue;
402 sprintf(name, "clkout%d", i);
403
404 clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
405 if (!clk) {
406 kfree(name);
407 continue;
408 }
409 clk->cl.dev_id = "1f103000.cgu";
410 clk->cl.con_id = name;
411 clk->cl.clk = clk;
412 clk->rate = 0;
413 clk->rates = valid_clkout_rates[i];
414 clk->enable = clkout_enable;
415 clk->module = i;
416 clkdev_add(&clk->cl);
417 }
418 }
419
420 /* bring up all register ranges that we need for basic system control */
ltq_soc_init(void)421 void __init ltq_soc_init(void)
422 {
423 struct resource res_pmu, res_cgu, res_ebu;
424 struct device_node *np_pmu =
425 of_find_compatible_node(NULL, NULL, "lantiq,pmu-xway");
426 struct device_node *np_cgu =
427 of_find_compatible_node(NULL, NULL, "lantiq,cgu-xway");
428 struct device_node *np_ebu =
429 of_find_compatible_node(NULL, NULL, "lantiq,ebu-xway");
430
431 /* check if all the core register ranges are available */
432 if (!np_pmu || !np_cgu || !np_ebu)
433 panic("Failed to load core nodes from devicetree");
434
435 if (of_address_to_resource(np_pmu, 0, &res_pmu) ||
436 of_address_to_resource(np_cgu, 0, &res_cgu) ||
437 of_address_to_resource(np_ebu, 0, &res_ebu))
438 panic("Failed to get core resources");
439
440 if (!request_mem_region(res_pmu.start, resource_size(&res_pmu),
441 res_pmu.name) ||
442 !request_mem_region(res_cgu.start, resource_size(&res_cgu),
443 res_cgu.name) ||
444 !request_mem_region(res_ebu.start, resource_size(&res_ebu),
445 res_ebu.name))
446 pr_err("Failed to request core resources");
447
448 pmu_membase = ioremap_nocache(res_pmu.start, resource_size(&res_pmu));
449 ltq_cgu_membase = ioremap_nocache(res_cgu.start,
450 resource_size(&res_cgu));
451 ltq_ebu_membase = ioremap_nocache(res_ebu.start,
452 resource_size(&res_ebu));
453 if (!pmu_membase || !ltq_cgu_membase || !ltq_ebu_membase)
454 panic("Failed to remap core resources");
455
456 /* make sure to unprotect the memory region where flash is located */
457 ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0);
458
459 /* add our generic xway clocks */
460 clkdev_add_pmu("10000000.fpi", NULL, 0, 0, PMU_FPI);
461 clkdev_add_pmu("1e100a00.gptu", NULL, 1, 0, PMU_GPT);
462 clkdev_add_pmu("1e100bb0.stp", NULL, 1, 0, PMU_STP);
463 clkdev_add_pmu("1e100c00.serial", NULL, 0, 0, PMU_ASC1);
464 clkdev_add_pmu("1e104100.dma", NULL, 1, 0, PMU_DMA);
465 clkdev_add_pmu("1e100800.spi", NULL, 1, 0, PMU_SPI);
466 clkdev_add_pmu("1e105300.ebu", NULL, 0, 0, PMU_EBU);
467 clkdev_add_clkout();
468
469 /* add the soc dependent clocks */
470 if (of_machine_is_compatible("lantiq,vr9")) {
471 ifccr = CGU_IFCCR_VR9;
472 pcicr = CGU_PCICR_VR9;
473 } else {
474 clkdev_add_pmu("1e180000.etop", NULL, 1, 0, PMU_PPE);
475 }
476
477 if (!of_machine_is_compatible("lantiq,ase"))
478 clkdev_add_pci();
479
480 if (of_machine_is_compatible("lantiq,grx390") ||
481 of_machine_is_compatible("lantiq,ar10")) {
482 clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 2, PMU_ANALOG_USB0_P);
483 clkdev_add_pmu("1f203034.usb2-phy", "phy", 1, 2, PMU_ANALOG_USB1_P);
484 /* rc 0 */
485 clkdev_add_pmu("1f106800.phy", "phy", 1, 2, PMU_ANALOG_PCIE0_P);
486 clkdev_add_pmu("1d900000.pcie", "msi", 1, 1, PMU1_PCIE_MSI);
487 clkdev_add_pmu("1f106800.phy", "pdi", 1, 1, PMU1_PCIE_PDI);
488 clkdev_add_pmu("1d900000.pcie", "ctl", 1, 1, PMU1_PCIE_CTL);
489 /* rc 1 */
490 clkdev_add_pmu("1f700400.phy", "phy", 1, 2, PMU_ANALOG_PCIE1_P);
491 clkdev_add_pmu("19000000.pcie", "msi", 1, 1, PMU1_PCIE1_MSI);
492 clkdev_add_pmu("1f700400.phy", "pdi", 1, 1, PMU1_PCIE1_PDI);
493 clkdev_add_pmu("19000000.pcie", "ctl", 1, 1, PMU1_PCIE1_CTL);
494 }
495
496 if (of_machine_is_compatible("lantiq,ase")) {
497 if (ltq_cgu_r32(CGU_SYS) & (1 << 5))
498 clkdev_add_static(CLOCK_266M, CLOCK_133M,
499 CLOCK_133M, CLOCK_266M);
500 else
501 clkdev_add_static(CLOCK_133M, CLOCK_133M,
502 CLOCK_133M, CLOCK_133M);
503 clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0);
504 clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P);
505 clkdev_add_pmu("1e180000.etop", "ppe", 1, 0, PMU_PPE);
506 clkdev_add_cgu("1e180000.etop", "ephycgu", CGU_EPHY);
507 clkdev_add_pmu("1e180000.etop", "ephy", 1, 0, PMU_EPHY);
508 clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_ASE_SDIO);
509 clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
510 } else if (of_machine_is_compatible("lantiq,grx390")) {
511 clkdev_add_static(ltq_grx390_cpu_hz(), ltq_grx390_fpi_hz(),
512 ltq_grx390_fpi_hz(), ltq_grx390_pp32_hz());
513 clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0);
514 clkdev_add_pmu("1e106000.usb", "otg", 1, 0, PMU_USB1);
515 /* rc 2 */
516 clkdev_add_pmu("1f106a00.pcie", "phy", 1, 2, PMU_ANALOG_PCIE2_P);
517 clkdev_add_pmu("1a800000.pcie", "msi", 1, 1, PMU1_PCIE2_MSI);
518 clkdev_add_pmu("1f106a00.pcie", "pdi", 1, 1, PMU1_PCIE2_PDI);
519 clkdev_add_pmu("1a800000.pcie", "ctl", 1, 1, PMU1_PCIE2_CTL);
520 clkdev_add_pmu("1e10b308.eth", NULL, 0, 0, PMU_SWITCH | PMU_PPE_DP);
521 clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);
522 clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
523 } else if (of_machine_is_compatible("lantiq,ar10")) {
524 clkdev_add_static(ltq_ar10_cpu_hz(), ltq_ar10_fpi_hz(),
525 ltq_ar10_fpi_hz(), ltq_ar10_pp32_hz());
526 clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0);
527 clkdev_add_pmu("1e106000.usb", "otg", 1, 0, PMU_USB1);
528 clkdev_add_pmu("1e10b308.eth", NULL, 0, 0, PMU_SWITCH |
529 PMU_PPE_DP | PMU_PPE_TC);
530 clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);
531 clkdev_add_pmu("1e108000.switch", "gphy0", 0, 0, PMU_GPHY);
532 clkdev_add_pmu("1e108000.switch", "gphy1", 0, 0, PMU_GPHY);
533 clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
534 clkdev_add_pmu("1e116000.mei", "afe", 1, 2, PMU_ANALOG_DSL_AFE);
535 clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
536 } else if (of_machine_is_compatible("lantiq,vr9")) {
537 clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(),
538 ltq_vr9_fpi_hz(), ltq_vr9_pp32_hz());
539 clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P);
540 clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0 | PMU_AHBM);
541 clkdev_add_pmu("1f203034.usb2-phy", "phy", 1, 0, PMU_USB1_P);
542 clkdev_add_pmu("1e106000.usb", "otg", 1, 0, PMU_USB1 | PMU_AHBM);
543 clkdev_add_pmu("1f106800.phy", "phy", 1, 1, PMU1_PCIE_PHY);
544 clkdev_add_pmu("1d900000.pcie", "bus", 1, 0, PMU_PCIE_CLK);
545 clkdev_add_pmu("1d900000.pcie", "msi", 1, 1, PMU1_PCIE_MSI);
546 clkdev_add_pmu("1f106800.phy", "pdi", 1, 1, PMU1_PCIE_PDI);
547 clkdev_add_pmu("1d900000.pcie", "ctl", 1, 1, PMU1_PCIE_CTL);
548 clkdev_add_pmu(NULL, "ahb", 1, 0, PMU_AHBM | PMU_AHBS);
549
550 clkdev_add_pmu("1da00000.usif", "NULL", 1, 0, PMU_USIF);
551 clkdev_add_pmu("1e10b308.eth", NULL, 0, 0,
552 PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM |
553 PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |
554 PMU_PPE_QSB | PMU_PPE_TOP);
555 clkdev_add_pmu("1e108000.switch", "gphy0", 0, 0, PMU_GPHY);
556 clkdev_add_pmu("1e108000.switch", "gphy1", 0, 0, PMU_GPHY);
557 clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
558 clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
559 clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
560 } else if (of_machine_is_compatible("lantiq,ar9")) {
561 clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(),
562 ltq_ar9_fpi_hz(), CLOCK_250M);
563 clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P);
564 clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0 | PMU_AHBM);
565 clkdev_add_pmu("1f203034.usb2-phy", "phy", 1, 0, PMU_USB1_P);
566 clkdev_add_pmu("1e106000.usb", "otg", 1, 0, PMU_USB1 | PMU_AHBM);
567 clkdev_add_pmu("1e180000.etop", "switch", 1, 0, PMU_SWITCH);
568 clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
569 clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
570 clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
571 clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0);
572 } else {
573 clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(),
574 ltq_danube_fpi_hz(), ltq_danube_pp32_hz());
575 clkdev_add_pmu("1e101000.usb", "otg", 1, 0, PMU_USB0 | PMU_AHBM);
576 clkdev_add_pmu("1f203018.usb2-phy", "phy", 1, 0, PMU_USB0_P);
577 clkdev_add_pmu("1e103000.sdio", NULL, 1, 0, PMU_SDIO);
578 clkdev_add_pmu("1e103100.deu", NULL, 1, 0, PMU_DEU);
579 clkdev_add_pmu("1e116000.mei", "dfe", 1, 0, PMU_DFE);
580 clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0);
581 }
582 }
583