1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * linux/arch/arm/mach-mmp/time.c
4 *
5 * Support for clocksource and clockevents
6 *
7 * Copyright (C) 2008 Marvell International Ltd.
8 * All rights reserved.
9 *
10 * 2008-04-11: Jason Chagas <Jason.chagas@marvell.com>
11 * 2008-10-08: Bin Yang <bin.yang@marvell.com>
12 *
13 * The timers module actually includes three timers, each timer with up to
14 * three match comparators. Timer #0 is used here in free-running mode as
15 * the clock source, and match comparator #1 used as clock event device.
16 */
17
18 #include <linux/init.h>
19 #include <linux/kernel.h>
20 #include <linux/interrupt.h>
21 #include <linux/clockchips.h>
22 #include <linux/clk.h>
23
24 #include <linux/io.h>
25 #include <linux/irq.h>
26 #include <linux/of.h>
27 #include <linux/of_address.h>
28 #include <linux/of_irq.h>
29 #include <linux/sched_clock.h>
30 #include <asm/mach/time.h>
31
32 #include "addr-map.h"
33 #include "regs-timers.h"
34 #include "regs-apbc.h"
35 #include "irqs.h"
36 #include "cputype.h"
37 #include "clock.h"
38
39 #define TIMERS_VIRT_BASE TIMERS1_VIRT_BASE
40
41 #define MAX_DELTA (0xfffffffe)
42 #define MIN_DELTA (16)
43
44 static void __iomem *mmp_timer_base = TIMERS_VIRT_BASE;
45
46 /*
47 * Read the timer through the CVWR register. Delay is required after requesting
48 * a read. The CR register cannot be directly read due to metastability issues
49 * documented in the PXA168 software manual.
50 */
timer_read(void)51 static inline uint32_t timer_read(void)
52 {
53 uint32_t val;
54 int delay = 3;
55
56 __raw_writel(1, mmp_timer_base + TMR_CVWR(1));
57
58 while (delay--)
59 val = __raw_readl(mmp_timer_base + TMR_CVWR(1));
60
61 return val;
62 }
63
mmp_read_sched_clock(void)64 static u64 notrace mmp_read_sched_clock(void)
65 {
66 return timer_read();
67 }
68
timer_interrupt(int irq,void * dev_id)69 static irqreturn_t timer_interrupt(int irq, void *dev_id)
70 {
71 struct clock_event_device *c = dev_id;
72
73 /*
74 * Clear pending interrupt status.
75 */
76 __raw_writel(0x01, mmp_timer_base + TMR_ICR(0));
77
78 /*
79 * Disable timer 0.
80 */
81 __raw_writel(0x02, mmp_timer_base + TMR_CER);
82
83 c->event_handler(c);
84
85 return IRQ_HANDLED;
86 }
87
timer_set_next_event(unsigned long delta,struct clock_event_device * dev)88 static int timer_set_next_event(unsigned long delta,
89 struct clock_event_device *dev)
90 {
91 unsigned long flags;
92
93 local_irq_save(flags);
94
95 /*
96 * Disable timer 0.
97 */
98 __raw_writel(0x02, mmp_timer_base + TMR_CER);
99
100 /*
101 * Clear and enable timer match 0 interrupt.
102 */
103 __raw_writel(0x01, mmp_timer_base + TMR_ICR(0));
104 __raw_writel(0x01, mmp_timer_base + TMR_IER(0));
105
106 /*
107 * Setup new clockevent timer value.
108 */
109 __raw_writel(delta - 1, mmp_timer_base + TMR_TN_MM(0, 0));
110
111 /*
112 * Enable timer 0.
113 */
114 __raw_writel(0x03, mmp_timer_base + TMR_CER);
115
116 local_irq_restore(flags);
117
118 return 0;
119 }
120
timer_set_shutdown(struct clock_event_device * evt)121 static int timer_set_shutdown(struct clock_event_device *evt)
122 {
123 unsigned long flags;
124
125 local_irq_save(flags);
126 /* disable the matching interrupt */
127 __raw_writel(0x00, mmp_timer_base + TMR_IER(0));
128 local_irq_restore(flags);
129
130 return 0;
131 }
132
133 static struct clock_event_device ckevt = {
134 .name = "clockevent",
135 .features = CLOCK_EVT_FEAT_ONESHOT,
136 .rating = 200,
137 .set_next_event = timer_set_next_event,
138 .set_state_shutdown = timer_set_shutdown,
139 .set_state_oneshot = timer_set_shutdown,
140 };
141
clksrc_read(struct clocksource * cs)142 static u64 clksrc_read(struct clocksource *cs)
143 {
144 return timer_read();
145 }
146
147 static struct clocksource cksrc = {
148 .name = "clocksource",
149 .rating = 200,
150 .read = clksrc_read,
151 .mask = CLOCKSOURCE_MASK(32),
152 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
153 };
154
timer_config(void)155 static void __init timer_config(void)
156 {
157 uint32_t ccr = __raw_readl(mmp_timer_base + TMR_CCR);
158
159 __raw_writel(0x0, mmp_timer_base + TMR_CER); /* disable */
160
161 ccr &= (cpu_is_mmp2()) ? (TMR_CCR_CS_0(0) | TMR_CCR_CS_1(0)) :
162 (TMR_CCR_CS_0(3) | TMR_CCR_CS_1(3));
163 __raw_writel(ccr, mmp_timer_base + TMR_CCR);
164
165 /* set timer 0 to periodic mode, and timer 1 to free-running mode */
166 __raw_writel(0x2, mmp_timer_base + TMR_CMR);
167
168 __raw_writel(0x1, mmp_timer_base + TMR_PLCR(0)); /* periodic */
169 __raw_writel(0x7, mmp_timer_base + TMR_ICR(0)); /* clear status */
170 __raw_writel(0x0, mmp_timer_base + TMR_IER(0));
171
172 __raw_writel(0x0, mmp_timer_base + TMR_PLCR(1)); /* free-running */
173 __raw_writel(0x7, mmp_timer_base + TMR_ICR(1)); /* clear status */
174 __raw_writel(0x0, mmp_timer_base + TMR_IER(1));
175
176 /* enable timer 1 counter */
177 __raw_writel(0x2, mmp_timer_base + TMR_CER);
178 }
179
180 static struct irqaction timer_irq = {
181 .name = "timer",
182 .flags = IRQF_TIMER | IRQF_IRQPOLL,
183 .handler = timer_interrupt,
184 .dev_id = &ckevt,
185 };
186
mmp_timer_init(int irq,unsigned long rate)187 void __init mmp_timer_init(int irq, unsigned long rate)
188 {
189 timer_config();
190
191 sched_clock_register(mmp_read_sched_clock, 32, rate);
192
193 ckevt.cpumask = cpumask_of(0);
194
195 setup_irq(irq, &timer_irq);
196
197 clocksource_register_hz(&cksrc, rate);
198 clockevents_config_and_register(&ckevt, rate, MIN_DELTA, MAX_DELTA);
199 }
200
201 #ifdef CONFIG_OF
202 static const struct of_device_id mmp_timer_dt_ids[] = {
203 { .compatible = "mrvl,mmp-timer", },
204 {}
205 };
206
mmp_dt_init_timer(void)207 void __init mmp_dt_init_timer(void)
208 {
209 struct device_node *np;
210 struct clk *clk;
211 int irq, ret;
212 unsigned long rate;
213
214 np = of_find_matching_node(NULL, mmp_timer_dt_ids);
215 if (!np) {
216 ret = -ENODEV;
217 goto out;
218 }
219
220 clk = of_clk_get(np, 0);
221 if (!IS_ERR(clk)) {
222 ret = clk_prepare_enable(clk);
223 if (ret)
224 goto out;
225 rate = clk_get_rate(clk) / 2;
226 } else if (cpu_is_pj4()) {
227 rate = 6500000;
228 } else {
229 rate = 3250000;
230 }
231
232 irq = irq_of_parse_and_map(np, 0);
233 if (!irq) {
234 ret = -EINVAL;
235 goto out;
236 }
237 mmp_timer_base = of_iomap(np, 0);
238 if (!mmp_timer_base) {
239 ret = -ENOMEM;
240 goto out;
241 }
242 mmp_timer_init(irq, rate);
243 return;
244 out:
245 pr_err("Failed to get timer from device tree with error:%d\n", ret);
246 }
247 #endif
248