1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 *
4 * arch/xtensa/platform/xtavnet/setup.c
5 *
6 * ...
7 *
8 * Authors: Chris Zankel <chris@zankel.net>
9 * Joe Taylor <joe@tensilica.com>
10 *
11 * Copyright 2001 - 2006 Tensilica Inc.
12 */
13 #include <linux/stddef.h>
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/io.h>
17 #include <linux/errno.h>
18 #include <linux/reboot.h>
19 #include <linux/kdev_t.h>
20 #include <linux/types.h>
21 #include <linux/major.h>
22 #include <linux/console.h>
23 #include <linux/delay.h>
24 #include <linux/of.h>
25 #include <linux/clk-provider.h>
26 #include <linux/of_address.h>
27
28 #include <asm/timex.h>
29 #include <asm/processor.h>
30 #include <asm/platform.h>
31 #include <asm/bootparam.h>
32 #include <platform/lcd.h>
33 #include <platform/hardware.h>
34
platform_halt(void)35 void platform_halt(void)
36 {
37 lcd_disp_at_pos(" HALT ", 0);
38 local_irq_disable();
39 while (1)
40 cpu_relax();
41 }
42
platform_power_off(void)43 void platform_power_off(void)
44 {
45 lcd_disp_at_pos("POWEROFF", 0);
46 local_irq_disable();
47 while (1)
48 cpu_relax();
49 }
50
platform_restart(void)51 void platform_restart(void)
52 {
53 /* Try software reset first. */
54 WRITE_ONCE(*(u32 *)XTFPGA_SWRST_VADDR, 0xdead);
55
56 /* If software reset did not work, flush and reset the mmu,
57 * simulate a processor reset, and jump to the reset vector.
58 */
59 cpu_reset();
60 /* control never gets here */
61 }
62
platform_setup(char ** cmdline)63 void __init platform_setup(char **cmdline)
64 {
65 }
66
67 /* early initialization */
68
platform_init(bp_tag_t * first)69 void __init platform_init(bp_tag_t *first)
70 {
71 }
72
73 /* Heartbeat. */
74
platform_heartbeat(void)75 void platform_heartbeat(void)
76 {
77 }
78
79 #ifdef CONFIG_XTENSA_CALIBRATE_CCOUNT
80
platform_calibrate_ccount(void)81 void __init platform_calibrate_ccount(void)
82 {
83 ccount_freq = *(long *)XTFPGA_CLKFRQ_VADDR;
84 }
85
86 #endif
87
88 #ifdef CONFIG_USE_OF
89
xtfpga_clk_setup(struct device_node * np)90 static void __init xtfpga_clk_setup(struct device_node *np)
91 {
92 void __iomem *base = of_iomap(np, 0);
93 struct clk *clk;
94 u32 freq;
95
96 if (!base) {
97 pr_err("%pOFn: invalid address\n", np);
98 return;
99 }
100
101 freq = __raw_readl(base);
102 iounmap(base);
103 clk = clk_register_fixed_rate(NULL, np->name, NULL, 0, freq);
104
105 if (IS_ERR(clk)) {
106 pr_err("%pOFn: clk registration failed\n", np);
107 return;
108 }
109
110 if (of_clk_add_provider(np, of_clk_src_simple_get, clk)) {
111 pr_err("%pOFn: clk provider registration failed\n", np);
112 return;
113 }
114 }
115 CLK_OF_DECLARE(xtfpga_clk, "cdns,xtfpga-clock", xtfpga_clk_setup);
116
117 #define MAC_LEN 6
update_local_mac(struct device_node * node)118 static void __init update_local_mac(struct device_node *node)
119 {
120 struct property *newmac;
121 const u8* macaddr;
122 int prop_len;
123
124 macaddr = of_get_property(node, "local-mac-address", &prop_len);
125 if (macaddr == NULL || prop_len != MAC_LEN)
126 return;
127
128 newmac = kzalloc(sizeof(*newmac) + MAC_LEN, GFP_KERNEL);
129 if (newmac == NULL)
130 return;
131
132 newmac->value = newmac + 1;
133 newmac->length = MAC_LEN;
134 newmac->name = kstrdup("local-mac-address", GFP_KERNEL);
135 if (newmac->name == NULL) {
136 kfree(newmac);
137 return;
138 }
139
140 memcpy(newmac->value, macaddr, MAC_LEN);
141 ((u8*)newmac->value)[5] = (*(u32*)DIP_SWITCHES_VADDR) & 0x3f;
142 of_update_property(node, newmac);
143 }
144
machine_setup(void)145 static int __init machine_setup(void)
146 {
147 struct device_node *eth = NULL;
148
149 if ((eth = of_find_compatible_node(eth, NULL, "opencores,ethoc")))
150 update_local_mac(eth);
151 of_node_put(eth);
152 return 0;
153 }
154 arch_initcall(machine_setup);
155
156 #else
157
158 #include <linux/serial_8250.h>
159 #include <linux/if.h>
160 #include <net/ethoc.h>
161 #include <linux/usb/c67x00.h>
162
163 /*----------------------------------------------------------------------------
164 * Ethernet -- OpenCores Ethernet MAC (ethoc driver)
165 */
166
167 static struct resource ethoc_res[] = {
168 [0] = { /* register space */
169 .start = OETH_REGS_PADDR,
170 .end = OETH_REGS_PADDR + OETH_REGS_SIZE - 1,
171 .flags = IORESOURCE_MEM,
172 },
173 [1] = { /* buffer space */
174 .start = OETH_SRAMBUFF_PADDR,
175 .end = OETH_SRAMBUFF_PADDR + OETH_SRAMBUFF_SIZE - 1,
176 .flags = IORESOURCE_MEM,
177 },
178 [2] = { /* IRQ number */
179 .start = XTENSA_PIC_LINUX_IRQ(OETH_IRQ),
180 .end = XTENSA_PIC_LINUX_IRQ(OETH_IRQ),
181 .flags = IORESOURCE_IRQ,
182 },
183 };
184
185 static struct ethoc_platform_data ethoc_pdata = {
186 /*
187 * The MAC address for these boards is 00:50:c2:13:6f:xx.
188 * The last byte (here as zero) is read from the DIP switches on the
189 * board.
190 */
191 .hwaddr = { 0x00, 0x50, 0xc2, 0x13, 0x6f, 0 },
192 .phy_id = -1,
193 .big_endian = XCHAL_HAVE_BE,
194 };
195
196 static struct platform_device ethoc_device = {
197 .name = "ethoc",
198 .id = -1,
199 .num_resources = ARRAY_SIZE(ethoc_res),
200 .resource = ethoc_res,
201 .dev = {
202 .platform_data = ðoc_pdata,
203 },
204 };
205
206 /*----------------------------------------------------------------------------
207 * USB Host/Device -- Cypress CY7C67300
208 */
209
210 static struct resource c67x00_res[] = {
211 [0] = { /* register space */
212 .start = C67X00_PADDR,
213 .end = C67X00_PADDR + C67X00_SIZE - 1,
214 .flags = IORESOURCE_MEM,
215 },
216 [1] = { /* IRQ number */
217 .start = XTENSA_PIC_LINUX_IRQ(C67X00_IRQ),
218 .end = XTENSA_PIC_LINUX_IRQ(C67X00_IRQ),
219 .flags = IORESOURCE_IRQ,
220 },
221 };
222
223 static struct c67x00_platform_data c67x00_pdata = {
224 .sie_config = C67X00_SIE1_HOST | C67X00_SIE2_UNUSED,
225 .hpi_regstep = 4,
226 };
227
228 static struct platform_device c67x00_device = {
229 .name = "c67x00",
230 .id = -1,
231 .num_resources = ARRAY_SIZE(c67x00_res),
232 .resource = c67x00_res,
233 .dev = {
234 .platform_data = &c67x00_pdata,
235 },
236 };
237
238 /*----------------------------------------------------------------------------
239 * UART
240 */
241
242 static struct resource serial_resource = {
243 .start = DUART16552_PADDR,
244 .end = DUART16552_PADDR + 0x1f,
245 .flags = IORESOURCE_MEM,
246 };
247
248 static struct plat_serial8250_port serial_platform_data[] = {
249 [0] = {
250 .mapbase = DUART16552_PADDR,
251 .irq = XTENSA_PIC_LINUX_IRQ(DUART16552_INTNUM),
252 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
253 UPF_IOREMAP,
254 .iotype = XCHAL_HAVE_BE ? UPIO_MEM32BE : UPIO_MEM32,
255 .regshift = 2,
256 .uartclk = 0, /* set in xtavnet_init() */
257 },
258 { },
259 };
260
261 static struct platform_device xtavnet_uart = {
262 .name = "serial8250",
263 .id = PLAT8250_DEV_PLATFORM,
264 .dev = {
265 .platform_data = serial_platform_data,
266 },
267 .num_resources = 1,
268 .resource = &serial_resource,
269 };
270
271 /* platform devices */
272 static struct platform_device *platform_devices[] __initdata = {
273 ðoc_device,
274 &c67x00_device,
275 &xtavnet_uart,
276 };
277
278
xtavnet_init(void)279 static int __init xtavnet_init(void)
280 {
281 /* Ethernet MAC address. */
282 ethoc_pdata.hwaddr[5] = *(u32 *)DIP_SWITCHES_VADDR;
283
284 /* Clock rate varies among FPGA bitstreams; board specific FPGA register
285 * reports the actual clock rate.
286 */
287 serial_platform_data[0].uartclk = *(long *)XTFPGA_CLKFRQ_VADDR;
288
289
290 /* register platform devices */
291 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
292
293 /* ETHOC driver is a bit quiet; at least display Ethernet MAC, so user
294 * knows whether they set it correctly on the DIP switches.
295 */
296 pr_info("XTFPGA: Ethernet MAC %pM\n", ethoc_pdata.hwaddr);
297 ethoc_pdata.eth_clkfreq = *(long *)XTFPGA_CLKFRQ_VADDR;
298
299 return 0;
300 }
301
302 /*
303 * Register to be done during do_initcalls().
304 */
305 arch_initcall(xtavnet_init);
306
307 #endif /* CONFIG_USE_OF */
308