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1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Copyright 2016,2017 IBM Corporation.
4  */
5 
6 #define pr_fmt(fmt) "xive: " fmt
7 
8 #include <linux/types.h>
9 #include <linux/irq.h>
10 #include <linux/smp.h>
11 #include <linux/interrupt.h>
12 #include <linux/init.h>
13 #include <linux/of.h>
14 #include <linux/slab.h>
15 #include <linux/spinlock.h>
16 #include <linux/cpumask.h>
17 #include <linux/mm.h>
18 #include <linux/delay.h>
19 #include <linux/libfdt.h>
20 
21 #include <asm/prom.h>
22 #include <asm/io.h>
23 #include <asm/smp.h>
24 #include <asm/irq.h>
25 #include <asm/errno.h>
26 #include <asm/xive.h>
27 #include <asm/xive-regs.h>
28 #include <asm/hvcall.h>
29 
30 #include "xive-internal.h"
31 
32 static u32 xive_queue_shift;
33 
34 struct xive_irq_bitmap {
35 	unsigned long		*bitmap;
36 	unsigned int		base;
37 	unsigned int		count;
38 	spinlock_t		lock;
39 	struct list_head	list;
40 };
41 
42 static LIST_HEAD(xive_irq_bitmaps);
43 
xive_irq_bitmap_add(int base,int count)44 static int xive_irq_bitmap_add(int base, int count)
45 {
46 	struct xive_irq_bitmap *xibm;
47 
48 	xibm = kzalloc(sizeof(*xibm), GFP_KERNEL);
49 	if (!xibm)
50 		return -ENOMEM;
51 
52 	spin_lock_init(&xibm->lock);
53 	xibm->base = base;
54 	xibm->count = count;
55 	xibm->bitmap = kzalloc(xibm->count, GFP_KERNEL);
56 	if (!xibm->bitmap) {
57 		kfree(xibm);
58 		return -ENOMEM;
59 	}
60 	list_add(&xibm->list, &xive_irq_bitmaps);
61 
62 	pr_info("Using IRQ range [%x-%x]", xibm->base,
63 		xibm->base + xibm->count - 1);
64 	return 0;
65 }
66 
__xive_irq_bitmap_alloc(struct xive_irq_bitmap * xibm)67 static int __xive_irq_bitmap_alloc(struct xive_irq_bitmap *xibm)
68 {
69 	int irq;
70 
71 	irq = find_first_zero_bit(xibm->bitmap, xibm->count);
72 	if (irq != xibm->count) {
73 		set_bit(irq, xibm->bitmap);
74 		irq += xibm->base;
75 	} else {
76 		irq = -ENOMEM;
77 	}
78 
79 	return irq;
80 }
81 
xive_irq_bitmap_alloc(void)82 static int xive_irq_bitmap_alloc(void)
83 {
84 	struct xive_irq_bitmap *xibm;
85 	unsigned long flags;
86 	int irq = -ENOENT;
87 
88 	list_for_each_entry(xibm, &xive_irq_bitmaps, list) {
89 		spin_lock_irqsave(&xibm->lock, flags);
90 		irq = __xive_irq_bitmap_alloc(xibm);
91 		spin_unlock_irqrestore(&xibm->lock, flags);
92 		if (irq >= 0)
93 			break;
94 	}
95 	return irq;
96 }
97 
xive_irq_bitmap_free(int irq)98 static void xive_irq_bitmap_free(int irq)
99 {
100 	unsigned long flags;
101 	struct xive_irq_bitmap *xibm;
102 
103 	list_for_each_entry(xibm, &xive_irq_bitmaps, list) {
104 		if ((irq >= xibm->base) && (irq < xibm->base + xibm->count)) {
105 			spin_lock_irqsave(&xibm->lock, flags);
106 			clear_bit(irq - xibm->base, xibm->bitmap);
107 			spin_unlock_irqrestore(&xibm->lock, flags);
108 			break;
109 		}
110 	}
111 }
112 
113 
114 /* Based on the similar routines in RTAS */
plpar_busy_delay_time(long rc)115 static unsigned int plpar_busy_delay_time(long rc)
116 {
117 	unsigned int ms = 0;
118 
119 	if (H_IS_LONG_BUSY(rc)) {
120 		ms = get_longbusy_msecs(rc);
121 	} else if (rc == H_BUSY) {
122 		ms = 10; /* seems appropriate for XIVE hcalls */
123 	}
124 
125 	return ms;
126 }
127 
plpar_busy_delay(int rc)128 static unsigned int plpar_busy_delay(int rc)
129 {
130 	unsigned int ms;
131 
132 	ms = plpar_busy_delay_time(rc);
133 	if (ms)
134 		mdelay(ms);
135 
136 	return ms;
137 }
138 
139 /*
140  * Note: this call has a partition wide scope and can take a while to
141  * complete. If it returns H_LONG_BUSY_* it should be retried
142  * periodically.
143  */
plpar_int_reset(unsigned long flags)144 static long plpar_int_reset(unsigned long flags)
145 {
146 	long rc;
147 
148 	do {
149 		rc = plpar_hcall_norets(H_INT_RESET, flags);
150 	} while (plpar_busy_delay(rc));
151 
152 	if (rc)
153 		pr_err("H_INT_RESET failed %ld\n", rc);
154 
155 	return rc;
156 }
157 
plpar_int_get_source_info(unsigned long flags,unsigned long lisn,unsigned long * src_flags,unsigned long * eoi_page,unsigned long * trig_page,unsigned long * esb_shift)158 static long plpar_int_get_source_info(unsigned long flags,
159 				      unsigned long lisn,
160 				      unsigned long *src_flags,
161 				      unsigned long *eoi_page,
162 				      unsigned long *trig_page,
163 				      unsigned long *esb_shift)
164 {
165 	unsigned long retbuf[PLPAR_HCALL_BUFSIZE];
166 	long rc;
167 
168 	do {
169 		rc = plpar_hcall(H_INT_GET_SOURCE_INFO, retbuf, flags, lisn);
170 	} while (plpar_busy_delay(rc));
171 
172 	if (rc) {
173 		pr_err("H_INT_GET_SOURCE_INFO lisn=%ld failed %ld\n", lisn, rc);
174 		return rc;
175 	}
176 
177 	*src_flags = retbuf[0];
178 	*eoi_page  = retbuf[1];
179 	*trig_page = retbuf[2];
180 	*esb_shift = retbuf[3];
181 
182 	pr_devel("H_INT_GET_SOURCE_INFO flags=%lx eoi=%lx trig=%lx shift=%lx\n",
183 		retbuf[0], retbuf[1], retbuf[2], retbuf[3]);
184 
185 	return 0;
186 }
187 
188 #define XIVE_SRC_SET_EISN (1ull << (63 - 62))
189 #define XIVE_SRC_MASK     (1ull << (63 - 63)) /* unused */
190 
plpar_int_set_source_config(unsigned long flags,unsigned long lisn,unsigned long target,unsigned long prio,unsigned long sw_irq)191 static long plpar_int_set_source_config(unsigned long flags,
192 					unsigned long lisn,
193 					unsigned long target,
194 					unsigned long prio,
195 					unsigned long sw_irq)
196 {
197 	long rc;
198 
199 
200 	pr_devel("H_INT_SET_SOURCE_CONFIG flags=%lx lisn=%lx target=%lx prio=%lx sw_irq=%lx\n",
201 		flags, lisn, target, prio, sw_irq);
202 
203 
204 	do {
205 		rc = plpar_hcall_norets(H_INT_SET_SOURCE_CONFIG, flags, lisn,
206 					target, prio, sw_irq);
207 	} while (plpar_busy_delay(rc));
208 
209 	if (rc) {
210 		pr_err("H_INT_SET_SOURCE_CONFIG lisn=%ld target=%lx prio=%lx failed %ld\n",
211 		       lisn, target, prio, rc);
212 		return rc;
213 	}
214 
215 	return 0;
216 }
217 
plpar_int_get_source_config(unsigned long flags,unsigned long lisn,unsigned long * target,unsigned long * prio,unsigned long * sw_irq)218 static long plpar_int_get_source_config(unsigned long flags,
219 					unsigned long lisn,
220 					unsigned long *target,
221 					unsigned long *prio,
222 					unsigned long *sw_irq)
223 {
224 	unsigned long retbuf[PLPAR_HCALL_BUFSIZE];
225 	long rc;
226 
227 	pr_devel("H_INT_GET_SOURCE_CONFIG flags=%lx lisn=%lx\n", flags, lisn);
228 
229 	do {
230 		rc = plpar_hcall(H_INT_GET_SOURCE_CONFIG, retbuf, flags, lisn,
231 				 target, prio, sw_irq);
232 	} while (plpar_busy_delay(rc));
233 
234 	if (rc) {
235 		pr_err("H_INT_GET_SOURCE_CONFIG lisn=%ld failed %ld\n",
236 		       lisn, rc);
237 		return rc;
238 	}
239 
240 	*target = retbuf[0];
241 	*prio   = retbuf[1];
242 	*sw_irq = retbuf[2];
243 
244 	pr_devel("H_INT_GET_SOURCE_CONFIG target=%lx prio=%lx sw_irq=%lx\n",
245 		retbuf[0], retbuf[1], retbuf[2]);
246 
247 	return 0;
248 }
249 
plpar_int_get_queue_info(unsigned long flags,unsigned long target,unsigned long priority,unsigned long * esn_page,unsigned long * esn_size)250 static long plpar_int_get_queue_info(unsigned long flags,
251 				     unsigned long target,
252 				     unsigned long priority,
253 				     unsigned long *esn_page,
254 				     unsigned long *esn_size)
255 {
256 	unsigned long retbuf[PLPAR_HCALL_BUFSIZE];
257 	long rc;
258 
259 	do {
260 		rc = plpar_hcall(H_INT_GET_QUEUE_INFO, retbuf, flags, target,
261 				 priority);
262 	} while (plpar_busy_delay(rc));
263 
264 	if (rc) {
265 		pr_err("H_INT_GET_QUEUE_INFO cpu=%ld prio=%ld failed %ld\n",
266 		       target, priority, rc);
267 		return rc;
268 	}
269 
270 	*esn_page = retbuf[0];
271 	*esn_size = retbuf[1];
272 
273 	pr_devel("H_INT_GET_QUEUE_INFO page=%lx size=%lx\n",
274 		retbuf[0], retbuf[1]);
275 
276 	return 0;
277 }
278 
279 #define XIVE_EQ_ALWAYS_NOTIFY (1ull << (63 - 63))
280 
plpar_int_set_queue_config(unsigned long flags,unsigned long target,unsigned long priority,unsigned long qpage,unsigned long qsize)281 static long plpar_int_set_queue_config(unsigned long flags,
282 				       unsigned long target,
283 				       unsigned long priority,
284 				       unsigned long qpage,
285 				       unsigned long qsize)
286 {
287 	long rc;
288 
289 	pr_devel("H_INT_SET_QUEUE_CONFIG flags=%lx target=%lx priority=%lx qpage=%lx qsize=%lx\n",
290 		flags,  target, priority, qpage, qsize);
291 
292 	do {
293 		rc = plpar_hcall_norets(H_INT_SET_QUEUE_CONFIG, flags, target,
294 					priority, qpage, qsize);
295 	} while (plpar_busy_delay(rc));
296 
297 	if (rc) {
298 		pr_err("H_INT_SET_QUEUE_CONFIG cpu=%ld prio=%ld qpage=%lx returned %ld\n",
299 		       target, priority, qpage, rc);
300 		return  rc;
301 	}
302 
303 	return 0;
304 }
305 
plpar_int_sync(unsigned long flags,unsigned long lisn)306 static long plpar_int_sync(unsigned long flags, unsigned long lisn)
307 {
308 	long rc;
309 
310 	do {
311 		rc = plpar_hcall_norets(H_INT_SYNC, flags, lisn);
312 	} while (plpar_busy_delay(rc));
313 
314 	if (rc) {
315 		pr_err("H_INT_SYNC lisn=%ld returned %ld\n", lisn, rc);
316 		return  rc;
317 	}
318 
319 	return 0;
320 }
321 
322 #define XIVE_ESB_FLAG_STORE (1ull << (63 - 63))
323 
plpar_int_esb(unsigned long flags,unsigned long lisn,unsigned long offset,unsigned long in_data,unsigned long * out_data)324 static long plpar_int_esb(unsigned long flags,
325 			  unsigned long lisn,
326 			  unsigned long offset,
327 			  unsigned long in_data,
328 			  unsigned long *out_data)
329 {
330 	unsigned long retbuf[PLPAR_HCALL_BUFSIZE];
331 	long rc;
332 
333 	pr_devel("H_INT_ESB flags=%lx lisn=%lx offset=%lx in=%lx\n",
334 		flags,  lisn, offset, in_data);
335 
336 	do {
337 		rc = plpar_hcall(H_INT_ESB, retbuf, flags, lisn, offset,
338 				 in_data);
339 	} while (plpar_busy_delay(rc));
340 
341 	if (rc) {
342 		pr_err("H_INT_ESB lisn=%ld offset=%ld returned %ld\n",
343 		       lisn, offset, rc);
344 		return  rc;
345 	}
346 
347 	*out_data = retbuf[0];
348 
349 	return 0;
350 }
351 
xive_spapr_esb_rw(u32 lisn,u32 offset,u64 data,bool write)352 static u64 xive_spapr_esb_rw(u32 lisn, u32 offset, u64 data, bool write)
353 {
354 	unsigned long read_data;
355 	long rc;
356 
357 	rc = plpar_int_esb(write ? XIVE_ESB_FLAG_STORE : 0,
358 			   lisn, offset, data, &read_data);
359 	if (rc)
360 		return -1;
361 
362 	return write ? 0 : read_data;
363 }
364 
365 #define XIVE_SRC_H_INT_ESB     (1ull << (63 - 60))
366 #define XIVE_SRC_LSI           (1ull << (63 - 61))
367 #define XIVE_SRC_TRIGGER       (1ull << (63 - 62))
368 #define XIVE_SRC_STORE_EOI     (1ull << (63 - 63))
369 
xive_spapr_populate_irq_data(u32 hw_irq,struct xive_irq_data * data)370 static int xive_spapr_populate_irq_data(u32 hw_irq, struct xive_irq_data *data)
371 {
372 	long rc;
373 	unsigned long flags;
374 	unsigned long eoi_page;
375 	unsigned long trig_page;
376 	unsigned long esb_shift;
377 
378 	memset(data, 0, sizeof(*data));
379 
380 	rc = plpar_int_get_source_info(0, hw_irq, &flags, &eoi_page, &trig_page,
381 				       &esb_shift);
382 	if (rc)
383 		return  -EINVAL;
384 
385 	if (flags & XIVE_SRC_H_INT_ESB)
386 		data->flags  |= XIVE_IRQ_FLAG_H_INT_ESB;
387 	if (flags & XIVE_SRC_STORE_EOI)
388 		data->flags  |= XIVE_IRQ_FLAG_STORE_EOI;
389 	if (flags & XIVE_SRC_LSI)
390 		data->flags  |= XIVE_IRQ_FLAG_LSI;
391 	data->eoi_page  = eoi_page;
392 	data->esb_shift = esb_shift;
393 	data->trig_page = trig_page;
394 
395 	data->hw_irq = hw_irq;
396 
397 	/*
398 	 * No chip-id for the sPAPR backend. This has an impact how we
399 	 * pick a target. See xive_pick_irq_target().
400 	 */
401 	data->src_chip = XIVE_INVALID_CHIP_ID;
402 
403 	/*
404 	 * When the H_INT_ESB flag is set, the H_INT_ESB hcall should
405 	 * be used for interrupt management. Skip the remapping of the
406 	 * ESB pages which are not available.
407 	 */
408 	if (data->flags & XIVE_IRQ_FLAG_H_INT_ESB)
409 		return 0;
410 
411 	data->eoi_mmio = ioremap(data->eoi_page, 1u << data->esb_shift);
412 	if (!data->eoi_mmio) {
413 		pr_err("Failed to map EOI page for irq 0x%x\n", hw_irq);
414 		return -ENOMEM;
415 	}
416 
417 	/* Full function page supports trigger */
418 	if (flags & XIVE_SRC_TRIGGER) {
419 		data->trig_mmio = data->eoi_mmio;
420 		return 0;
421 	}
422 
423 	data->trig_mmio = ioremap(data->trig_page, 1u << data->esb_shift);
424 	if (!data->trig_mmio) {
425 		iounmap(data->eoi_mmio);
426 		pr_err("Failed to map trigger page for irq 0x%x\n", hw_irq);
427 		return -ENOMEM;
428 	}
429 	return 0;
430 }
431 
xive_spapr_configure_irq(u32 hw_irq,u32 target,u8 prio,u32 sw_irq)432 static int xive_spapr_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_irq)
433 {
434 	long rc;
435 
436 	rc = plpar_int_set_source_config(XIVE_SRC_SET_EISN, hw_irq, target,
437 					 prio, sw_irq);
438 
439 	return rc == 0 ? 0 : -ENXIO;
440 }
441 
xive_spapr_get_irq_config(u32 hw_irq,u32 * target,u8 * prio,u32 * sw_irq)442 static int xive_spapr_get_irq_config(u32 hw_irq, u32 *target, u8 *prio,
443 				     u32 *sw_irq)
444 {
445 	long rc;
446 	unsigned long h_target;
447 	unsigned long h_prio;
448 	unsigned long h_sw_irq;
449 
450 	rc = plpar_int_get_source_config(0, hw_irq, &h_target, &h_prio,
451 					 &h_sw_irq);
452 
453 	*target = h_target;
454 	*prio = h_prio;
455 	*sw_irq = h_sw_irq;
456 
457 	return rc == 0 ? 0 : -ENXIO;
458 }
459 
460 /* This can be called multiple time to change a queue configuration */
xive_spapr_configure_queue(u32 target,struct xive_q * q,u8 prio,__be32 * qpage,u32 order)461 static int xive_spapr_configure_queue(u32 target, struct xive_q *q, u8 prio,
462 				   __be32 *qpage, u32 order)
463 {
464 	s64 rc = 0;
465 	unsigned long esn_page;
466 	unsigned long esn_size;
467 	u64 flags, qpage_phys;
468 
469 	/* If there's an actual queue page, clean it */
470 	if (order) {
471 		if (WARN_ON(!qpage))
472 			return -EINVAL;
473 		qpage_phys = __pa(qpage);
474 	} else {
475 		qpage_phys = 0;
476 	}
477 
478 	/* Initialize the rest of the fields */
479 	q->msk = order ? ((1u << (order - 2)) - 1) : 0;
480 	q->idx = 0;
481 	q->toggle = 0;
482 
483 	rc = plpar_int_get_queue_info(0, target, prio, &esn_page, &esn_size);
484 	if (rc) {
485 		pr_err("Error %lld getting queue info CPU %d prio %d\n", rc,
486 		       target, prio);
487 		rc = -EIO;
488 		goto fail;
489 	}
490 
491 	/* TODO: add support for the notification page */
492 	q->eoi_phys = esn_page;
493 
494 	/* Default is to always notify */
495 	flags = XIVE_EQ_ALWAYS_NOTIFY;
496 
497 	/* Configure and enable the queue in HW */
498 	rc = plpar_int_set_queue_config(flags, target, prio, qpage_phys, order);
499 	if (rc) {
500 		pr_err("Error %lld setting queue for CPU %d prio %d\n", rc,
501 		       target, prio);
502 		rc = -EIO;
503 	} else {
504 		q->qpage = qpage;
505 	}
506 fail:
507 	return rc;
508 }
509 
xive_spapr_setup_queue(unsigned int cpu,struct xive_cpu * xc,u8 prio)510 static int xive_spapr_setup_queue(unsigned int cpu, struct xive_cpu *xc,
511 				  u8 prio)
512 {
513 	struct xive_q *q = &xc->queue[prio];
514 	__be32 *qpage;
515 
516 	qpage = xive_queue_page_alloc(cpu, xive_queue_shift);
517 	if (IS_ERR(qpage))
518 		return PTR_ERR(qpage);
519 
520 	return xive_spapr_configure_queue(get_hard_smp_processor_id(cpu),
521 					  q, prio, qpage, xive_queue_shift);
522 }
523 
xive_spapr_cleanup_queue(unsigned int cpu,struct xive_cpu * xc,u8 prio)524 static void xive_spapr_cleanup_queue(unsigned int cpu, struct xive_cpu *xc,
525 				  u8 prio)
526 {
527 	struct xive_q *q = &xc->queue[prio];
528 	unsigned int alloc_order;
529 	long rc;
530 	int hw_cpu = get_hard_smp_processor_id(cpu);
531 
532 	rc = plpar_int_set_queue_config(0, hw_cpu, prio, 0, 0);
533 	if (rc)
534 		pr_err("Error %ld setting queue for CPU %d prio %d\n", rc,
535 		       hw_cpu, prio);
536 
537 	alloc_order = xive_alloc_order(xive_queue_shift);
538 	free_pages((unsigned long)q->qpage, alloc_order);
539 	q->qpage = NULL;
540 }
541 
xive_spapr_match(struct device_node * node)542 static bool xive_spapr_match(struct device_node *node)
543 {
544 	/* Ignore cascaded controllers for the moment */
545 	return 1;
546 }
547 
548 #ifdef CONFIG_SMP
xive_spapr_get_ipi(unsigned int cpu,struct xive_cpu * xc)549 static int xive_spapr_get_ipi(unsigned int cpu, struct xive_cpu *xc)
550 {
551 	int irq = xive_irq_bitmap_alloc();
552 
553 	if (irq < 0) {
554 		pr_err("Failed to allocate IPI on CPU %d\n", cpu);
555 		return -ENXIO;
556 	}
557 
558 	xc->hw_ipi = irq;
559 	return 0;
560 }
561 
xive_spapr_put_ipi(unsigned int cpu,struct xive_cpu * xc)562 static void xive_spapr_put_ipi(unsigned int cpu, struct xive_cpu *xc)
563 {
564 	if (xc->hw_ipi == XIVE_BAD_IRQ)
565 		return;
566 
567 	xive_irq_bitmap_free(xc->hw_ipi);
568 	xc->hw_ipi = XIVE_BAD_IRQ;
569 }
570 #endif /* CONFIG_SMP */
571 
xive_spapr_shutdown(void)572 static void xive_spapr_shutdown(void)
573 {
574 	plpar_int_reset(0);
575 }
576 
577 /*
578  * Perform an "ack" cycle on the current thread. Grab the pending
579  * active priorities and update the CPPR to the most favored one.
580  */
xive_spapr_update_pending(struct xive_cpu * xc)581 static void xive_spapr_update_pending(struct xive_cpu *xc)
582 {
583 	u8 nsr, cppr;
584 	u16 ack;
585 
586 	/*
587 	 * Perform the "Acknowledge O/S to Register" cycle.
588 	 *
589 	 * Let's speedup the access to the TIMA using the raw I/O
590 	 * accessor as we don't need the synchronisation routine of
591 	 * the higher level ones
592 	 */
593 	ack = be16_to_cpu(__raw_readw(xive_tima + TM_SPC_ACK_OS_REG));
594 
595 	/* Synchronize subsequent queue accesses */
596 	mb();
597 
598 	/*
599 	 * Grab the CPPR and the "NSR" field which indicates the source
600 	 * of the interrupt (if any)
601 	 */
602 	cppr = ack & 0xff;
603 	nsr = ack >> 8;
604 
605 	if (nsr & TM_QW1_NSR_EO) {
606 		if (cppr == 0xff)
607 			return;
608 		/* Mark the priority pending */
609 		xc->pending_prio |= 1 << cppr;
610 
611 		/*
612 		 * A new interrupt should never have a CPPR less favored
613 		 * than our current one.
614 		 */
615 		if (cppr >= xc->cppr)
616 			pr_err("CPU %d odd ack CPPR, got %d at %d\n",
617 			       smp_processor_id(), cppr, xc->cppr);
618 
619 		/* Update our idea of what the CPPR is */
620 		xc->cppr = cppr;
621 	}
622 }
623 
xive_spapr_eoi(u32 hw_irq)624 static void xive_spapr_eoi(u32 hw_irq)
625 {
626 	/* Not used */;
627 }
628 
xive_spapr_setup_cpu(unsigned int cpu,struct xive_cpu * xc)629 static void xive_spapr_setup_cpu(unsigned int cpu, struct xive_cpu *xc)
630 {
631 	/* Only some debug on the TIMA settings */
632 	pr_debug("(HW value: %08x %08x %08x)\n",
633 		 in_be32(xive_tima + TM_QW1_OS + TM_WORD0),
634 		 in_be32(xive_tima + TM_QW1_OS + TM_WORD1),
635 		 in_be32(xive_tima + TM_QW1_OS + TM_WORD2));
636 }
637 
xive_spapr_teardown_cpu(unsigned int cpu,struct xive_cpu * xc)638 static void xive_spapr_teardown_cpu(unsigned int cpu, struct xive_cpu *xc)
639 {
640 	/* Nothing to do */;
641 }
642 
xive_spapr_sync_source(u32 hw_irq)643 static void xive_spapr_sync_source(u32 hw_irq)
644 {
645 	/* Specs are unclear on what this is doing */
646 	plpar_int_sync(0, hw_irq);
647 }
648 
649 static const struct xive_ops xive_spapr_ops = {
650 	.populate_irq_data	= xive_spapr_populate_irq_data,
651 	.configure_irq		= xive_spapr_configure_irq,
652 	.get_irq_config		= xive_spapr_get_irq_config,
653 	.setup_queue		= xive_spapr_setup_queue,
654 	.cleanup_queue		= xive_spapr_cleanup_queue,
655 	.match			= xive_spapr_match,
656 	.shutdown		= xive_spapr_shutdown,
657 	.update_pending		= xive_spapr_update_pending,
658 	.eoi			= xive_spapr_eoi,
659 	.setup_cpu		= xive_spapr_setup_cpu,
660 	.teardown_cpu		= xive_spapr_teardown_cpu,
661 	.sync_source		= xive_spapr_sync_source,
662 	.esb_rw			= xive_spapr_esb_rw,
663 #ifdef CONFIG_SMP
664 	.get_ipi		= xive_spapr_get_ipi,
665 	.put_ipi		= xive_spapr_put_ipi,
666 #endif /* CONFIG_SMP */
667 	.name			= "spapr",
668 };
669 
670 /*
671  * get max priority from "/ibm,plat-res-int-priorities"
672  */
xive_get_max_prio(u8 * max_prio)673 static bool xive_get_max_prio(u8 *max_prio)
674 {
675 	struct device_node *rootdn;
676 	const __be32 *reg;
677 	u32 len;
678 	int prio, found;
679 
680 	rootdn = of_find_node_by_path("/");
681 	if (!rootdn) {
682 		pr_err("not root node found !\n");
683 		return false;
684 	}
685 
686 	reg = of_get_property(rootdn, "ibm,plat-res-int-priorities", &len);
687 	of_node_put(rootdn);
688 	if (!reg) {
689 		pr_err("Failed to read 'ibm,plat-res-int-priorities' property\n");
690 		return false;
691 	}
692 
693 	if (len % (2 * sizeof(u32)) != 0) {
694 		pr_err("invalid 'ibm,plat-res-int-priorities' property\n");
695 		return false;
696 	}
697 
698 	/* HW supports priorities in the range [0-7] and 0xFF is a
699 	 * wildcard priority used to mask. We scan the ranges reserved
700 	 * by the hypervisor to find the lowest priority we can use.
701 	 */
702 	found = 0xFF;
703 	for (prio = 0; prio < 8; prio++) {
704 		int reserved = 0;
705 		int i;
706 
707 		for (i = 0; i < len / (2 * sizeof(u32)); i++) {
708 			int base  = be32_to_cpu(reg[2 * i]);
709 			int range = be32_to_cpu(reg[2 * i + 1]);
710 
711 			if (prio >= base && prio < base + range)
712 				reserved++;
713 		}
714 
715 		if (!reserved)
716 			found = prio;
717 	}
718 
719 	if (found == 0xFF) {
720 		pr_err("no valid priority found in 'ibm,plat-res-int-priorities'\n");
721 		return false;
722 	}
723 
724 	*max_prio = found;
725 	return true;
726 }
727 
get_vec5_feature(unsigned int index)728 static const u8 *get_vec5_feature(unsigned int index)
729 {
730 	unsigned long root, chosen;
731 	int size;
732 	const u8 *vec5;
733 
734 	root = of_get_flat_dt_root();
735 	chosen = of_get_flat_dt_subnode_by_name(root, "chosen");
736 	if (chosen == -FDT_ERR_NOTFOUND)
737 		return NULL;
738 
739 	vec5 = of_get_flat_dt_prop(chosen, "ibm,architecture-vec-5", &size);
740 	if (!vec5)
741 		return NULL;
742 
743 	if (size <= index)
744 		return NULL;
745 
746 	return vec5 + index;
747 }
748 
xive_spapr_disabled(void)749 static bool xive_spapr_disabled(void)
750 {
751 	const u8 *vec5_xive;
752 
753 	vec5_xive = get_vec5_feature(OV5_INDX(OV5_XIVE_SUPPORT));
754 	if (vec5_xive) {
755 		u8 val;
756 
757 		val = *vec5_xive & OV5_FEAT(OV5_XIVE_SUPPORT);
758 		switch (val) {
759 		case OV5_FEAT(OV5_XIVE_EITHER):
760 		case OV5_FEAT(OV5_XIVE_LEGACY):
761 			break;
762 		case OV5_FEAT(OV5_XIVE_EXPLOIT):
763 			/* Hypervisor only supports XIVE */
764 			if (xive_cmdline_disabled)
765 				pr_warn("WARNING: Ignoring cmdline option xive=off\n");
766 			return false;
767 		default:
768 			pr_warn("%s: Unknown xive support option: 0x%x\n",
769 				__func__, val);
770 			break;
771 		}
772 	}
773 
774 	return xive_cmdline_disabled;
775 }
776 
xive_spapr_init(void)777 bool __init xive_spapr_init(void)
778 {
779 	struct device_node *np;
780 	struct resource r;
781 	void __iomem *tima;
782 	struct property *prop;
783 	u8 max_prio;
784 	u32 val;
785 	u32 len;
786 	const __be32 *reg;
787 	int i;
788 
789 	if (xive_spapr_disabled())
790 		return false;
791 
792 	pr_devel("%s()\n", __func__);
793 	np = of_find_compatible_node(NULL, NULL, "ibm,power-ivpe");
794 	if (!np) {
795 		pr_devel("not found !\n");
796 		return false;
797 	}
798 	pr_devel("Found %s\n", np->full_name);
799 
800 	/* Resource 1 is the OS ring TIMA */
801 	if (of_address_to_resource(np, 1, &r)) {
802 		pr_err("Failed to get thread mgmnt area resource\n");
803 		return false;
804 	}
805 	tima = ioremap(r.start, resource_size(&r));
806 	if (!tima) {
807 		pr_err("Failed to map thread mgmnt area\n");
808 		return false;
809 	}
810 
811 	if (!xive_get_max_prio(&max_prio))
812 		return false;
813 
814 	/* Feed the IRQ number allocator with the ranges given in the DT */
815 	reg = of_get_property(np, "ibm,xive-lisn-ranges", &len);
816 	if (!reg) {
817 		pr_err("Failed to read 'ibm,xive-lisn-ranges' property\n");
818 		return false;
819 	}
820 
821 	if (len % (2 * sizeof(u32)) != 0) {
822 		pr_err("invalid 'ibm,xive-lisn-ranges' property\n");
823 		return false;
824 	}
825 
826 	for (i = 0; i < len / (2 * sizeof(u32)); i++, reg += 2)
827 		xive_irq_bitmap_add(be32_to_cpu(reg[0]),
828 				    be32_to_cpu(reg[1]));
829 
830 	/* Iterate the EQ sizes and pick one */
831 	of_property_for_each_u32(np, "ibm,xive-eq-sizes", prop, reg, val) {
832 		xive_queue_shift = val;
833 		if (val == PAGE_SHIFT)
834 			break;
835 	}
836 
837 	/* Initialize XIVE core with our backend */
838 	if (!xive_core_init(&xive_spapr_ops, tima, TM_QW1_OS, max_prio))
839 		return false;
840 
841 	pr_info("Using %dkB queues\n", 1 << (xive_queue_shift - 10));
842 	return true;
843 }
844