1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2012,2013 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 *
6 * Derived from arch/arm/kvm/coproc.c:
7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
8 * Authors: Rusty Russell <rusty@rustcorp.com.au>
9 * Christoffer Dall <c.dall@virtualopensystems.com>
10 */
11
12 #include <linux/bsearch.h>
13 #include <linux/kvm_host.h>
14 #include <linux/mm.h>
15 #include <linux/printk.h>
16 #include <linux/uaccess.h>
17
18 #include <asm/cacheflush.h>
19 #include <asm/cputype.h>
20 #include <asm/debug-monitors.h>
21 #include <asm/esr.h>
22 #include <asm/kvm_arm.h>
23 #include <asm/kvm_coproc.h>
24 #include <asm/kvm_emulate.h>
25 #include <asm/kvm_host.h>
26 #include <asm/kvm_hyp.h>
27 #include <asm/kvm_mmu.h>
28 #include <asm/perf_event.h>
29 #include <asm/sysreg.h>
30
31 #include <trace/events/kvm.h>
32
33 #include "sys_regs.h"
34
35 #include "trace.h"
36
37 /*
38 * All of this file is extremly similar to the ARM coproc.c, but the
39 * types are different. My gut feeling is that it should be pretty
40 * easy to merge, but that would be an ABI breakage -- again. VFP
41 * would also need to be abstracted.
42 *
43 * For AArch32, we only take care of what is being trapped. Anything
44 * that has to do with init and userspace access has to go via the
45 * 64bit interface.
46 */
47
read_from_write_only(struct kvm_vcpu * vcpu,struct sys_reg_params * params,const struct sys_reg_desc * r)48 static bool read_from_write_only(struct kvm_vcpu *vcpu,
49 struct sys_reg_params *params,
50 const struct sys_reg_desc *r)
51 {
52 WARN_ONCE(1, "Unexpected sys_reg read to write-only register\n");
53 print_sys_reg_instr(params);
54 kvm_inject_undefined(vcpu);
55 return false;
56 }
57
write_to_read_only(struct kvm_vcpu * vcpu,struct sys_reg_params * params,const struct sys_reg_desc * r)58 static bool write_to_read_only(struct kvm_vcpu *vcpu,
59 struct sys_reg_params *params,
60 const struct sys_reg_desc *r)
61 {
62 WARN_ONCE(1, "Unexpected sys_reg write to read-only register\n");
63 print_sys_reg_instr(params);
64 kvm_inject_undefined(vcpu);
65 return false;
66 }
67
vcpu_read_sys_reg(const struct kvm_vcpu * vcpu,int reg)68 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg)
69 {
70 if (!vcpu->arch.sysregs_loaded_on_cpu)
71 goto immediate_read;
72
73 /*
74 * System registers listed in the switch are not saved on every
75 * exit from the guest but are only saved on vcpu_put.
76 *
77 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but
78 * should never be listed below, because the guest cannot modify its
79 * own MPIDR_EL1 and MPIDR_EL1 is accessed for VCPU A from VCPU B's
80 * thread when emulating cross-VCPU communication.
81 */
82 switch (reg) {
83 case CSSELR_EL1: return read_sysreg_s(SYS_CSSELR_EL1);
84 case SCTLR_EL1: return read_sysreg_s(SYS_SCTLR_EL12);
85 case ACTLR_EL1: return read_sysreg_s(SYS_ACTLR_EL1);
86 case CPACR_EL1: return read_sysreg_s(SYS_CPACR_EL12);
87 case TTBR0_EL1: return read_sysreg_s(SYS_TTBR0_EL12);
88 case TTBR1_EL1: return read_sysreg_s(SYS_TTBR1_EL12);
89 case TCR_EL1: return read_sysreg_s(SYS_TCR_EL12);
90 case ESR_EL1: return read_sysreg_s(SYS_ESR_EL12);
91 case AFSR0_EL1: return read_sysreg_s(SYS_AFSR0_EL12);
92 case AFSR1_EL1: return read_sysreg_s(SYS_AFSR1_EL12);
93 case FAR_EL1: return read_sysreg_s(SYS_FAR_EL12);
94 case MAIR_EL1: return read_sysreg_s(SYS_MAIR_EL12);
95 case VBAR_EL1: return read_sysreg_s(SYS_VBAR_EL12);
96 case CONTEXTIDR_EL1: return read_sysreg_s(SYS_CONTEXTIDR_EL12);
97 case TPIDR_EL0: return read_sysreg_s(SYS_TPIDR_EL0);
98 case TPIDRRO_EL0: return read_sysreg_s(SYS_TPIDRRO_EL0);
99 case TPIDR_EL1: return read_sysreg_s(SYS_TPIDR_EL1);
100 case AMAIR_EL1: return read_sysreg_s(SYS_AMAIR_EL12);
101 case CNTKCTL_EL1: return read_sysreg_s(SYS_CNTKCTL_EL12);
102 case PAR_EL1: return read_sysreg_s(SYS_PAR_EL1);
103 case DACR32_EL2: return read_sysreg_s(SYS_DACR32_EL2);
104 case IFSR32_EL2: return read_sysreg_s(SYS_IFSR32_EL2);
105 case DBGVCR32_EL2: return read_sysreg_s(SYS_DBGVCR32_EL2);
106 }
107
108 immediate_read:
109 return __vcpu_sys_reg(vcpu, reg);
110 }
111
vcpu_write_sys_reg(struct kvm_vcpu * vcpu,u64 val,int reg)112 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg)
113 {
114 if (!vcpu->arch.sysregs_loaded_on_cpu)
115 goto immediate_write;
116
117 /*
118 * System registers listed in the switch are not restored on every
119 * entry to the guest but are only restored on vcpu_load.
120 *
121 * Note that MPIDR_EL1 for the guest is set by KVM via VMPIDR_EL2 but
122 * should never be listed below, because the the MPIDR should only be
123 * set once, before running the VCPU, and never changed later.
124 */
125 switch (reg) {
126 case CSSELR_EL1: write_sysreg_s(val, SYS_CSSELR_EL1); return;
127 case SCTLR_EL1: write_sysreg_s(val, SYS_SCTLR_EL12); return;
128 case ACTLR_EL1: write_sysreg_s(val, SYS_ACTLR_EL1); return;
129 case CPACR_EL1: write_sysreg_s(val, SYS_CPACR_EL12); return;
130 case TTBR0_EL1: write_sysreg_s(val, SYS_TTBR0_EL12); return;
131 case TTBR1_EL1: write_sysreg_s(val, SYS_TTBR1_EL12); return;
132 case TCR_EL1: write_sysreg_s(val, SYS_TCR_EL12); return;
133 case ESR_EL1: write_sysreg_s(val, SYS_ESR_EL12); return;
134 case AFSR0_EL1: write_sysreg_s(val, SYS_AFSR0_EL12); return;
135 case AFSR1_EL1: write_sysreg_s(val, SYS_AFSR1_EL12); return;
136 case FAR_EL1: write_sysreg_s(val, SYS_FAR_EL12); return;
137 case MAIR_EL1: write_sysreg_s(val, SYS_MAIR_EL12); return;
138 case VBAR_EL1: write_sysreg_s(val, SYS_VBAR_EL12); return;
139 case CONTEXTIDR_EL1: write_sysreg_s(val, SYS_CONTEXTIDR_EL12); return;
140 case TPIDR_EL0: write_sysreg_s(val, SYS_TPIDR_EL0); return;
141 case TPIDRRO_EL0: write_sysreg_s(val, SYS_TPIDRRO_EL0); return;
142 case TPIDR_EL1: write_sysreg_s(val, SYS_TPIDR_EL1); return;
143 case AMAIR_EL1: write_sysreg_s(val, SYS_AMAIR_EL12); return;
144 case CNTKCTL_EL1: write_sysreg_s(val, SYS_CNTKCTL_EL12); return;
145 case PAR_EL1: write_sysreg_s(val, SYS_PAR_EL1); return;
146 case DACR32_EL2: write_sysreg_s(val, SYS_DACR32_EL2); return;
147 case IFSR32_EL2: write_sysreg_s(val, SYS_IFSR32_EL2); return;
148 case DBGVCR32_EL2: write_sysreg_s(val, SYS_DBGVCR32_EL2); return;
149 }
150
151 immediate_write:
152 __vcpu_sys_reg(vcpu, reg) = val;
153 }
154
155 /* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */
156 static u32 cache_levels;
157
158 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
159 #define CSSELR_MAX 12
160
161 /* Which cache CCSIDR represents depends on CSSELR value. */
get_ccsidr(u32 csselr)162 static u32 get_ccsidr(u32 csselr)
163 {
164 u32 ccsidr;
165
166 /* Make sure noone else changes CSSELR during this! */
167 local_irq_disable();
168 write_sysreg(csselr, csselr_el1);
169 isb();
170 ccsidr = read_sysreg(ccsidr_el1);
171 local_irq_enable();
172
173 return ccsidr;
174 }
175
176 /*
177 * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized).
178 */
access_dcsw(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)179 static bool access_dcsw(struct kvm_vcpu *vcpu,
180 struct sys_reg_params *p,
181 const struct sys_reg_desc *r)
182 {
183 if (!p->is_write)
184 return read_from_write_only(vcpu, p, r);
185
186 /*
187 * Only track S/W ops if we don't have FWB. It still indicates
188 * that the guest is a bit broken (S/W operations should only
189 * be done by firmware, knowing that there is only a single
190 * CPU left in the system, and certainly not from non-secure
191 * software).
192 */
193 if (!cpus_have_const_cap(ARM64_HAS_STAGE2_FWB))
194 kvm_set_way_flush(vcpu);
195
196 return true;
197 }
198
199 /*
200 * Generic accessor for VM registers. Only called as long as HCR_TVM
201 * is set. If the guest enables the MMU, we stop trapping the VM
202 * sys_regs and leave it in complete control of the caches.
203 */
access_vm_reg(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)204 static bool access_vm_reg(struct kvm_vcpu *vcpu,
205 struct sys_reg_params *p,
206 const struct sys_reg_desc *r)
207 {
208 bool was_enabled = vcpu_has_cache_enabled(vcpu);
209 u64 val;
210 int reg = r->reg;
211
212 BUG_ON(!p->is_write);
213
214 /* See the 32bit mapping in kvm_host.h */
215 if (p->is_aarch32)
216 reg = r->reg / 2;
217
218 if (!p->is_aarch32 || !p->is_32bit) {
219 val = p->regval;
220 } else {
221 val = vcpu_read_sys_reg(vcpu, reg);
222 if (r->reg % 2)
223 val = (p->regval << 32) | (u64)lower_32_bits(val);
224 else
225 val = ((u64)upper_32_bits(val) << 32) |
226 lower_32_bits(p->regval);
227 }
228 vcpu_write_sys_reg(vcpu, val, reg);
229
230 kvm_toggle_cache(vcpu, was_enabled);
231 return true;
232 }
233
234 /*
235 * Trap handler for the GICv3 SGI generation system register.
236 * Forward the request to the VGIC emulation.
237 * The cp15_64 code makes sure this automatically works
238 * for both AArch64 and AArch32 accesses.
239 */
access_gic_sgi(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)240 static bool access_gic_sgi(struct kvm_vcpu *vcpu,
241 struct sys_reg_params *p,
242 const struct sys_reg_desc *r)
243 {
244 bool g1;
245
246 if (!p->is_write)
247 return read_from_write_only(vcpu, p, r);
248
249 /*
250 * In a system where GICD_CTLR.DS=1, a ICC_SGI0R_EL1 access generates
251 * Group0 SGIs only, while ICC_SGI1R_EL1 can generate either group,
252 * depending on the SGI configuration. ICC_ASGI1R_EL1 is effectively
253 * equivalent to ICC_SGI0R_EL1, as there is no "alternative" secure
254 * group.
255 */
256 if (p->is_aarch32) {
257 switch (p->Op1) {
258 default: /* Keep GCC quiet */
259 case 0: /* ICC_SGI1R */
260 g1 = true;
261 break;
262 case 1: /* ICC_ASGI1R */
263 case 2: /* ICC_SGI0R */
264 g1 = false;
265 break;
266 }
267 } else {
268 switch (p->Op2) {
269 default: /* Keep GCC quiet */
270 case 5: /* ICC_SGI1R_EL1 */
271 g1 = true;
272 break;
273 case 6: /* ICC_ASGI1R_EL1 */
274 case 7: /* ICC_SGI0R_EL1 */
275 g1 = false;
276 break;
277 }
278 }
279
280 vgic_v3_dispatch_sgi(vcpu, p->regval, g1);
281
282 return true;
283 }
284
access_gic_sre(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)285 static bool access_gic_sre(struct kvm_vcpu *vcpu,
286 struct sys_reg_params *p,
287 const struct sys_reg_desc *r)
288 {
289 if (p->is_write)
290 return ignore_write(vcpu, p);
291
292 p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre;
293 return true;
294 }
295
trap_raz_wi(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)296 static bool trap_raz_wi(struct kvm_vcpu *vcpu,
297 struct sys_reg_params *p,
298 const struct sys_reg_desc *r)
299 {
300 if (p->is_write)
301 return ignore_write(vcpu, p);
302 else
303 return read_zero(vcpu, p);
304 }
305
306 /*
307 * ARMv8.1 mandates at least a trivial LORegion implementation, where all the
308 * RW registers are RES0 (which we can implement as RAZ/WI). On an ARMv8.0
309 * system, these registers should UNDEF. LORID_EL1 being a RO register, we
310 * treat it separately.
311 */
trap_loregion(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)312 static bool trap_loregion(struct kvm_vcpu *vcpu,
313 struct sys_reg_params *p,
314 const struct sys_reg_desc *r)
315 {
316 u64 val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
317 u32 sr = sys_reg((u32)r->Op0, (u32)r->Op1,
318 (u32)r->CRn, (u32)r->CRm, (u32)r->Op2);
319
320 if (!(val & (0xfUL << ID_AA64MMFR1_LOR_SHIFT))) {
321 kvm_inject_undefined(vcpu);
322 return false;
323 }
324
325 if (p->is_write && sr == SYS_LORID_EL1)
326 return write_to_read_only(vcpu, p, r);
327
328 return trap_raz_wi(vcpu, p, r);
329 }
330
trap_oslsr_el1(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)331 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu,
332 struct sys_reg_params *p,
333 const struct sys_reg_desc *r)
334 {
335 if (p->is_write) {
336 return ignore_write(vcpu, p);
337 } else {
338 p->regval = (1 << 3);
339 return true;
340 }
341 }
342
trap_dbgauthstatus_el1(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)343 static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu,
344 struct sys_reg_params *p,
345 const struct sys_reg_desc *r)
346 {
347 if (p->is_write) {
348 return ignore_write(vcpu, p);
349 } else {
350 p->regval = read_sysreg(dbgauthstatus_el1);
351 return true;
352 }
353 }
354
355 /*
356 * We want to avoid world-switching all the DBG registers all the
357 * time:
358 *
359 * - If we've touched any debug register, it is likely that we're
360 * going to touch more of them. It then makes sense to disable the
361 * traps and start doing the save/restore dance
362 * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is
363 * then mandatory to save/restore the registers, as the guest
364 * depends on them.
365 *
366 * For this, we use a DIRTY bit, indicating the guest has modified the
367 * debug registers, used as follow:
368 *
369 * On guest entry:
370 * - If the dirty bit is set (because we're coming back from trapping),
371 * disable the traps, save host registers, restore guest registers.
372 * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set),
373 * set the dirty bit, disable the traps, save host registers,
374 * restore guest registers.
375 * - Otherwise, enable the traps
376 *
377 * On guest exit:
378 * - If the dirty bit is set, save guest registers, restore host
379 * registers and clear the dirty bit. This ensure that the host can
380 * now use the debug registers.
381 */
trap_debug_regs(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)382 static bool trap_debug_regs(struct kvm_vcpu *vcpu,
383 struct sys_reg_params *p,
384 const struct sys_reg_desc *r)
385 {
386 if (p->is_write) {
387 vcpu_write_sys_reg(vcpu, p->regval, r->reg);
388 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY;
389 } else {
390 p->regval = vcpu_read_sys_reg(vcpu, r->reg);
391 }
392
393 trace_trap_reg(__func__, r->reg, p->is_write, p->regval);
394
395 return true;
396 }
397
398 /*
399 * reg_to_dbg/dbg_to_reg
400 *
401 * A 32 bit write to a debug register leave top bits alone
402 * A 32 bit read from a debug register only returns the bottom bits
403 *
404 * All writes will set the KVM_ARM64_DEBUG_DIRTY flag to ensure the
405 * hyp.S code switches between host and guest values in future.
406 */
reg_to_dbg(struct kvm_vcpu * vcpu,struct sys_reg_params * p,u64 * dbg_reg)407 static void reg_to_dbg(struct kvm_vcpu *vcpu,
408 struct sys_reg_params *p,
409 u64 *dbg_reg)
410 {
411 u64 val = p->regval;
412
413 if (p->is_32bit) {
414 val &= 0xffffffffUL;
415 val |= ((*dbg_reg >> 32) << 32);
416 }
417
418 *dbg_reg = val;
419 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY;
420 }
421
dbg_to_reg(struct kvm_vcpu * vcpu,struct sys_reg_params * p,u64 * dbg_reg)422 static void dbg_to_reg(struct kvm_vcpu *vcpu,
423 struct sys_reg_params *p,
424 u64 *dbg_reg)
425 {
426 p->regval = *dbg_reg;
427 if (p->is_32bit)
428 p->regval &= 0xffffffffUL;
429 }
430
trap_bvr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * rd)431 static bool trap_bvr(struct kvm_vcpu *vcpu,
432 struct sys_reg_params *p,
433 const struct sys_reg_desc *rd)
434 {
435 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm];
436
437 if (p->is_write)
438 reg_to_dbg(vcpu, p, dbg_reg);
439 else
440 dbg_to_reg(vcpu, p, dbg_reg);
441
442 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg);
443
444 return true;
445 }
446
set_bvr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,const struct kvm_one_reg * reg,void __user * uaddr)447 static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
448 const struct kvm_one_reg *reg, void __user *uaddr)
449 {
450 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm];
451
452 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
453 return -EFAULT;
454 return 0;
455 }
456
get_bvr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,const struct kvm_one_reg * reg,void __user * uaddr)457 static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
458 const struct kvm_one_reg *reg, void __user *uaddr)
459 {
460 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm];
461
462 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
463 return -EFAULT;
464 return 0;
465 }
466
reset_bvr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)467 static void reset_bvr(struct kvm_vcpu *vcpu,
468 const struct sys_reg_desc *rd)
469 {
470 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = rd->val;
471 }
472
trap_bcr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * rd)473 static bool trap_bcr(struct kvm_vcpu *vcpu,
474 struct sys_reg_params *p,
475 const struct sys_reg_desc *rd)
476 {
477 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm];
478
479 if (p->is_write)
480 reg_to_dbg(vcpu, p, dbg_reg);
481 else
482 dbg_to_reg(vcpu, p, dbg_reg);
483
484 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg);
485
486 return true;
487 }
488
set_bcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,const struct kvm_one_reg * reg,void __user * uaddr)489 static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
490 const struct kvm_one_reg *reg, void __user *uaddr)
491 {
492 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm];
493
494 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
495 return -EFAULT;
496
497 return 0;
498 }
499
get_bcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,const struct kvm_one_reg * reg,void __user * uaddr)500 static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
501 const struct kvm_one_reg *reg, void __user *uaddr)
502 {
503 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm];
504
505 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
506 return -EFAULT;
507 return 0;
508 }
509
reset_bcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)510 static void reset_bcr(struct kvm_vcpu *vcpu,
511 const struct sys_reg_desc *rd)
512 {
513 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm] = rd->val;
514 }
515
trap_wvr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * rd)516 static bool trap_wvr(struct kvm_vcpu *vcpu,
517 struct sys_reg_params *p,
518 const struct sys_reg_desc *rd)
519 {
520 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm];
521
522 if (p->is_write)
523 reg_to_dbg(vcpu, p, dbg_reg);
524 else
525 dbg_to_reg(vcpu, p, dbg_reg);
526
527 trace_trap_reg(__func__, rd->CRm, p->is_write,
528 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]);
529
530 return true;
531 }
532
set_wvr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,const struct kvm_one_reg * reg,void __user * uaddr)533 static int set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
534 const struct kvm_one_reg *reg, void __user *uaddr)
535 {
536 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm];
537
538 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
539 return -EFAULT;
540 return 0;
541 }
542
get_wvr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,const struct kvm_one_reg * reg,void __user * uaddr)543 static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
544 const struct kvm_one_reg *reg, void __user *uaddr)
545 {
546 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm];
547
548 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
549 return -EFAULT;
550 return 0;
551 }
552
reset_wvr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)553 static void reset_wvr(struct kvm_vcpu *vcpu,
554 const struct sys_reg_desc *rd)
555 {
556 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm] = rd->val;
557 }
558
trap_wcr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * rd)559 static bool trap_wcr(struct kvm_vcpu *vcpu,
560 struct sys_reg_params *p,
561 const struct sys_reg_desc *rd)
562 {
563 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm];
564
565 if (p->is_write)
566 reg_to_dbg(vcpu, p, dbg_reg);
567 else
568 dbg_to_reg(vcpu, p, dbg_reg);
569
570 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg);
571
572 return true;
573 }
574
set_wcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,const struct kvm_one_reg * reg,void __user * uaddr)575 static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
576 const struct kvm_one_reg *reg, void __user *uaddr)
577 {
578 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm];
579
580 if (copy_from_user(r, uaddr, KVM_REG_SIZE(reg->id)) != 0)
581 return -EFAULT;
582 return 0;
583 }
584
get_wcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,const struct kvm_one_reg * reg,void __user * uaddr)585 static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
586 const struct kvm_one_reg *reg, void __user *uaddr)
587 {
588 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm];
589
590 if (copy_to_user(uaddr, r, KVM_REG_SIZE(reg->id)) != 0)
591 return -EFAULT;
592 return 0;
593 }
594
reset_wcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)595 static void reset_wcr(struct kvm_vcpu *vcpu,
596 const struct sys_reg_desc *rd)
597 {
598 vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm] = rd->val;
599 }
600
reset_amair_el1(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)601 static void reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
602 {
603 u64 amair = read_sysreg(amair_el1);
604 vcpu_write_sys_reg(vcpu, amair, AMAIR_EL1);
605 }
606
reset_mpidr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)607 static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
608 {
609 u64 mpidr;
610
611 /*
612 * Map the vcpu_id into the first three affinity level fields of
613 * the MPIDR. We limit the number of VCPUs in level 0 due to a
614 * limitation to 16 CPUs in that level in the ICC_SGIxR registers
615 * of the GICv3 to be able to address each CPU directly when
616 * sending IPIs.
617 */
618 mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0);
619 mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1);
620 mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2);
621 vcpu_write_sys_reg(vcpu, (1ULL << 31) | mpidr, MPIDR_EL1);
622 }
623
reset_pmcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)624 static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
625 {
626 u64 pmcr, val;
627
628 /* No PMU available, PMCR_EL0 may UNDEF... */
629 if (!kvm_arm_support_pmu_v3())
630 return;
631
632 pmcr = read_sysreg(pmcr_el0);
633 /*
634 * Writable bits of PMCR_EL0 (ARMV8_PMU_PMCR_MASK) are reset to UNKNOWN
635 * except PMCR.E resetting to zero.
636 */
637 val = ((pmcr & ~ARMV8_PMU_PMCR_MASK)
638 | (ARMV8_PMU_PMCR_MASK & 0xdecafbad)) & (~ARMV8_PMU_PMCR_E);
639 if (!system_supports_32bit_el0())
640 val |= ARMV8_PMU_PMCR_LC;
641 __vcpu_sys_reg(vcpu, r->reg) = val;
642 }
643
check_pmu_access_disabled(struct kvm_vcpu * vcpu,u64 flags)644 static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags)
645 {
646 u64 reg = __vcpu_sys_reg(vcpu, PMUSERENR_EL0);
647 bool enabled = (reg & flags) || vcpu_mode_priv(vcpu);
648
649 if (!enabled)
650 kvm_inject_undefined(vcpu);
651
652 return !enabled;
653 }
654
pmu_access_el0_disabled(struct kvm_vcpu * vcpu)655 static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu)
656 {
657 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_EN);
658 }
659
pmu_write_swinc_el0_disabled(struct kvm_vcpu * vcpu)660 static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu)
661 {
662 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN);
663 }
664
pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu * vcpu)665 static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu)
666 {
667 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN);
668 }
669
pmu_access_event_counter_el0_disabled(struct kvm_vcpu * vcpu)670 static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu)
671 {
672 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN);
673 }
674
access_pmcr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)675 static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
676 const struct sys_reg_desc *r)
677 {
678 u64 val;
679
680 if (!kvm_arm_pmu_v3_ready(vcpu))
681 return trap_raz_wi(vcpu, p, r);
682
683 if (pmu_access_el0_disabled(vcpu))
684 return false;
685
686 if (p->is_write) {
687 /* Only update writeable bits of PMCR */
688 val = __vcpu_sys_reg(vcpu, PMCR_EL0);
689 val &= ~ARMV8_PMU_PMCR_MASK;
690 val |= p->regval & ARMV8_PMU_PMCR_MASK;
691 if (!system_supports_32bit_el0())
692 val |= ARMV8_PMU_PMCR_LC;
693 __vcpu_sys_reg(vcpu, PMCR_EL0) = val;
694 kvm_pmu_handle_pmcr(vcpu, val);
695 kvm_vcpu_pmu_restore_guest(vcpu);
696 } else {
697 /* PMCR.P & PMCR.C are RAZ */
698 val = __vcpu_sys_reg(vcpu, PMCR_EL0)
699 & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C);
700 p->regval = val;
701 }
702
703 return true;
704 }
705
access_pmselr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)706 static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
707 const struct sys_reg_desc *r)
708 {
709 if (!kvm_arm_pmu_v3_ready(vcpu))
710 return trap_raz_wi(vcpu, p, r);
711
712 if (pmu_access_event_counter_el0_disabled(vcpu))
713 return false;
714
715 if (p->is_write)
716 __vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval;
717 else
718 /* return PMSELR.SEL field */
719 p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0)
720 & ARMV8_PMU_COUNTER_MASK;
721
722 return true;
723 }
724
access_pmceid(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)725 static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
726 const struct sys_reg_desc *r)
727 {
728 u64 pmceid;
729
730 if (!kvm_arm_pmu_v3_ready(vcpu))
731 return trap_raz_wi(vcpu, p, r);
732
733 BUG_ON(p->is_write);
734
735 if (pmu_access_el0_disabled(vcpu))
736 return false;
737
738 if (!(p->Op2 & 1))
739 pmceid = read_sysreg(pmceid0_el0);
740 else
741 pmceid = read_sysreg(pmceid1_el0);
742
743 p->regval = pmceid;
744
745 return true;
746 }
747
pmu_counter_idx_valid(struct kvm_vcpu * vcpu,u64 idx)748 static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx)
749 {
750 u64 pmcr, val;
751
752 pmcr = __vcpu_sys_reg(vcpu, PMCR_EL0);
753 val = (pmcr >> ARMV8_PMU_PMCR_N_SHIFT) & ARMV8_PMU_PMCR_N_MASK;
754 if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX) {
755 kvm_inject_undefined(vcpu);
756 return false;
757 }
758
759 return true;
760 }
761
access_pmu_evcntr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)762 static bool access_pmu_evcntr(struct kvm_vcpu *vcpu,
763 struct sys_reg_params *p,
764 const struct sys_reg_desc *r)
765 {
766 u64 idx;
767
768 if (!kvm_arm_pmu_v3_ready(vcpu))
769 return trap_raz_wi(vcpu, p, r);
770
771 if (r->CRn == 9 && r->CRm == 13) {
772 if (r->Op2 == 2) {
773 /* PMXEVCNTR_EL0 */
774 if (pmu_access_event_counter_el0_disabled(vcpu))
775 return false;
776
777 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0)
778 & ARMV8_PMU_COUNTER_MASK;
779 } else if (r->Op2 == 0) {
780 /* PMCCNTR_EL0 */
781 if (pmu_access_cycle_counter_el0_disabled(vcpu))
782 return false;
783
784 idx = ARMV8_PMU_CYCLE_IDX;
785 } else {
786 return false;
787 }
788 } else if (r->CRn == 0 && r->CRm == 9) {
789 /* PMCCNTR */
790 if (pmu_access_event_counter_el0_disabled(vcpu))
791 return false;
792
793 idx = ARMV8_PMU_CYCLE_IDX;
794 } else if (r->CRn == 14 && (r->CRm & 12) == 8) {
795 /* PMEVCNTRn_EL0 */
796 if (pmu_access_event_counter_el0_disabled(vcpu))
797 return false;
798
799 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
800 } else {
801 return false;
802 }
803
804 if (!pmu_counter_idx_valid(vcpu, idx))
805 return false;
806
807 if (p->is_write) {
808 if (pmu_access_el0_disabled(vcpu))
809 return false;
810
811 kvm_pmu_set_counter_value(vcpu, idx, p->regval);
812 } else {
813 p->regval = kvm_pmu_get_counter_value(vcpu, idx);
814 }
815
816 return true;
817 }
818
access_pmu_evtyper(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)819 static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
820 const struct sys_reg_desc *r)
821 {
822 u64 idx, reg;
823
824 if (!kvm_arm_pmu_v3_ready(vcpu))
825 return trap_raz_wi(vcpu, p, r);
826
827 if (pmu_access_el0_disabled(vcpu))
828 return false;
829
830 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) {
831 /* PMXEVTYPER_EL0 */
832 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_PMU_COUNTER_MASK;
833 reg = PMEVTYPER0_EL0 + idx;
834 } else if (r->CRn == 14 && (r->CRm & 12) == 12) {
835 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
836 if (idx == ARMV8_PMU_CYCLE_IDX)
837 reg = PMCCFILTR_EL0;
838 else
839 /* PMEVTYPERn_EL0 */
840 reg = PMEVTYPER0_EL0 + idx;
841 } else {
842 BUG();
843 }
844
845 if (!pmu_counter_idx_valid(vcpu, idx))
846 return false;
847
848 if (p->is_write) {
849 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx);
850 __vcpu_sys_reg(vcpu, reg) = p->regval & ARMV8_PMU_EVTYPE_MASK;
851 kvm_vcpu_pmu_restore_guest(vcpu);
852 } else {
853 p->regval = __vcpu_sys_reg(vcpu, reg) & ARMV8_PMU_EVTYPE_MASK;
854 }
855
856 return true;
857 }
858
access_pmcnten(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)859 static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
860 const struct sys_reg_desc *r)
861 {
862 u64 val, mask;
863
864 if (!kvm_arm_pmu_v3_ready(vcpu))
865 return trap_raz_wi(vcpu, p, r);
866
867 if (pmu_access_el0_disabled(vcpu))
868 return false;
869
870 mask = kvm_pmu_valid_counter_mask(vcpu);
871 if (p->is_write) {
872 val = p->regval & mask;
873 if (r->Op2 & 0x1) {
874 /* accessing PMCNTENSET_EL0 */
875 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val;
876 kvm_pmu_enable_counter_mask(vcpu, val);
877 kvm_vcpu_pmu_restore_guest(vcpu);
878 } else {
879 /* accessing PMCNTENCLR_EL0 */
880 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val;
881 kvm_pmu_disable_counter_mask(vcpu, val);
882 }
883 } else {
884 p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) & mask;
885 }
886
887 return true;
888 }
889
access_pminten(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)890 static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
891 const struct sys_reg_desc *r)
892 {
893 u64 mask = kvm_pmu_valid_counter_mask(vcpu);
894
895 if (!kvm_arm_pmu_v3_ready(vcpu))
896 return trap_raz_wi(vcpu, p, r);
897
898 if (!vcpu_mode_priv(vcpu)) {
899 kvm_inject_undefined(vcpu);
900 return false;
901 }
902
903 if (p->is_write) {
904 u64 val = p->regval & mask;
905
906 if (r->Op2 & 0x1)
907 /* accessing PMINTENSET_EL1 */
908 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val;
909 else
910 /* accessing PMINTENCLR_EL1 */
911 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val;
912 } else {
913 p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1) & mask;
914 }
915
916 return true;
917 }
918
access_pmovs(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)919 static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
920 const struct sys_reg_desc *r)
921 {
922 u64 mask = kvm_pmu_valid_counter_mask(vcpu);
923
924 if (!kvm_arm_pmu_v3_ready(vcpu))
925 return trap_raz_wi(vcpu, p, r);
926
927 if (pmu_access_el0_disabled(vcpu))
928 return false;
929
930 if (p->is_write) {
931 if (r->CRm & 0x2)
932 /* accessing PMOVSSET_EL0 */
933 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= (p->regval & mask);
934 else
935 /* accessing PMOVSCLR_EL0 */
936 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask);
937 } else {
938 p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0) & mask;
939 }
940
941 return true;
942 }
943
access_pmswinc(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)944 static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
945 const struct sys_reg_desc *r)
946 {
947 u64 mask;
948
949 if (!kvm_arm_pmu_v3_ready(vcpu))
950 return trap_raz_wi(vcpu, p, r);
951
952 if (!p->is_write)
953 return read_from_write_only(vcpu, p, r);
954
955 if (pmu_write_swinc_el0_disabled(vcpu))
956 return false;
957
958 mask = kvm_pmu_valid_counter_mask(vcpu);
959 kvm_pmu_software_increment(vcpu, p->regval & mask);
960 return true;
961 }
962
access_pmuserenr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)963 static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
964 const struct sys_reg_desc *r)
965 {
966 if (!kvm_arm_pmu_v3_ready(vcpu))
967 return trap_raz_wi(vcpu, p, r);
968
969 if (p->is_write) {
970 if (!vcpu_mode_priv(vcpu)) {
971 kvm_inject_undefined(vcpu);
972 return false;
973 }
974
975 __vcpu_sys_reg(vcpu, PMUSERENR_EL0) =
976 p->regval & ARMV8_PMU_USERENR_MASK;
977 } else {
978 p->regval = __vcpu_sys_reg(vcpu, PMUSERENR_EL0)
979 & ARMV8_PMU_USERENR_MASK;
980 }
981
982 return true;
983 }
984
985 #define reg_to_encoding(x) \
986 sys_reg((u32)(x)->Op0, (u32)(x)->Op1, \
987 (u32)(x)->CRn, (u32)(x)->CRm, (u32)(x)->Op2);
988
989 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
990 #define DBG_BCR_BVR_WCR_WVR_EL1(n) \
991 { SYS_DESC(SYS_DBGBVRn_EL1(n)), \
992 trap_bvr, reset_bvr, 0, 0, get_bvr, set_bvr }, \
993 { SYS_DESC(SYS_DBGBCRn_EL1(n)), \
994 trap_bcr, reset_bcr, 0, 0, get_bcr, set_bcr }, \
995 { SYS_DESC(SYS_DBGWVRn_EL1(n)), \
996 trap_wvr, reset_wvr, 0, 0, get_wvr, set_wvr }, \
997 { SYS_DESC(SYS_DBGWCRn_EL1(n)), \
998 trap_wcr, reset_wcr, 0, 0, get_wcr, set_wcr }
999
1000 /* Macro to expand the PMEVCNTRn_EL0 register */
1001 #define PMU_PMEVCNTR_EL0(n) \
1002 { SYS_DESC(SYS_PMEVCNTRn_EL0(n)), \
1003 access_pmu_evcntr, reset_unknown, (PMEVCNTR0_EL0 + n), }
1004
1005 /* Macro to expand the PMEVTYPERn_EL0 register */
1006 #define PMU_PMEVTYPER_EL0(n) \
1007 { SYS_DESC(SYS_PMEVTYPERn_EL0(n)), \
1008 access_pmu_evtyper, reset_unknown, (PMEVTYPER0_EL0 + n), }
1009
access_amu(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1010 static bool access_amu(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1011 const struct sys_reg_desc *r)
1012 {
1013 kvm_inject_undefined(vcpu);
1014
1015 return false;
1016 }
1017
1018 /* Macro to expand the AMU counter and type registers*/
1019 #define AMU_AMEVCNTR0_EL0(n) { SYS_DESC(SYS_AMEVCNTR0_EL0(n)), access_amu }
1020 #define AMU_AMEVTYPE0_EL0(n) { SYS_DESC(SYS_AMEVTYPE0_EL0(n)), access_amu }
1021 #define AMU_AMEVCNTR1_EL0(n) { SYS_DESC(SYS_AMEVCNTR1_EL0(n)), access_amu }
1022 #define AMU_AMEVTYPE1_EL0(n) { SYS_DESC(SYS_AMEVTYPE1_EL0(n)), access_amu }
1023
trap_ptrauth(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * rd)1024 static bool trap_ptrauth(struct kvm_vcpu *vcpu,
1025 struct sys_reg_params *p,
1026 const struct sys_reg_desc *rd)
1027 {
1028 kvm_arm_vcpu_ptrauth_trap(vcpu);
1029
1030 /*
1031 * Return false for both cases as we never skip the trapped
1032 * instruction:
1033 *
1034 * - Either we re-execute the same key register access instruction
1035 * after enabling ptrauth.
1036 * - Or an UNDEF is injected as ptrauth is not supported/enabled.
1037 */
1038 return false;
1039 }
1040
ptrauth_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)1041 static unsigned int ptrauth_visibility(const struct kvm_vcpu *vcpu,
1042 const struct sys_reg_desc *rd)
1043 {
1044 return vcpu_has_ptrauth(vcpu) ? 0 : REG_HIDDEN_USER | REG_HIDDEN_GUEST;
1045 }
1046
1047 #define __PTRAUTH_KEY(k) \
1048 { SYS_DESC(SYS_## k), trap_ptrauth, reset_unknown, k, \
1049 .visibility = ptrauth_visibility}
1050
1051 #define PTRAUTH_KEY(k) \
1052 __PTRAUTH_KEY(k ## KEYLO_EL1), \
1053 __PTRAUTH_KEY(k ## KEYHI_EL1)
1054
access_arch_timer(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1055 static bool access_arch_timer(struct kvm_vcpu *vcpu,
1056 struct sys_reg_params *p,
1057 const struct sys_reg_desc *r)
1058 {
1059 enum kvm_arch_timers tmr;
1060 enum kvm_arch_timer_regs treg;
1061 u64 reg = reg_to_encoding(r);
1062
1063 switch (reg) {
1064 case SYS_CNTP_TVAL_EL0:
1065 case SYS_AARCH32_CNTP_TVAL:
1066 tmr = TIMER_PTIMER;
1067 treg = TIMER_REG_TVAL;
1068 break;
1069 case SYS_CNTP_CTL_EL0:
1070 case SYS_AARCH32_CNTP_CTL:
1071 tmr = TIMER_PTIMER;
1072 treg = TIMER_REG_CTL;
1073 break;
1074 case SYS_CNTP_CVAL_EL0:
1075 case SYS_AARCH32_CNTP_CVAL:
1076 tmr = TIMER_PTIMER;
1077 treg = TIMER_REG_CVAL;
1078 break;
1079 default:
1080 BUG();
1081 }
1082
1083 if (p->is_write)
1084 kvm_arm_timer_write_sysreg(vcpu, tmr, treg, p->regval);
1085 else
1086 p->regval = kvm_arm_timer_read_sysreg(vcpu, tmr, treg);
1087
1088 return true;
1089 }
1090
1091 /* Read a sanitised cpufeature ID register by sys_reg_desc */
read_id_reg(const struct kvm_vcpu * vcpu,struct sys_reg_desc const * r,bool raz)1092 static u64 read_id_reg(const struct kvm_vcpu *vcpu,
1093 struct sys_reg_desc const *r, bool raz)
1094 {
1095 u32 id = sys_reg((u32)r->Op0, (u32)r->Op1,
1096 (u32)r->CRn, (u32)r->CRm, (u32)r->Op2);
1097 u64 val = raz ? 0 : read_sanitised_ftr_reg(id);
1098
1099 if (id == SYS_ID_AA64PFR0_EL1) {
1100 if (!vcpu_has_sve(vcpu))
1101 val &= ~(0xfUL << ID_AA64PFR0_SVE_SHIFT);
1102 val &= ~(0xfUL << ID_AA64PFR0_AMU_SHIFT);
1103 } else if (id == SYS_ID_AA64ISAR1_EL1 && !vcpu_has_ptrauth(vcpu)) {
1104 val &= ~((0xfUL << ID_AA64ISAR1_APA_SHIFT) |
1105 (0xfUL << ID_AA64ISAR1_API_SHIFT) |
1106 (0xfUL << ID_AA64ISAR1_GPA_SHIFT) |
1107 (0xfUL << ID_AA64ISAR1_GPI_SHIFT));
1108 } else if (id == SYS_ID_AA64DFR0_EL1) {
1109 /* Limit guests to PMUv3 for ARMv8.1 */
1110 val = cpuid_feature_cap_perfmon_field(val,
1111 ID_AA64DFR0_PMUVER_SHIFT,
1112 ID_AA64DFR0_PMUVER_8_1);
1113 } else if (id == SYS_ID_DFR0_EL1) {
1114 /* Limit guests to PMUv3 for ARMv8.1 */
1115 val = cpuid_feature_cap_perfmon_field(val,
1116 ID_DFR0_PERFMON_SHIFT,
1117 ID_DFR0_PERFMON_8_1);
1118 }
1119
1120 return val;
1121 }
1122
1123 /* cpufeature ID register access trap handlers */
1124
__access_id_reg(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r,bool raz)1125 static bool __access_id_reg(struct kvm_vcpu *vcpu,
1126 struct sys_reg_params *p,
1127 const struct sys_reg_desc *r,
1128 bool raz)
1129 {
1130 if (p->is_write)
1131 return write_to_read_only(vcpu, p, r);
1132
1133 p->regval = read_id_reg(vcpu, r, raz);
1134 return true;
1135 }
1136
access_id_reg(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1137 static bool access_id_reg(struct kvm_vcpu *vcpu,
1138 struct sys_reg_params *p,
1139 const struct sys_reg_desc *r)
1140 {
1141 return __access_id_reg(vcpu, p, r, false);
1142 }
1143
access_raz_id_reg(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1144 static bool access_raz_id_reg(struct kvm_vcpu *vcpu,
1145 struct sys_reg_params *p,
1146 const struct sys_reg_desc *r)
1147 {
1148 return __access_id_reg(vcpu, p, r, true);
1149 }
1150
1151 static int reg_from_user(u64 *val, const void __user *uaddr, u64 id);
1152 static int reg_to_user(void __user *uaddr, const u64 *val, u64 id);
1153 static u64 sys_reg_to_index(const struct sys_reg_desc *reg);
1154
1155 /* Visibility overrides for SVE-specific control registers */
sve_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)1156 static unsigned int sve_visibility(const struct kvm_vcpu *vcpu,
1157 const struct sys_reg_desc *rd)
1158 {
1159 if (vcpu_has_sve(vcpu))
1160 return 0;
1161
1162 return REG_HIDDEN_USER | REG_HIDDEN_GUEST;
1163 }
1164
1165 /* Generate the emulated ID_AA64ZFR0_EL1 value exposed to the guest */
guest_id_aa64zfr0_el1(const struct kvm_vcpu * vcpu)1166 static u64 guest_id_aa64zfr0_el1(const struct kvm_vcpu *vcpu)
1167 {
1168 if (!vcpu_has_sve(vcpu))
1169 return 0;
1170
1171 return read_sanitised_ftr_reg(SYS_ID_AA64ZFR0_EL1);
1172 }
1173
access_id_aa64zfr0_el1(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * rd)1174 static bool access_id_aa64zfr0_el1(struct kvm_vcpu *vcpu,
1175 struct sys_reg_params *p,
1176 const struct sys_reg_desc *rd)
1177 {
1178 if (p->is_write)
1179 return write_to_read_only(vcpu, p, rd);
1180
1181 p->regval = guest_id_aa64zfr0_el1(vcpu);
1182 return true;
1183 }
1184
get_id_aa64zfr0_el1(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,const struct kvm_one_reg * reg,void __user * uaddr)1185 static int get_id_aa64zfr0_el1(struct kvm_vcpu *vcpu,
1186 const struct sys_reg_desc *rd,
1187 const struct kvm_one_reg *reg, void __user *uaddr)
1188 {
1189 u64 val;
1190
1191 val = guest_id_aa64zfr0_el1(vcpu);
1192 return reg_to_user(uaddr, &val, reg->id);
1193 }
1194
set_id_aa64zfr0_el1(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,const struct kvm_one_reg * reg,void __user * uaddr)1195 static int set_id_aa64zfr0_el1(struct kvm_vcpu *vcpu,
1196 const struct sys_reg_desc *rd,
1197 const struct kvm_one_reg *reg, void __user *uaddr)
1198 {
1199 const u64 id = sys_reg_to_index(rd);
1200 int err;
1201 u64 val;
1202
1203 err = reg_from_user(&val, uaddr, id);
1204 if (err)
1205 return err;
1206
1207 /* This is what we mean by invariant: you can't change it. */
1208 if (val != guest_id_aa64zfr0_el1(vcpu))
1209 return -EINVAL;
1210
1211 return 0;
1212 }
1213
1214 /*
1215 * cpufeature ID register user accessors
1216 *
1217 * For now, these registers are immutable for userspace, so no values
1218 * are stored, and for set_id_reg() we don't allow the effective value
1219 * to be changed.
1220 */
__get_id_reg(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,void __user * uaddr,bool raz)1221 static int __get_id_reg(const struct kvm_vcpu *vcpu,
1222 const struct sys_reg_desc *rd, void __user *uaddr,
1223 bool raz)
1224 {
1225 const u64 id = sys_reg_to_index(rd);
1226 const u64 val = read_id_reg(vcpu, rd, raz);
1227
1228 return reg_to_user(uaddr, &val, id);
1229 }
1230
__set_id_reg(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,void __user * uaddr,bool raz)1231 static int __set_id_reg(const struct kvm_vcpu *vcpu,
1232 const struct sys_reg_desc *rd, void __user *uaddr,
1233 bool raz)
1234 {
1235 const u64 id = sys_reg_to_index(rd);
1236 int err;
1237 u64 val;
1238
1239 err = reg_from_user(&val, uaddr, id);
1240 if (err)
1241 return err;
1242
1243 /* This is what we mean by invariant: you can't change it. */
1244 if (val != read_id_reg(vcpu, rd, raz))
1245 return -EINVAL;
1246
1247 return 0;
1248 }
1249
get_id_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,const struct kvm_one_reg * reg,void __user * uaddr)1250 static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1251 const struct kvm_one_reg *reg, void __user *uaddr)
1252 {
1253 return __get_id_reg(vcpu, rd, uaddr, false);
1254 }
1255
set_id_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,const struct kvm_one_reg * reg,void __user * uaddr)1256 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1257 const struct kvm_one_reg *reg, void __user *uaddr)
1258 {
1259 return __set_id_reg(vcpu, rd, uaddr, false);
1260 }
1261
get_raz_id_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,const struct kvm_one_reg * reg,void __user * uaddr)1262 static int get_raz_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1263 const struct kvm_one_reg *reg, void __user *uaddr)
1264 {
1265 return __get_id_reg(vcpu, rd, uaddr, true);
1266 }
1267
set_raz_id_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,const struct kvm_one_reg * reg,void __user * uaddr)1268 static int set_raz_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1269 const struct kvm_one_reg *reg, void __user *uaddr)
1270 {
1271 return __set_id_reg(vcpu, rd, uaddr, true);
1272 }
1273
access_ctr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1274 static bool access_ctr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1275 const struct sys_reg_desc *r)
1276 {
1277 if (p->is_write)
1278 return write_to_read_only(vcpu, p, r);
1279
1280 p->regval = read_sanitised_ftr_reg(SYS_CTR_EL0);
1281 return true;
1282 }
1283
access_clidr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1284 static bool access_clidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1285 const struct sys_reg_desc *r)
1286 {
1287 if (p->is_write)
1288 return write_to_read_only(vcpu, p, r);
1289
1290 p->regval = read_sysreg(clidr_el1);
1291 return true;
1292 }
1293
access_csselr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1294 static bool access_csselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1295 const struct sys_reg_desc *r)
1296 {
1297 int reg = r->reg;
1298
1299 /* See the 32bit mapping in kvm_host.h */
1300 if (p->is_aarch32)
1301 reg = r->reg / 2;
1302
1303 if (p->is_write)
1304 vcpu_write_sys_reg(vcpu, p->regval, reg);
1305 else
1306 p->regval = vcpu_read_sys_reg(vcpu, reg);
1307 return true;
1308 }
1309
access_ccsidr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1310 static bool access_ccsidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1311 const struct sys_reg_desc *r)
1312 {
1313 u32 csselr;
1314
1315 if (p->is_write)
1316 return write_to_read_only(vcpu, p, r);
1317
1318 csselr = vcpu_read_sys_reg(vcpu, CSSELR_EL1);
1319 p->regval = get_ccsidr(csselr);
1320
1321 /*
1322 * Guests should not be doing cache operations by set/way at all, and
1323 * for this reason, we trap them and attempt to infer the intent, so
1324 * that we can flush the entire guest's address space at the appropriate
1325 * time.
1326 * To prevent this trapping from causing performance problems, let's
1327 * expose the geometry of all data and unified caches (which are
1328 * guaranteed to be PIPT and thus non-aliasing) as 1 set and 1 way.
1329 * [If guests should attempt to infer aliasing properties from the
1330 * geometry (which is not permitted by the architecture), they would
1331 * only do so for virtually indexed caches.]
1332 */
1333 if (!(csselr & 1)) // data or unified cache
1334 p->regval &= ~GENMASK(27, 3);
1335 return true;
1336 }
1337
1338 /* sys_reg_desc initialiser for known cpufeature ID registers */
1339 #define ID_SANITISED(name) { \
1340 SYS_DESC(SYS_##name), \
1341 .access = access_id_reg, \
1342 .get_user = get_id_reg, \
1343 .set_user = set_id_reg, \
1344 }
1345
1346 /*
1347 * sys_reg_desc initialiser for architecturally unallocated cpufeature ID
1348 * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2
1349 * (1 <= crm < 8, 0 <= Op2 < 8).
1350 */
1351 #define ID_UNALLOCATED(crm, op2) { \
1352 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \
1353 .access = access_raz_id_reg, \
1354 .get_user = get_raz_id_reg, \
1355 .set_user = set_raz_id_reg, \
1356 }
1357
1358 /*
1359 * sys_reg_desc initialiser for known ID registers that we hide from guests.
1360 * For now, these are exposed just like unallocated ID regs: they appear
1361 * RAZ for the guest.
1362 */
1363 #define ID_HIDDEN(name) { \
1364 SYS_DESC(SYS_##name), \
1365 .access = access_raz_id_reg, \
1366 .get_user = get_raz_id_reg, \
1367 .set_user = set_raz_id_reg, \
1368 }
1369
1370 /*
1371 * Architected system registers.
1372 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
1373 *
1374 * Debug handling: We do trap most, if not all debug related system
1375 * registers. The implementation is good enough to ensure that a guest
1376 * can use these with minimal performance degradation. The drawback is
1377 * that we don't implement any of the external debug, none of the
1378 * OSlock protocol. This should be revisited if we ever encounter a
1379 * more demanding guest...
1380 */
1381 static const struct sys_reg_desc sys_reg_descs[] = {
1382 { SYS_DESC(SYS_DC_ISW), access_dcsw },
1383 { SYS_DESC(SYS_DC_CSW), access_dcsw },
1384 { SYS_DESC(SYS_DC_CISW), access_dcsw },
1385
1386 DBG_BCR_BVR_WCR_WVR_EL1(0),
1387 DBG_BCR_BVR_WCR_WVR_EL1(1),
1388 { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 },
1389 { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 },
1390 DBG_BCR_BVR_WCR_WVR_EL1(2),
1391 DBG_BCR_BVR_WCR_WVR_EL1(3),
1392 DBG_BCR_BVR_WCR_WVR_EL1(4),
1393 DBG_BCR_BVR_WCR_WVR_EL1(5),
1394 DBG_BCR_BVR_WCR_WVR_EL1(6),
1395 DBG_BCR_BVR_WCR_WVR_EL1(7),
1396 DBG_BCR_BVR_WCR_WVR_EL1(8),
1397 DBG_BCR_BVR_WCR_WVR_EL1(9),
1398 DBG_BCR_BVR_WCR_WVR_EL1(10),
1399 DBG_BCR_BVR_WCR_WVR_EL1(11),
1400 DBG_BCR_BVR_WCR_WVR_EL1(12),
1401 DBG_BCR_BVR_WCR_WVR_EL1(13),
1402 DBG_BCR_BVR_WCR_WVR_EL1(14),
1403 DBG_BCR_BVR_WCR_WVR_EL1(15),
1404
1405 { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi },
1406 { SYS_DESC(SYS_OSLAR_EL1), trap_raz_wi },
1407 { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1 },
1408 { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi },
1409 { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi },
1410 { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi },
1411 { SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi },
1412 { SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 },
1413
1414 { SYS_DESC(SYS_MDCCSR_EL0), trap_raz_wi },
1415 { SYS_DESC(SYS_DBGDTR_EL0), trap_raz_wi },
1416 // DBGDTR[TR]X_EL0 share the same encoding
1417 { SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi },
1418
1419 { SYS_DESC(SYS_DBGVCR32_EL2), NULL, reset_val, DBGVCR32_EL2, 0 },
1420
1421 { SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 },
1422
1423 /*
1424 * ID regs: all ID_SANITISED() entries here must have corresponding
1425 * entries in arm64_ftr_regs[].
1426 */
1427
1428 /* AArch64 mappings of the AArch32 ID registers */
1429 /* CRm=1 */
1430 ID_SANITISED(ID_PFR0_EL1),
1431 ID_SANITISED(ID_PFR1_EL1),
1432 ID_SANITISED(ID_DFR0_EL1),
1433 ID_HIDDEN(ID_AFR0_EL1),
1434 ID_SANITISED(ID_MMFR0_EL1),
1435 ID_SANITISED(ID_MMFR1_EL1),
1436 ID_SANITISED(ID_MMFR2_EL1),
1437 ID_SANITISED(ID_MMFR3_EL1),
1438
1439 /* CRm=2 */
1440 ID_SANITISED(ID_ISAR0_EL1),
1441 ID_SANITISED(ID_ISAR1_EL1),
1442 ID_SANITISED(ID_ISAR2_EL1),
1443 ID_SANITISED(ID_ISAR3_EL1),
1444 ID_SANITISED(ID_ISAR4_EL1),
1445 ID_SANITISED(ID_ISAR5_EL1),
1446 ID_SANITISED(ID_MMFR4_EL1),
1447 ID_UNALLOCATED(2,7),
1448
1449 /* CRm=3 */
1450 ID_SANITISED(MVFR0_EL1),
1451 ID_SANITISED(MVFR1_EL1),
1452 ID_SANITISED(MVFR2_EL1),
1453 ID_UNALLOCATED(3,3),
1454 ID_UNALLOCATED(3,4),
1455 ID_UNALLOCATED(3,5),
1456 ID_UNALLOCATED(3,6),
1457 ID_UNALLOCATED(3,7),
1458
1459 /* AArch64 ID registers */
1460 /* CRm=4 */
1461 ID_SANITISED(ID_AA64PFR0_EL1),
1462 ID_SANITISED(ID_AA64PFR1_EL1),
1463 ID_UNALLOCATED(4,2),
1464 ID_UNALLOCATED(4,3),
1465 { SYS_DESC(SYS_ID_AA64ZFR0_EL1), access_id_aa64zfr0_el1, .get_user = get_id_aa64zfr0_el1, .set_user = set_id_aa64zfr0_el1, },
1466 ID_UNALLOCATED(4,5),
1467 ID_UNALLOCATED(4,6),
1468 ID_UNALLOCATED(4,7),
1469
1470 /* CRm=5 */
1471 ID_SANITISED(ID_AA64DFR0_EL1),
1472 ID_SANITISED(ID_AA64DFR1_EL1),
1473 ID_UNALLOCATED(5,2),
1474 ID_UNALLOCATED(5,3),
1475 ID_HIDDEN(ID_AA64AFR0_EL1),
1476 ID_HIDDEN(ID_AA64AFR1_EL1),
1477 ID_UNALLOCATED(5,6),
1478 ID_UNALLOCATED(5,7),
1479
1480 /* CRm=6 */
1481 ID_SANITISED(ID_AA64ISAR0_EL1),
1482 ID_SANITISED(ID_AA64ISAR1_EL1),
1483 ID_SANITISED(ID_AA64ISAR2_EL1),
1484 ID_UNALLOCATED(6,3),
1485 ID_UNALLOCATED(6,4),
1486 ID_UNALLOCATED(6,5),
1487 ID_UNALLOCATED(6,6),
1488 ID_UNALLOCATED(6,7),
1489
1490 /* CRm=7 */
1491 ID_SANITISED(ID_AA64MMFR0_EL1),
1492 ID_SANITISED(ID_AA64MMFR1_EL1),
1493 ID_SANITISED(ID_AA64MMFR2_EL1),
1494 ID_UNALLOCATED(7,3),
1495 ID_UNALLOCATED(7,4),
1496 ID_UNALLOCATED(7,5),
1497 ID_UNALLOCATED(7,6),
1498 ID_UNALLOCATED(7,7),
1499
1500 { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 },
1501 { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 },
1502 { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility },
1503 { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 },
1504 { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 },
1505 { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 },
1506
1507 PTRAUTH_KEY(APIA),
1508 PTRAUTH_KEY(APIB),
1509 PTRAUTH_KEY(APDA),
1510 PTRAUTH_KEY(APDB),
1511 PTRAUTH_KEY(APGA),
1512
1513 { SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 },
1514 { SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 },
1515 { SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 },
1516
1517 { SYS_DESC(SYS_ERRIDR_EL1), trap_raz_wi },
1518 { SYS_DESC(SYS_ERRSELR_EL1), trap_raz_wi },
1519 { SYS_DESC(SYS_ERXFR_EL1), trap_raz_wi },
1520 { SYS_DESC(SYS_ERXCTLR_EL1), trap_raz_wi },
1521 { SYS_DESC(SYS_ERXSTATUS_EL1), trap_raz_wi },
1522 { SYS_DESC(SYS_ERXADDR_EL1), trap_raz_wi },
1523 { SYS_DESC(SYS_ERXMISC0_EL1), trap_raz_wi },
1524 { SYS_DESC(SYS_ERXMISC1_EL1), trap_raz_wi },
1525
1526 { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 },
1527 { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 },
1528
1529 { SYS_DESC(SYS_PMINTENSET_EL1), access_pminten, reset_unknown, PMINTENSET_EL1 },
1530 { SYS_DESC(SYS_PMINTENCLR_EL1), access_pminten, NULL, PMINTENSET_EL1 },
1531
1532 { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 },
1533 { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 },
1534
1535 { SYS_DESC(SYS_LORSA_EL1), trap_loregion },
1536 { SYS_DESC(SYS_LOREA_EL1), trap_loregion },
1537 { SYS_DESC(SYS_LORN_EL1), trap_loregion },
1538 { SYS_DESC(SYS_LORC_EL1), trap_loregion },
1539 { SYS_DESC(SYS_LORID_EL1), trap_loregion },
1540
1541 { SYS_DESC(SYS_VBAR_EL1), NULL, reset_val, VBAR_EL1, 0 },
1542 { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 },
1543
1544 { SYS_DESC(SYS_ICC_IAR0_EL1), write_to_read_only },
1545 { SYS_DESC(SYS_ICC_EOIR0_EL1), read_from_write_only },
1546 { SYS_DESC(SYS_ICC_HPPIR0_EL1), write_to_read_only },
1547 { SYS_DESC(SYS_ICC_DIR_EL1), read_from_write_only },
1548 { SYS_DESC(SYS_ICC_RPR_EL1), write_to_read_only },
1549 { SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi },
1550 { SYS_DESC(SYS_ICC_ASGI1R_EL1), access_gic_sgi },
1551 { SYS_DESC(SYS_ICC_SGI0R_EL1), access_gic_sgi },
1552 { SYS_DESC(SYS_ICC_IAR1_EL1), write_to_read_only },
1553 { SYS_DESC(SYS_ICC_EOIR1_EL1), read_from_write_only },
1554 { SYS_DESC(SYS_ICC_HPPIR1_EL1), write_to_read_only },
1555 { SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre },
1556
1557 { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 },
1558 { SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 },
1559
1560 { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0},
1561
1562 { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr },
1563 { SYS_DESC(SYS_CLIDR_EL1), access_clidr },
1564 { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 },
1565 { SYS_DESC(SYS_CTR_EL0), access_ctr },
1566
1567 { SYS_DESC(SYS_PMCR_EL0), access_pmcr, reset_pmcr, PMCR_EL0 },
1568 { SYS_DESC(SYS_PMCNTENSET_EL0), access_pmcnten, reset_unknown, PMCNTENSET_EL0 },
1569 { SYS_DESC(SYS_PMCNTENCLR_EL0), access_pmcnten, NULL, PMCNTENSET_EL0 },
1570 { SYS_DESC(SYS_PMOVSCLR_EL0), access_pmovs, NULL, PMOVSSET_EL0 },
1571 { SYS_DESC(SYS_PMSWINC_EL0), access_pmswinc, reset_unknown, PMSWINC_EL0 },
1572 { SYS_DESC(SYS_PMSELR_EL0), access_pmselr, reset_unknown, PMSELR_EL0 },
1573 { SYS_DESC(SYS_PMCEID0_EL0), access_pmceid },
1574 { SYS_DESC(SYS_PMCEID1_EL0), access_pmceid },
1575 { SYS_DESC(SYS_PMCCNTR_EL0), access_pmu_evcntr, reset_unknown, PMCCNTR_EL0 },
1576 { SYS_DESC(SYS_PMXEVTYPER_EL0), access_pmu_evtyper },
1577 { SYS_DESC(SYS_PMXEVCNTR_EL0), access_pmu_evcntr },
1578 /*
1579 * PMUSERENR_EL0 resets as unknown in 64bit mode while it resets as zero
1580 * in 32bit mode. Here we choose to reset it as zero for consistency.
1581 */
1582 { SYS_DESC(SYS_PMUSERENR_EL0), access_pmuserenr, reset_val, PMUSERENR_EL0, 0 },
1583 { SYS_DESC(SYS_PMOVSSET_EL0), access_pmovs, reset_unknown, PMOVSSET_EL0 },
1584
1585 { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 },
1586 { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 },
1587
1588 { SYS_DESC(SYS_AMCR_EL0), access_amu },
1589 { SYS_DESC(SYS_AMCFGR_EL0), access_amu },
1590 { SYS_DESC(SYS_AMCGCR_EL0), access_amu },
1591 { SYS_DESC(SYS_AMUSERENR_EL0), access_amu },
1592 { SYS_DESC(SYS_AMCNTENCLR0_EL0), access_amu },
1593 { SYS_DESC(SYS_AMCNTENSET0_EL0), access_amu },
1594 { SYS_DESC(SYS_AMCNTENCLR1_EL0), access_amu },
1595 { SYS_DESC(SYS_AMCNTENSET1_EL0), access_amu },
1596 AMU_AMEVCNTR0_EL0(0),
1597 AMU_AMEVCNTR0_EL0(1),
1598 AMU_AMEVCNTR0_EL0(2),
1599 AMU_AMEVCNTR0_EL0(3),
1600 AMU_AMEVCNTR0_EL0(4),
1601 AMU_AMEVCNTR0_EL0(5),
1602 AMU_AMEVCNTR0_EL0(6),
1603 AMU_AMEVCNTR0_EL0(7),
1604 AMU_AMEVCNTR0_EL0(8),
1605 AMU_AMEVCNTR0_EL0(9),
1606 AMU_AMEVCNTR0_EL0(10),
1607 AMU_AMEVCNTR0_EL0(11),
1608 AMU_AMEVCNTR0_EL0(12),
1609 AMU_AMEVCNTR0_EL0(13),
1610 AMU_AMEVCNTR0_EL0(14),
1611 AMU_AMEVCNTR0_EL0(15),
1612 AMU_AMEVTYPE0_EL0(0),
1613 AMU_AMEVTYPE0_EL0(1),
1614 AMU_AMEVTYPE0_EL0(2),
1615 AMU_AMEVTYPE0_EL0(3),
1616 AMU_AMEVTYPE0_EL0(4),
1617 AMU_AMEVTYPE0_EL0(5),
1618 AMU_AMEVTYPE0_EL0(6),
1619 AMU_AMEVTYPE0_EL0(7),
1620 AMU_AMEVTYPE0_EL0(8),
1621 AMU_AMEVTYPE0_EL0(9),
1622 AMU_AMEVTYPE0_EL0(10),
1623 AMU_AMEVTYPE0_EL0(11),
1624 AMU_AMEVTYPE0_EL0(12),
1625 AMU_AMEVTYPE0_EL0(13),
1626 AMU_AMEVTYPE0_EL0(14),
1627 AMU_AMEVTYPE0_EL0(15),
1628 AMU_AMEVCNTR1_EL0(0),
1629 AMU_AMEVCNTR1_EL0(1),
1630 AMU_AMEVCNTR1_EL0(2),
1631 AMU_AMEVCNTR1_EL0(3),
1632 AMU_AMEVCNTR1_EL0(4),
1633 AMU_AMEVCNTR1_EL0(5),
1634 AMU_AMEVCNTR1_EL0(6),
1635 AMU_AMEVCNTR1_EL0(7),
1636 AMU_AMEVCNTR1_EL0(8),
1637 AMU_AMEVCNTR1_EL0(9),
1638 AMU_AMEVCNTR1_EL0(10),
1639 AMU_AMEVCNTR1_EL0(11),
1640 AMU_AMEVCNTR1_EL0(12),
1641 AMU_AMEVCNTR1_EL0(13),
1642 AMU_AMEVCNTR1_EL0(14),
1643 AMU_AMEVCNTR1_EL0(15),
1644 AMU_AMEVTYPE1_EL0(0),
1645 AMU_AMEVTYPE1_EL0(1),
1646 AMU_AMEVTYPE1_EL0(2),
1647 AMU_AMEVTYPE1_EL0(3),
1648 AMU_AMEVTYPE1_EL0(4),
1649 AMU_AMEVTYPE1_EL0(5),
1650 AMU_AMEVTYPE1_EL0(6),
1651 AMU_AMEVTYPE1_EL0(7),
1652 AMU_AMEVTYPE1_EL0(8),
1653 AMU_AMEVTYPE1_EL0(9),
1654 AMU_AMEVTYPE1_EL0(10),
1655 AMU_AMEVTYPE1_EL0(11),
1656 AMU_AMEVTYPE1_EL0(12),
1657 AMU_AMEVTYPE1_EL0(13),
1658 AMU_AMEVTYPE1_EL0(14),
1659 AMU_AMEVTYPE1_EL0(15),
1660
1661 { SYS_DESC(SYS_CNTP_TVAL_EL0), access_arch_timer },
1662 { SYS_DESC(SYS_CNTP_CTL_EL0), access_arch_timer },
1663 { SYS_DESC(SYS_CNTP_CVAL_EL0), access_arch_timer },
1664
1665 /* PMEVCNTRn_EL0 */
1666 PMU_PMEVCNTR_EL0(0),
1667 PMU_PMEVCNTR_EL0(1),
1668 PMU_PMEVCNTR_EL0(2),
1669 PMU_PMEVCNTR_EL0(3),
1670 PMU_PMEVCNTR_EL0(4),
1671 PMU_PMEVCNTR_EL0(5),
1672 PMU_PMEVCNTR_EL0(6),
1673 PMU_PMEVCNTR_EL0(7),
1674 PMU_PMEVCNTR_EL0(8),
1675 PMU_PMEVCNTR_EL0(9),
1676 PMU_PMEVCNTR_EL0(10),
1677 PMU_PMEVCNTR_EL0(11),
1678 PMU_PMEVCNTR_EL0(12),
1679 PMU_PMEVCNTR_EL0(13),
1680 PMU_PMEVCNTR_EL0(14),
1681 PMU_PMEVCNTR_EL0(15),
1682 PMU_PMEVCNTR_EL0(16),
1683 PMU_PMEVCNTR_EL0(17),
1684 PMU_PMEVCNTR_EL0(18),
1685 PMU_PMEVCNTR_EL0(19),
1686 PMU_PMEVCNTR_EL0(20),
1687 PMU_PMEVCNTR_EL0(21),
1688 PMU_PMEVCNTR_EL0(22),
1689 PMU_PMEVCNTR_EL0(23),
1690 PMU_PMEVCNTR_EL0(24),
1691 PMU_PMEVCNTR_EL0(25),
1692 PMU_PMEVCNTR_EL0(26),
1693 PMU_PMEVCNTR_EL0(27),
1694 PMU_PMEVCNTR_EL0(28),
1695 PMU_PMEVCNTR_EL0(29),
1696 PMU_PMEVCNTR_EL0(30),
1697 /* PMEVTYPERn_EL0 */
1698 PMU_PMEVTYPER_EL0(0),
1699 PMU_PMEVTYPER_EL0(1),
1700 PMU_PMEVTYPER_EL0(2),
1701 PMU_PMEVTYPER_EL0(3),
1702 PMU_PMEVTYPER_EL0(4),
1703 PMU_PMEVTYPER_EL0(5),
1704 PMU_PMEVTYPER_EL0(6),
1705 PMU_PMEVTYPER_EL0(7),
1706 PMU_PMEVTYPER_EL0(8),
1707 PMU_PMEVTYPER_EL0(9),
1708 PMU_PMEVTYPER_EL0(10),
1709 PMU_PMEVTYPER_EL0(11),
1710 PMU_PMEVTYPER_EL0(12),
1711 PMU_PMEVTYPER_EL0(13),
1712 PMU_PMEVTYPER_EL0(14),
1713 PMU_PMEVTYPER_EL0(15),
1714 PMU_PMEVTYPER_EL0(16),
1715 PMU_PMEVTYPER_EL0(17),
1716 PMU_PMEVTYPER_EL0(18),
1717 PMU_PMEVTYPER_EL0(19),
1718 PMU_PMEVTYPER_EL0(20),
1719 PMU_PMEVTYPER_EL0(21),
1720 PMU_PMEVTYPER_EL0(22),
1721 PMU_PMEVTYPER_EL0(23),
1722 PMU_PMEVTYPER_EL0(24),
1723 PMU_PMEVTYPER_EL0(25),
1724 PMU_PMEVTYPER_EL0(26),
1725 PMU_PMEVTYPER_EL0(27),
1726 PMU_PMEVTYPER_EL0(28),
1727 PMU_PMEVTYPER_EL0(29),
1728 PMU_PMEVTYPER_EL0(30),
1729 /*
1730 * PMCCFILTR_EL0 resets as unknown in 64bit mode while it resets as zero
1731 * in 32bit mode. Here we choose to reset it as zero for consistency.
1732 */
1733 { SYS_DESC(SYS_PMCCFILTR_EL0), access_pmu_evtyper, reset_val, PMCCFILTR_EL0, 0 },
1734
1735 { SYS_DESC(SYS_DACR32_EL2), NULL, reset_unknown, DACR32_EL2 },
1736 { SYS_DESC(SYS_IFSR32_EL2), NULL, reset_unknown, IFSR32_EL2 },
1737 { SYS_DESC(SYS_FPEXC32_EL2), NULL, reset_val, FPEXC32_EL2, 0x700 },
1738 };
1739
trap_dbgidr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1740 static bool trap_dbgidr(struct kvm_vcpu *vcpu,
1741 struct sys_reg_params *p,
1742 const struct sys_reg_desc *r)
1743 {
1744 if (p->is_write) {
1745 return ignore_write(vcpu, p);
1746 } else {
1747 u64 dfr = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1);
1748 u64 pfr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
1749 u32 el3 = !!cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR0_EL3_SHIFT);
1750
1751 p->regval = ((((dfr >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) << 28) |
1752 (((dfr >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) << 24) |
1753 (((dfr >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) << 20)
1754 | (6 << 16) | (el3 << 14) | (el3 << 12));
1755 return true;
1756 }
1757 }
1758
trap_debug32(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1759 static bool trap_debug32(struct kvm_vcpu *vcpu,
1760 struct sys_reg_params *p,
1761 const struct sys_reg_desc *r)
1762 {
1763 if (p->is_write) {
1764 vcpu_cp14(vcpu, r->reg) = p->regval;
1765 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY;
1766 } else {
1767 p->regval = vcpu_cp14(vcpu, r->reg);
1768 }
1769
1770 return true;
1771 }
1772
1773 /* AArch32 debug register mappings
1774 *
1775 * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0]
1776 * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32]
1777 *
1778 * All control registers and watchpoint value registers are mapped to
1779 * the lower 32 bits of their AArch64 equivalents. We share the trap
1780 * handlers with the above AArch64 code which checks what mode the
1781 * system is in.
1782 */
1783
trap_xvr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * rd)1784 static bool trap_xvr(struct kvm_vcpu *vcpu,
1785 struct sys_reg_params *p,
1786 const struct sys_reg_desc *rd)
1787 {
1788 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];
1789
1790 if (p->is_write) {
1791 u64 val = *dbg_reg;
1792
1793 val &= 0xffffffffUL;
1794 val |= p->regval << 32;
1795 *dbg_reg = val;
1796
1797 vcpu->arch.flags |= KVM_ARM64_DEBUG_DIRTY;
1798 } else {
1799 p->regval = *dbg_reg >> 32;
1800 }
1801
1802 trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);
1803
1804 return true;
1805 }
1806
1807 #define DBG_BCR_BVR_WCR_WVR(n) \
1808 /* DBGBVRn */ \
1809 { Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \
1810 /* DBGBCRn */ \
1811 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n }, \
1812 /* DBGWVRn */ \
1813 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n }, \
1814 /* DBGWCRn */ \
1815 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n }
1816
1817 #define DBGBXVR(n) \
1818 { Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_xvr, NULL, n }
1819
1820 /*
1821 * Trapped cp14 registers. We generally ignore most of the external
1822 * debug, on the principle that they don't really make sense to a
1823 * guest. Revisit this one day, would this principle change.
1824 */
1825 static const struct sys_reg_desc cp14_regs[] = {
1826 /* DBGIDR */
1827 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgidr },
1828 /* DBGDTRRXext */
1829 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi },
1830
1831 DBG_BCR_BVR_WCR_WVR(0),
1832 /* DBGDSCRint */
1833 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi },
1834 DBG_BCR_BVR_WCR_WVR(1),
1835 /* DBGDCCINT */
1836 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug32, NULL, cp14_DBGDCCINT },
1837 /* DBGDSCRext */
1838 { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug32, NULL, cp14_DBGDSCRext },
1839 DBG_BCR_BVR_WCR_WVR(2),
1840 /* DBGDTR[RT]Xint */
1841 { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi },
1842 /* DBGDTR[RT]Xext */
1843 { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi },
1844 DBG_BCR_BVR_WCR_WVR(3),
1845 DBG_BCR_BVR_WCR_WVR(4),
1846 DBG_BCR_BVR_WCR_WVR(5),
1847 /* DBGWFAR */
1848 { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi },
1849 /* DBGOSECCR */
1850 { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi },
1851 DBG_BCR_BVR_WCR_WVR(6),
1852 /* DBGVCR */
1853 { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug32, NULL, cp14_DBGVCR },
1854 DBG_BCR_BVR_WCR_WVR(7),
1855 DBG_BCR_BVR_WCR_WVR(8),
1856 DBG_BCR_BVR_WCR_WVR(9),
1857 DBG_BCR_BVR_WCR_WVR(10),
1858 DBG_BCR_BVR_WCR_WVR(11),
1859 DBG_BCR_BVR_WCR_WVR(12),
1860 DBG_BCR_BVR_WCR_WVR(13),
1861 DBG_BCR_BVR_WCR_WVR(14),
1862 DBG_BCR_BVR_WCR_WVR(15),
1863
1864 /* DBGDRAR (32bit) */
1865 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi },
1866
1867 DBGBXVR(0),
1868 /* DBGOSLAR */
1869 { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_raz_wi },
1870 DBGBXVR(1),
1871 /* DBGOSLSR */
1872 { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1 },
1873 DBGBXVR(2),
1874 DBGBXVR(3),
1875 /* DBGOSDLR */
1876 { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi },
1877 DBGBXVR(4),
1878 /* DBGPRCR */
1879 { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi },
1880 DBGBXVR(5),
1881 DBGBXVR(6),
1882 DBGBXVR(7),
1883 DBGBXVR(8),
1884 DBGBXVR(9),
1885 DBGBXVR(10),
1886 DBGBXVR(11),
1887 DBGBXVR(12),
1888 DBGBXVR(13),
1889 DBGBXVR(14),
1890 DBGBXVR(15),
1891
1892 /* DBGDSAR (32bit) */
1893 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi },
1894
1895 /* DBGDEVID2 */
1896 { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi },
1897 /* DBGDEVID1 */
1898 { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi },
1899 /* DBGDEVID */
1900 { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi },
1901 /* DBGCLAIMSET */
1902 { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi },
1903 /* DBGCLAIMCLR */
1904 { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi },
1905 /* DBGAUTHSTATUS */
1906 { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 },
1907 };
1908
1909 /* Trapped cp14 64bit registers */
1910 static const struct sys_reg_desc cp14_64_regs[] = {
1911 /* DBGDRAR (64bit) */
1912 { Op1( 0), CRm( 1), .access = trap_raz_wi },
1913
1914 /* DBGDSAR (64bit) */
1915 { Op1( 0), CRm( 2), .access = trap_raz_wi },
1916 };
1917
1918 /* Macro to expand the PMEVCNTRn register */
1919 #define PMU_PMEVCNTR(n) \
1920 /* PMEVCNTRn */ \
1921 { Op1(0), CRn(0b1110), \
1922 CRm((0b1000 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
1923 access_pmu_evcntr }
1924
1925 /* Macro to expand the PMEVTYPERn register */
1926 #define PMU_PMEVTYPER(n) \
1927 /* PMEVTYPERn */ \
1928 { Op1(0), CRn(0b1110), \
1929 CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
1930 access_pmu_evtyper }
1931
1932 /*
1933 * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding,
1934 * depending on the way they are accessed (as a 32bit or a 64bit
1935 * register).
1936 */
1937 static const struct sys_reg_desc cp15_regs[] = {
1938 { Op1( 0), CRn( 0), CRm( 0), Op2( 1), access_ctr },
1939 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, c1_SCTLR },
1940 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
1941 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, c2_TTBR1 },
1942 { Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, c2_TTBCR },
1943 { Op1( 0), CRn( 2), CRm( 0), Op2( 3), access_vm_reg, NULL, c2_TTBCR2 },
1944 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, c3_DACR },
1945 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, c5_DFSR },
1946 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, c5_IFSR },
1947 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, c5_ADFSR },
1948 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, c5_AIFSR },
1949 { Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, c6_DFAR },
1950 { Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, c6_IFAR },
1951
1952 /*
1953 * DC{C,I,CI}SW operations:
1954 */
1955 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw },
1956 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw },
1957 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw },
1958
1959 /* PMU */
1960 { Op1( 0), CRn( 9), CRm(12), Op2( 0), access_pmcr },
1961 { Op1( 0), CRn( 9), CRm(12), Op2( 1), access_pmcnten },
1962 { Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmcnten },
1963 { Op1( 0), CRn( 9), CRm(12), Op2( 3), access_pmovs },
1964 { Op1( 0), CRn( 9), CRm(12), Op2( 4), access_pmswinc },
1965 { Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmselr },
1966 { Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmceid },
1967 { Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmceid },
1968 { Op1( 0), CRn( 9), CRm(13), Op2( 0), access_pmu_evcntr },
1969 { Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_evtyper },
1970 { Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_evcntr },
1971 { Op1( 0), CRn( 9), CRm(14), Op2( 0), access_pmuserenr },
1972 { Op1( 0), CRn( 9), CRm(14), Op2( 1), access_pminten },
1973 { Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pminten },
1974 { Op1( 0), CRn( 9), CRm(14), Op2( 3), access_pmovs },
1975
1976 { Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, c10_PRRR },
1977 { Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, c10_NMRR },
1978 { Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, c10_AMAIR0 },
1979 { Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, c10_AMAIR1 },
1980
1981 /* ICC_SRE */
1982 { Op1( 0), CRn(12), CRm(12), Op2( 5), access_gic_sre },
1983
1984 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, c13_CID },
1985
1986 /* Arch Tmers */
1987 { SYS_DESC(SYS_AARCH32_CNTP_TVAL), access_arch_timer },
1988 { SYS_DESC(SYS_AARCH32_CNTP_CTL), access_arch_timer },
1989
1990 /* PMEVCNTRn */
1991 PMU_PMEVCNTR(0),
1992 PMU_PMEVCNTR(1),
1993 PMU_PMEVCNTR(2),
1994 PMU_PMEVCNTR(3),
1995 PMU_PMEVCNTR(4),
1996 PMU_PMEVCNTR(5),
1997 PMU_PMEVCNTR(6),
1998 PMU_PMEVCNTR(7),
1999 PMU_PMEVCNTR(8),
2000 PMU_PMEVCNTR(9),
2001 PMU_PMEVCNTR(10),
2002 PMU_PMEVCNTR(11),
2003 PMU_PMEVCNTR(12),
2004 PMU_PMEVCNTR(13),
2005 PMU_PMEVCNTR(14),
2006 PMU_PMEVCNTR(15),
2007 PMU_PMEVCNTR(16),
2008 PMU_PMEVCNTR(17),
2009 PMU_PMEVCNTR(18),
2010 PMU_PMEVCNTR(19),
2011 PMU_PMEVCNTR(20),
2012 PMU_PMEVCNTR(21),
2013 PMU_PMEVCNTR(22),
2014 PMU_PMEVCNTR(23),
2015 PMU_PMEVCNTR(24),
2016 PMU_PMEVCNTR(25),
2017 PMU_PMEVCNTR(26),
2018 PMU_PMEVCNTR(27),
2019 PMU_PMEVCNTR(28),
2020 PMU_PMEVCNTR(29),
2021 PMU_PMEVCNTR(30),
2022 /* PMEVTYPERn */
2023 PMU_PMEVTYPER(0),
2024 PMU_PMEVTYPER(1),
2025 PMU_PMEVTYPER(2),
2026 PMU_PMEVTYPER(3),
2027 PMU_PMEVTYPER(4),
2028 PMU_PMEVTYPER(5),
2029 PMU_PMEVTYPER(6),
2030 PMU_PMEVTYPER(7),
2031 PMU_PMEVTYPER(8),
2032 PMU_PMEVTYPER(9),
2033 PMU_PMEVTYPER(10),
2034 PMU_PMEVTYPER(11),
2035 PMU_PMEVTYPER(12),
2036 PMU_PMEVTYPER(13),
2037 PMU_PMEVTYPER(14),
2038 PMU_PMEVTYPER(15),
2039 PMU_PMEVTYPER(16),
2040 PMU_PMEVTYPER(17),
2041 PMU_PMEVTYPER(18),
2042 PMU_PMEVTYPER(19),
2043 PMU_PMEVTYPER(20),
2044 PMU_PMEVTYPER(21),
2045 PMU_PMEVTYPER(22),
2046 PMU_PMEVTYPER(23),
2047 PMU_PMEVTYPER(24),
2048 PMU_PMEVTYPER(25),
2049 PMU_PMEVTYPER(26),
2050 PMU_PMEVTYPER(27),
2051 PMU_PMEVTYPER(28),
2052 PMU_PMEVTYPER(29),
2053 PMU_PMEVTYPER(30),
2054 /* PMCCFILTR */
2055 { Op1(0), CRn(14), CRm(15), Op2(7), access_pmu_evtyper },
2056
2057 { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr },
2058 { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr },
2059 { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, c0_CSSELR },
2060 };
2061
2062 static const struct sys_reg_desc cp15_64_regs[] = {
2063 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
2064 { Op1( 0), CRn( 0), CRm( 9), Op2( 0), access_pmu_evcntr },
2065 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */
2066 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR1 },
2067 { Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */
2068 { Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */
2069 { SYS_DESC(SYS_AARCH32_CNTP_CVAL), access_arch_timer },
2070 };
2071
2072 /* Target specific emulation tables */
2073 static struct kvm_sys_reg_target_table *target_tables[KVM_ARM_NUM_TARGETS];
2074
kvm_register_target_sys_reg_table(unsigned int target,struct kvm_sys_reg_target_table * table)2075 void kvm_register_target_sys_reg_table(unsigned int target,
2076 struct kvm_sys_reg_target_table *table)
2077 {
2078 target_tables[target] = table;
2079 }
2080
2081 /* Get specific register table for this target. */
get_target_table(unsigned target,bool mode_is_64,size_t * num)2082 static const struct sys_reg_desc *get_target_table(unsigned target,
2083 bool mode_is_64,
2084 size_t *num)
2085 {
2086 struct kvm_sys_reg_target_table *table;
2087
2088 table = target_tables[target];
2089 if (mode_is_64) {
2090 *num = table->table64.num;
2091 return table->table64.table;
2092 } else {
2093 *num = table->table32.num;
2094 return table->table32.table;
2095 }
2096 }
2097
match_sys_reg(const void * key,const void * elt)2098 static int match_sys_reg(const void *key, const void *elt)
2099 {
2100 const unsigned long pval = (unsigned long)key;
2101 const struct sys_reg_desc *r = elt;
2102
2103 return pval - reg_to_encoding(r);
2104 }
2105
find_reg(const struct sys_reg_params * params,const struct sys_reg_desc table[],unsigned int num)2106 static const struct sys_reg_desc *find_reg(const struct sys_reg_params *params,
2107 const struct sys_reg_desc table[],
2108 unsigned int num)
2109 {
2110 unsigned long pval = reg_to_encoding(params);
2111
2112 return bsearch((void *)pval, table, num, sizeof(table[0]), match_sys_reg);
2113 }
2114
kvm_handle_cp14_load_store(struct kvm_vcpu * vcpu,struct kvm_run * run)2115 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu, struct kvm_run *run)
2116 {
2117 kvm_inject_undefined(vcpu);
2118 return 1;
2119 }
2120
perform_access(struct kvm_vcpu * vcpu,struct sys_reg_params * params,const struct sys_reg_desc * r)2121 static void perform_access(struct kvm_vcpu *vcpu,
2122 struct sys_reg_params *params,
2123 const struct sys_reg_desc *r)
2124 {
2125 trace_kvm_sys_access(*vcpu_pc(vcpu), params, r);
2126
2127 /* Check for regs disabled by runtime config */
2128 if (sysreg_hidden_from_guest(vcpu, r)) {
2129 kvm_inject_undefined(vcpu);
2130 return;
2131 }
2132
2133 /*
2134 * Not having an accessor means that we have configured a trap
2135 * that we don't know how to handle. This certainly qualifies
2136 * as a gross bug that should be fixed right away.
2137 */
2138 BUG_ON(!r->access);
2139
2140 /* Skip instruction if instructed so */
2141 if (likely(r->access(vcpu, params, r)))
2142 kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
2143 }
2144
2145 /*
2146 * emulate_cp -- tries to match a sys_reg access in a handling table, and
2147 * call the corresponding trap handler.
2148 *
2149 * @params: pointer to the descriptor of the access
2150 * @table: array of trap descriptors
2151 * @num: size of the trap descriptor array
2152 *
2153 * Return 0 if the access has been handled, and -1 if not.
2154 */
emulate_cp(struct kvm_vcpu * vcpu,struct sys_reg_params * params,const struct sys_reg_desc * table,size_t num)2155 static int emulate_cp(struct kvm_vcpu *vcpu,
2156 struct sys_reg_params *params,
2157 const struct sys_reg_desc *table,
2158 size_t num)
2159 {
2160 const struct sys_reg_desc *r;
2161
2162 if (!table)
2163 return -1; /* Not handled */
2164
2165 r = find_reg(params, table, num);
2166
2167 if (r) {
2168 perform_access(vcpu, params, r);
2169 return 0;
2170 }
2171
2172 /* Not handled */
2173 return -1;
2174 }
2175
unhandled_cp_access(struct kvm_vcpu * vcpu,struct sys_reg_params * params)2176 static void unhandled_cp_access(struct kvm_vcpu *vcpu,
2177 struct sys_reg_params *params)
2178 {
2179 u8 hsr_ec = kvm_vcpu_trap_get_class(vcpu);
2180 int cp = -1;
2181
2182 switch(hsr_ec) {
2183 case ESR_ELx_EC_CP15_32:
2184 case ESR_ELx_EC_CP15_64:
2185 cp = 15;
2186 break;
2187 case ESR_ELx_EC_CP14_MR:
2188 case ESR_ELx_EC_CP14_64:
2189 cp = 14;
2190 break;
2191 default:
2192 WARN_ON(1);
2193 }
2194
2195 kvm_err("Unsupported guest CP%d access at: %08lx [%08lx]\n",
2196 cp, *vcpu_pc(vcpu), *vcpu_cpsr(vcpu));
2197 print_sys_reg_instr(params);
2198 kvm_inject_undefined(vcpu);
2199 }
2200
2201 /**
2202 * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access
2203 * @vcpu: The VCPU pointer
2204 * @run: The kvm_run struct
2205 */
kvm_handle_cp_64(struct kvm_vcpu * vcpu,const struct sys_reg_desc * global,size_t nr_global,const struct sys_reg_desc * target_specific,size_t nr_specific)2206 static int kvm_handle_cp_64(struct kvm_vcpu *vcpu,
2207 const struct sys_reg_desc *global,
2208 size_t nr_global,
2209 const struct sys_reg_desc *target_specific,
2210 size_t nr_specific)
2211 {
2212 struct sys_reg_params params;
2213 u32 hsr = kvm_vcpu_get_hsr(vcpu);
2214 int Rt = kvm_vcpu_sys_get_rt(vcpu);
2215 int Rt2 = (hsr >> 10) & 0x1f;
2216
2217 params.is_aarch32 = true;
2218 params.is_32bit = false;
2219 params.CRm = (hsr >> 1) & 0xf;
2220 params.is_write = ((hsr & 1) == 0);
2221
2222 params.Op0 = 0;
2223 params.Op1 = (hsr >> 16) & 0xf;
2224 params.Op2 = 0;
2225 params.CRn = 0;
2226
2227 /*
2228 * Make a 64-bit value out of Rt and Rt2. As we use the same trap
2229 * backends between AArch32 and AArch64, we get away with it.
2230 */
2231 if (params.is_write) {
2232 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff;
2233 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32;
2234 }
2235
2236 /*
2237 * Try to emulate the coprocessor access using the target
2238 * specific table first, and using the global table afterwards.
2239 * If either of the tables contains a handler, handle the
2240 * potential register operation in the case of a read and return
2241 * with success.
2242 */
2243 if (!emulate_cp(vcpu, ¶ms, target_specific, nr_specific) ||
2244 !emulate_cp(vcpu, ¶ms, global, nr_global)) {
2245 /* Split up the value between registers for the read side */
2246 if (!params.is_write) {
2247 vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval));
2248 vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval));
2249 }
2250
2251 return 1;
2252 }
2253
2254 unhandled_cp_access(vcpu, ¶ms);
2255 return 1;
2256 }
2257
2258 /**
2259 * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access
2260 * @vcpu: The VCPU pointer
2261 * @run: The kvm_run struct
2262 */
kvm_handle_cp_32(struct kvm_vcpu * vcpu,const struct sys_reg_desc * global,size_t nr_global,const struct sys_reg_desc * target_specific,size_t nr_specific)2263 static int kvm_handle_cp_32(struct kvm_vcpu *vcpu,
2264 const struct sys_reg_desc *global,
2265 size_t nr_global,
2266 const struct sys_reg_desc *target_specific,
2267 size_t nr_specific)
2268 {
2269 struct sys_reg_params params;
2270 u32 hsr = kvm_vcpu_get_hsr(vcpu);
2271 int Rt = kvm_vcpu_sys_get_rt(vcpu);
2272
2273 params.is_aarch32 = true;
2274 params.is_32bit = true;
2275 params.CRm = (hsr >> 1) & 0xf;
2276 params.regval = vcpu_get_reg(vcpu, Rt);
2277 params.is_write = ((hsr & 1) == 0);
2278 params.CRn = (hsr >> 10) & 0xf;
2279 params.Op0 = 0;
2280 params.Op1 = (hsr >> 14) & 0x7;
2281 params.Op2 = (hsr >> 17) & 0x7;
2282
2283 if (!emulate_cp(vcpu, ¶ms, target_specific, nr_specific) ||
2284 !emulate_cp(vcpu, ¶ms, global, nr_global)) {
2285 if (!params.is_write)
2286 vcpu_set_reg(vcpu, Rt, params.regval);
2287 return 1;
2288 }
2289
2290 unhandled_cp_access(vcpu, ¶ms);
2291 return 1;
2292 }
2293
kvm_handle_cp15_64(struct kvm_vcpu * vcpu,struct kvm_run * run)2294 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
2295 {
2296 const struct sys_reg_desc *target_specific;
2297 size_t num;
2298
2299 target_specific = get_target_table(vcpu->arch.target, false, &num);
2300 return kvm_handle_cp_64(vcpu,
2301 cp15_64_regs, ARRAY_SIZE(cp15_64_regs),
2302 target_specific, num);
2303 }
2304
kvm_handle_cp15_32(struct kvm_vcpu * vcpu,struct kvm_run * run)2305 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
2306 {
2307 const struct sys_reg_desc *target_specific;
2308 size_t num;
2309
2310 target_specific = get_target_table(vcpu->arch.target, false, &num);
2311 return kvm_handle_cp_32(vcpu,
2312 cp15_regs, ARRAY_SIZE(cp15_regs),
2313 target_specific, num);
2314 }
2315
kvm_handle_cp14_64(struct kvm_vcpu * vcpu,struct kvm_run * run)2316 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
2317 {
2318 return kvm_handle_cp_64(vcpu,
2319 cp14_64_regs, ARRAY_SIZE(cp14_64_regs),
2320 NULL, 0);
2321 }
2322
kvm_handle_cp14_32(struct kvm_vcpu * vcpu,struct kvm_run * run)2323 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
2324 {
2325 return kvm_handle_cp_32(vcpu,
2326 cp14_regs, ARRAY_SIZE(cp14_regs),
2327 NULL, 0);
2328 }
2329
emulate_sys_reg(struct kvm_vcpu * vcpu,struct sys_reg_params * params)2330 static int emulate_sys_reg(struct kvm_vcpu *vcpu,
2331 struct sys_reg_params *params)
2332 {
2333 size_t num;
2334 const struct sys_reg_desc *table, *r;
2335
2336 table = get_target_table(vcpu->arch.target, true, &num);
2337
2338 /* Search target-specific then generic table. */
2339 r = find_reg(params, table, num);
2340 if (!r)
2341 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
2342
2343 if (likely(r)) {
2344 perform_access(vcpu, params, r);
2345 } else {
2346 kvm_err("Unsupported guest sys_reg access at: %lx [%08lx]\n",
2347 *vcpu_pc(vcpu), *vcpu_cpsr(vcpu));
2348 print_sys_reg_instr(params);
2349 kvm_inject_undefined(vcpu);
2350 }
2351 return 1;
2352 }
2353
reset_sys_reg_descs(struct kvm_vcpu * vcpu,const struct sys_reg_desc * table,size_t num,unsigned long * bmap)2354 static void reset_sys_reg_descs(struct kvm_vcpu *vcpu,
2355 const struct sys_reg_desc *table, size_t num,
2356 unsigned long *bmap)
2357 {
2358 unsigned long i;
2359
2360 for (i = 0; i < num; i++)
2361 if (table[i].reset) {
2362 int reg = table[i].reg;
2363
2364 table[i].reset(vcpu, &table[i]);
2365 if (reg > 0 && reg < NR_SYS_REGS)
2366 set_bit(reg, bmap);
2367 }
2368 }
2369
2370 /**
2371 * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access
2372 * @vcpu: The VCPU pointer
2373 * @run: The kvm_run struct
2374 */
kvm_handle_sys_reg(struct kvm_vcpu * vcpu,struct kvm_run * run)2375 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu, struct kvm_run *run)
2376 {
2377 struct sys_reg_params params;
2378 unsigned long esr = kvm_vcpu_get_hsr(vcpu);
2379 int Rt = kvm_vcpu_sys_get_rt(vcpu);
2380 int ret;
2381
2382 trace_kvm_handle_sys_reg(esr);
2383
2384 params.is_aarch32 = false;
2385 params.is_32bit = false;
2386 params.Op0 = (esr >> 20) & 3;
2387 params.Op1 = (esr >> 14) & 0x7;
2388 params.CRn = (esr >> 10) & 0xf;
2389 params.CRm = (esr >> 1) & 0xf;
2390 params.Op2 = (esr >> 17) & 0x7;
2391 params.regval = vcpu_get_reg(vcpu, Rt);
2392 params.is_write = !(esr & 1);
2393
2394 ret = emulate_sys_reg(vcpu, ¶ms);
2395
2396 if (!params.is_write)
2397 vcpu_set_reg(vcpu, Rt, params.regval);
2398 return ret;
2399 }
2400
2401 /******************************************************************************
2402 * Userspace API
2403 *****************************************************************************/
2404
index_to_params(u64 id,struct sys_reg_params * params)2405 static bool index_to_params(u64 id, struct sys_reg_params *params)
2406 {
2407 switch (id & KVM_REG_SIZE_MASK) {
2408 case KVM_REG_SIZE_U64:
2409 /* Any unused index bits means it's not valid. */
2410 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
2411 | KVM_REG_ARM_COPROC_MASK
2412 | KVM_REG_ARM64_SYSREG_OP0_MASK
2413 | KVM_REG_ARM64_SYSREG_OP1_MASK
2414 | KVM_REG_ARM64_SYSREG_CRN_MASK
2415 | KVM_REG_ARM64_SYSREG_CRM_MASK
2416 | KVM_REG_ARM64_SYSREG_OP2_MASK))
2417 return false;
2418 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK)
2419 >> KVM_REG_ARM64_SYSREG_OP0_SHIFT);
2420 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK)
2421 >> KVM_REG_ARM64_SYSREG_OP1_SHIFT);
2422 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK)
2423 >> KVM_REG_ARM64_SYSREG_CRN_SHIFT);
2424 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK)
2425 >> KVM_REG_ARM64_SYSREG_CRM_SHIFT);
2426 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK)
2427 >> KVM_REG_ARM64_SYSREG_OP2_SHIFT);
2428 return true;
2429 default:
2430 return false;
2431 }
2432 }
2433
find_reg_by_id(u64 id,struct sys_reg_params * params,const struct sys_reg_desc table[],unsigned int num)2434 const struct sys_reg_desc *find_reg_by_id(u64 id,
2435 struct sys_reg_params *params,
2436 const struct sys_reg_desc table[],
2437 unsigned int num)
2438 {
2439 if (!index_to_params(id, params))
2440 return NULL;
2441
2442 return find_reg(params, table, num);
2443 }
2444
2445 /* Decode an index value, and find the sys_reg_desc entry. */
index_to_sys_reg_desc(struct kvm_vcpu * vcpu,u64 id)2446 static const struct sys_reg_desc *index_to_sys_reg_desc(struct kvm_vcpu *vcpu,
2447 u64 id)
2448 {
2449 size_t num;
2450 const struct sys_reg_desc *table, *r;
2451 struct sys_reg_params params;
2452
2453 /* We only do sys_reg for now. */
2454 if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG)
2455 return NULL;
2456
2457 if (!index_to_params(id, ¶ms))
2458 return NULL;
2459
2460 table = get_target_table(vcpu->arch.target, true, &num);
2461 r = find_reg(¶ms, table, num);
2462 if (!r)
2463 r = find_reg(¶ms, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
2464
2465 /* Not saved in the sys_reg array and not otherwise accessible? */
2466 if (r && !(r->reg || r->get_user))
2467 r = NULL;
2468
2469 return r;
2470 }
2471
2472 /*
2473 * These are the invariant sys_reg registers: we let the guest see the
2474 * host versions of these, so they're part of the guest state.
2475 *
2476 * A future CPU may provide a mechanism to present different values to
2477 * the guest, or a future kvm may trap them.
2478 */
2479
2480 #define FUNCTION_INVARIANT(reg) \
2481 static void get_##reg(struct kvm_vcpu *v, \
2482 const struct sys_reg_desc *r) \
2483 { \
2484 ((struct sys_reg_desc *)r)->val = read_sysreg(reg); \
2485 }
2486
2487 FUNCTION_INVARIANT(midr_el1)
FUNCTION_INVARIANT(revidr_el1)2488 FUNCTION_INVARIANT(revidr_el1)
2489 FUNCTION_INVARIANT(clidr_el1)
2490 FUNCTION_INVARIANT(aidr_el1)
2491
2492 static void get_ctr_el0(struct kvm_vcpu *v, const struct sys_reg_desc *r)
2493 {
2494 ((struct sys_reg_desc *)r)->val = read_sanitised_ftr_reg(SYS_CTR_EL0);
2495 }
2496
2497 /* ->val is filled in by kvm_sys_reg_table_init() */
2498 static struct sys_reg_desc invariant_sys_regs[] = {
2499 { SYS_DESC(SYS_MIDR_EL1), NULL, get_midr_el1 },
2500 { SYS_DESC(SYS_REVIDR_EL1), NULL, get_revidr_el1 },
2501 { SYS_DESC(SYS_CLIDR_EL1), NULL, get_clidr_el1 },
2502 { SYS_DESC(SYS_AIDR_EL1), NULL, get_aidr_el1 },
2503 { SYS_DESC(SYS_CTR_EL0), NULL, get_ctr_el0 },
2504 };
2505
reg_from_user(u64 * val,const void __user * uaddr,u64 id)2506 static int reg_from_user(u64 *val, const void __user *uaddr, u64 id)
2507 {
2508 if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0)
2509 return -EFAULT;
2510 return 0;
2511 }
2512
reg_to_user(void __user * uaddr,const u64 * val,u64 id)2513 static int reg_to_user(void __user *uaddr, const u64 *val, u64 id)
2514 {
2515 if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0)
2516 return -EFAULT;
2517 return 0;
2518 }
2519
get_invariant_sys_reg(u64 id,void __user * uaddr)2520 static int get_invariant_sys_reg(u64 id, void __user *uaddr)
2521 {
2522 struct sys_reg_params params;
2523 const struct sys_reg_desc *r;
2524
2525 r = find_reg_by_id(id, ¶ms, invariant_sys_regs,
2526 ARRAY_SIZE(invariant_sys_regs));
2527 if (!r)
2528 return -ENOENT;
2529
2530 return reg_to_user(uaddr, &r->val, id);
2531 }
2532
set_invariant_sys_reg(u64 id,void __user * uaddr)2533 static int set_invariant_sys_reg(u64 id, void __user *uaddr)
2534 {
2535 struct sys_reg_params params;
2536 const struct sys_reg_desc *r;
2537 int err;
2538 u64 val = 0; /* Make sure high bits are 0 for 32-bit regs */
2539
2540 r = find_reg_by_id(id, ¶ms, invariant_sys_regs,
2541 ARRAY_SIZE(invariant_sys_regs));
2542 if (!r)
2543 return -ENOENT;
2544
2545 err = reg_from_user(&val, uaddr, id);
2546 if (err)
2547 return err;
2548
2549 /* This is what we mean by invariant: you can't change it. */
2550 if (r->val != val)
2551 return -EINVAL;
2552
2553 return 0;
2554 }
2555
is_valid_cache(u32 val)2556 static bool is_valid_cache(u32 val)
2557 {
2558 u32 level, ctype;
2559
2560 if (val >= CSSELR_MAX)
2561 return false;
2562
2563 /* Bottom bit is Instruction or Data bit. Next 3 bits are level. */
2564 level = (val >> 1);
2565 ctype = (cache_levels >> (level * 3)) & 7;
2566
2567 switch (ctype) {
2568 case 0: /* No cache */
2569 return false;
2570 case 1: /* Instruction cache only */
2571 return (val & 1);
2572 case 2: /* Data cache only */
2573 case 4: /* Unified cache */
2574 return !(val & 1);
2575 case 3: /* Separate instruction and data caches */
2576 return true;
2577 default: /* Reserved: we can't know instruction or data. */
2578 return false;
2579 }
2580 }
2581
demux_c15_get(u64 id,void __user * uaddr)2582 static int demux_c15_get(u64 id, void __user *uaddr)
2583 {
2584 u32 val;
2585 u32 __user *uval = uaddr;
2586
2587 /* Fail if we have unknown bits set. */
2588 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
2589 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
2590 return -ENOENT;
2591
2592 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
2593 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
2594 if (KVM_REG_SIZE(id) != 4)
2595 return -ENOENT;
2596 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
2597 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
2598 if (!is_valid_cache(val))
2599 return -ENOENT;
2600
2601 return put_user(get_ccsidr(val), uval);
2602 default:
2603 return -ENOENT;
2604 }
2605 }
2606
demux_c15_set(u64 id,void __user * uaddr)2607 static int demux_c15_set(u64 id, void __user *uaddr)
2608 {
2609 u32 val, newval;
2610 u32 __user *uval = uaddr;
2611
2612 /* Fail if we have unknown bits set. */
2613 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
2614 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
2615 return -ENOENT;
2616
2617 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
2618 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
2619 if (KVM_REG_SIZE(id) != 4)
2620 return -ENOENT;
2621 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
2622 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
2623 if (!is_valid_cache(val))
2624 return -ENOENT;
2625
2626 if (get_user(newval, uval))
2627 return -EFAULT;
2628
2629 /* This is also invariant: you can't change it. */
2630 if (newval != get_ccsidr(val))
2631 return -EINVAL;
2632 return 0;
2633 default:
2634 return -ENOENT;
2635 }
2636 }
2637
kvm_arm_sys_reg_get_reg(struct kvm_vcpu * vcpu,const struct kvm_one_reg * reg)2638 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
2639 {
2640 const struct sys_reg_desc *r;
2641 void __user *uaddr = (void __user *)(unsigned long)reg->addr;
2642
2643 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
2644 return demux_c15_get(reg->id, uaddr);
2645
2646 if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
2647 return -ENOENT;
2648
2649 r = index_to_sys_reg_desc(vcpu, reg->id);
2650 if (!r)
2651 return get_invariant_sys_reg(reg->id, uaddr);
2652
2653 /* Check for regs disabled by runtime config */
2654 if (sysreg_hidden_from_user(vcpu, r))
2655 return -ENOENT;
2656
2657 if (r->get_user)
2658 return (r->get_user)(vcpu, r, reg, uaddr);
2659
2660 return reg_to_user(uaddr, &__vcpu_sys_reg(vcpu, r->reg), reg->id);
2661 }
2662
kvm_arm_sys_reg_set_reg(struct kvm_vcpu * vcpu,const struct kvm_one_reg * reg)2663 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
2664 {
2665 const struct sys_reg_desc *r;
2666 void __user *uaddr = (void __user *)(unsigned long)reg->addr;
2667
2668 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
2669 return demux_c15_set(reg->id, uaddr);
2670
2671 if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
2672 return -ENOENT;
2673
2674 r = index_to_sys_reg_desc(vcpu, reg->id);
2675 if (!r)
2676 return set_invariant_sys_reg(reg->id, uaddr);
2677
2678 /* Check for regs disabled by runtime config */
2679 if (sysreg_hidden_from_user(vcpu, r))
2680 return -ENOENT;
2681
2682 if (r->set_user)
2683 return (r->set_user)(vcpu, r, reg, uaddr);
2684
2685 return reg_from_user(&__vcpu_sys_reg(vcpu, r->reg), uaddr, reg->id);
2686 }
2687
num_demux_regs(void)2688 static unsigned int num_demux_regs(void)
2689 {
2690 unsigned int i, count = 0;
2691
2692 for (i = 0; i < CSSELR_MAX; i++)
2693 if (is_valid_cache(i))
2694 count++;
2695
2696 return count;
2697 }
2698
write_demux_regids(u64 __user * uindices)2699 static int write_demux_regids(u64 __user *uindices)
2700 {
2701 u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX;
2702 unsigned int i;
2703
2704 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR;
2705 for (i = 0; i < CSSELR_MAX; i++) {
2706 if (!is_valid_cache(i))
2707 continue;
2708 if (put_user(val | i, uindices))
2709 return -EFAULT;
2710 uindices++;
2711 }
2712 return 0;
2713 }
2714
sys_reg_to_index(const struct sys_reg_desc * reg)2715 static u64 sys_reg_to_index(const struct sys_reg_desc *reg)
2716 {
2717 return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 |
2718 KVM_REG_ARM64_SYSREG |
2719 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) |
2720 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) |
2721 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) |
2722 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) |
2723 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT));
2724 }
2725
copy_reg_to_user(const struct sys_reg_desc * reg,u64 __user ** uind)2726 static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind)
2727 {
2728 if (!*uind)
2729 return true;
2730
2731 if (put_user(sys_reg_to_index(reg), *uind))
2732 return false;
2733
2734 (*uind)++;
2735 return true;
2736 }
2737
walk_one_sys_reg(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 __user ** uind,unsigned int * total)2738 static int walk_one_sys_reg(const struct kvm_vcpu *vcpu,
2739 const struct sys_reg_desc *rd,
2740 u64 __user **uind,
2741 unsigned int *total)
2742 {
2743 /*
2744 * Ignore registers we trap but don't save,
2745 * and for which no custom user accessor is provided.
2746 */
2747 if (!(rd->reg || rd->get_user))
2748 return 0;
2749
2750 if (sysreg_hidden_from_user(vcpu, rd))
2751 return 0;
2752
2753 if (!copy_reg_to_user(rd, uind))
2754 return -EFAULT;
2755
2756 (*total)++;
2757 return 0;
2758 }
2759
2760 /* Assumed ordered tables, see kvm_sys_reg_table_init. */
walk_sys_regs(struct kvm_vcpu * vcpu,u64 __user * uind)2761 static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind)
2762 {
2763 const struct sys_reg_desc *i1, *i2, *end1, *end2;
2764 unsigned int total = 0;
2765 size_t num;
2766 int err;
2767
2768 /* We check for duplicates here, to allow arch-specific overrides. */
2769 i1 = get_target_table(vcpu->arch.target, true, &num);
2770 end1 = i1 + num;
2771 i2 = sys_reg_descs;
2772 end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs);
2773
2774 BUG_ON(i1 == end1 || i2 == end2);
2775
2776 /* Walk carefully, as both tables may refer to the same register. */
2777 while (i1 || i2) {
2778 int cmp = cmp_sys_reg(i1, i2);
2779 /* target-specific overrides generic entry. */
2780 if (cmp <= 0)
2781 err = walk_one_sys_reg(vcpu, i1, &uind, &total);
2782 else
2783 err = walk_one_sys_reg(vcpu, i2, &uind, &total);
2784
2785 if (err)
2786 return err;
2787
2788 if (cmp <= 0 && ++i1 == end1)
2789 i1 = NULL;
2790 if (cmp >= 0 && ++i2 == end2)
2791 i2 = NULL;
2792 }
2793 return total;
2794 }
2795
kvm_arm_num_sys_reg_descs(struct kvm_vcpu * vcpu)2796 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu)
2797 {
2798 return ARRAY_SIZE(invariant_sys_regs)
2799 + num_demux_regs()
2800 + walk_sys_regs(vcpu, (u64 __user *)NULL);
2801 }
2802
kvm_arm_copy_sys_reg_indices(struct kvm_vcpu * vcpu,u64 __user * uindices)2803 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
2804 {
2805 unsigned int i;
2806 int err;
2807
2808 /* Then give them all the invariant registers' indices. */
2809 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) {
2810 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices))
2811 return -EFAULT;
2812 uindices++;
2813 }
2814
2815 err = walk_sys_regs(vcpu, uindices);
2816 if (err < 0)
2817 return err;
2818 uindices += err;
2819
2820 return write_demux_regids(uindices);
2821 }
2822
check_sysreg_table(const struct sys_reg_desc * table,unsigned int n)2823 static int check_sysreg_table(const struct sys_reg_desc *table, unsigned int n)
2824 {
2825 unsigned int i;
2826
2827 for (i = 1; i < n; i++) {
2828 if (cmp_sys_reg(&table[i-1], &table[i]) >= 0) {
2829 kvm_err("sys_reg table %p out of order (%d)\n", table, i - 1);
2830 return 1;
2831 }
2832 }
2833
2834 return 0;
2835 }
2836
kvm_sys_reg_table_init(void)2837 void kvm_sys_reg_table_init(void)
2838 {
2839 unsigned int i;
2840 struct sys_reg_desc clidr;
2841
2842 /* Make sure tables are unique and in order. */
2843 BUG_ON(check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs)));
2844 BUG_ON(check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs)));
2845 BUG_ON(check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs)));
2846 BUG_ON(check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs)));
2847 BUG_ON(check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs)));
2848 BUG_ON(check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs)));
2849
2850 /* We abuse the reset function to overwrite the table itself. */
2851 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++)
2852 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]);
2853
2854 /*
2855 * CLIDR format is awkward, so clean it up. See ARM B4.1.20:
2856 *
2857 * If software reads the Cache Type fields from Ctype1
2858 * upwards, once it has seen a value of 0b000, no caches
2859 * exist at further-out levels of the hierarchy. So, for
2860 * example, if Ctype3 is the first Cache Type field with a
2861 * value of 0b000, the values of Ctype4 to Ctype7 must be
2862 * ignored.
2863 */
2864 get_clidr_el1(NULL, &clidr); /* Ugly... */
2865 cache_levels = clidr.val;
2866 for (i = 0; i < 7; i++)
2867 if (((cache_levels >> (i*3)) & 7) == 0)
2868 break;
2869 /* Clear all higher bits. */
2870 cache_levels &= (1 << (i*3))-1;
2871 }
2872
2873 /**
2874 * kvm_reset_sys_regs - sets system registers to reset value
2875 * @vcpu: The VCPU pointer
2876 *
2877 * This function finds the right table above and sets the registers on the
2878 * virtual CPU struct to their architecturally defined reset values.
2879 */
kvm_reset_sys_regs(struct kvm_vcpu * vcpu)2880 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu)
2881 {
2882 size_t num;
2883 const struct sys_reg_desc *table;
2884 DECLARE_BITMAP(bmap, NR_SYS_REGS) = { 0, };
2885
2886 /* Generic chip reset first (so target could override). */
2887 reset_sys_reg_descs(vcpu, sys_reg_descs, ARRAY_SIZE(sys_reg_descs), bmap);
2888
2889 table = get_target_table(vcpu->arch.target, true, &num);
2890 reset_sys_reg_descs(vcpu, table, num, bmap);
2891
2892 for (num = 1; num < NR_SYS_REGS; num++) {
2893 if (WARN(!test_bit(num, bmap),
2894 "Didn't reset __vcpu_sys_reg(%zi)\n", num))
2895 break;
2896 }
2897 }
2898