| /Documentation/hwmon/ |
| D | ir35221.rst | 44 curr[2-3]_label "iout[1-2]"
45 curr[2-3]_input Measured output current
46 curr[2-3]_crit Critical maximum current
47 curr[2-3]_crit_alarm Current critical high alarm
48 curr[2-3]_highest Highest output current
49 curr[2-3]_lowest Lowest output current
50 curr[2-3]_max Maximum current
51 curr[2-3]_max_alarm Current high alarm
62 in[2-3]_label "vout[1-2]"
63 in[2-3]_input Measured output voltage
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| D | isl68137.rst | 49 curr[2-3]_label "iout[1-2]"
50 curr[2-3]_input Measured output current
51 curr[2-3]_crit Critical maximum current
52 curr[2-3]_crit_alarm Current critical high alarm
61 in[2-3]_label "vout[1-2]"
62 in[2-3]_input Measured output voltage
63 in[2-3]_lcrit Critical minimum output voltage
64 in[2-3]_lcrit_alarm Output voltage critical low alarm
65 in[2-3]_crit Critical maximum output voltage
66 in[2-3]_crit_alarm Output voltage critical high alarm
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| D | w83795.rst | 61 40 FANIN1 2Eh fan1
62 42 FANIN2 2Fh fan2
75 41 FANCTL1 10h (bank 2) pwm1
76 43 FANCTL2 11h (bank 2) pwm2
77 45 FANCTL3 12h (bank 2) pwm3
78 47 FANCTL4 13h (bank 2) pwm4
79 49 FANCTL5 14h (bank 2) pwm5
80 51 FANCTL6 15h (bank 2) pwm6
81 53 FANCTL7 16h (bank 2) pwm7
82 55 FANCTL8 17h (bank 2) pwm8
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| D | ucd9200.rst | 73 in[2-5]_label "vout[1-4]".
74 in[2-5]_input Measured voltage. From READ_VOUT register.
75 in[2-5]_min Minimum Voltage. From VOUT_UV_WARN_LIMIT register.
76 in[2-5]_max Maximum voltage. From VOUT_OV_WARN_LIMIT register.
77 in[2-5]_lcrit Critical minimum Voltage. VOUT_UV_FAULT_LIMIT register.
78 in[2-5]_crit Critical maximum voltage. From VOUT_OV_FAULT_LIMIT
80 in[2-5]_min_alarm Voltage low alarm. From VOLTAGE_UV_WARNING status.
81 in[2-5]_max_alarm Voltage high alarm. From VOLTAGE_OV_WARNING status.
82 in[2-5]_lcrit_alarm Voltage critical low alarm. From VOLTAGE_UV_FAULT
84 in[2-5]_crit_alarm Voltage critical high alarm. From VOLTAGE_OV_FAULT
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| D | pxe1610.rst | 78 curr[2-4]_label "iout[1-3]"
79 curr[2-4]_input Measured output current
80 curr[2-4]_crit Critical maximum current
81 curr[2-4]_crit_alarm Current critical high alarm
88 in[2-4]_label "vout[1-3]"
89 in[2-4]_input Measured output voltage
90 in[2-4]_lcrit Critical minimum output voltage
91 in[2-4]_lcrit_alarm Output voltage critical low alarm
92 in[2-4]_crit Critical maximum output voltage
93 in[2-4]_crit_alarm Output voltage critical high alarm
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| /Documentation/filesystems/ext4/ |
| D | blocks.rst | 8 integral power of 2. Blocks are in turn grouped into larger units called
12 pages). By default a filesystem can contain 2^32 blocks; if the '64bit'
13 feature is enabled, then a filesystem can have 2^64 blocks. The location
25 - 2KiB
29 - 2^32
30 - 2^32
31 - 2^32
32 - 2^32
34 - 2^32
35 - 2^32
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| /Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/ |
| D | pincfg.txt | 13 2 = The pin is an input
38 1 9 1 0 2 0 /* TxD6 */
39 1 a 1 0 2 0 /* TxD7 */
40 0 9 2 0 1 0 /* RxD0 */
41 0 a 2 0 1 0 /* RxD1 */
42 0 b 2 0 1 0 /* RxD2 */
43 0 c 2 0 1 0 /* RxD3 */
44 0 d 2 0 1 0 /* RxD4 */
45 1 1 2 0 2 0 /* RxD5 */
46 1 0 2 0 2 0 /* RxD6 */
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| /Documentation/gpu/ |
| D | afbc.rst | 33 * Component 2: B
44 * Component 2: B(8)
51 * Component 2: B(8)
56 * Component 1: Cb(8, 2x1 subsampled)
57 * Component 2: Cr(8, 2x1 subsampled)
67 * Component 2: B(8)
97 * Component 1: Cb(8, 2x1 subsampled)
98 * Component 2: Cr(8, 2x1 subsampled)
100 * DRM_FORMAT_NV12: nplanes = 2
108 * Component 0: Cb(8, 2x1 subsampled)
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| /Documentation/media/uapi/v4l/ |
| D | subdev-formats.rst | 22 :widths: 1 1 2
111 1 and 2.
127 green and 5-bit blue values padded on the high bit, transferred as 2
147 \setlength{\tabcolsep}{2pt}
150 :header-rows: 2
152 :widths: 36 7 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
190 - 2
219 - r\ :sub:`2`
223 - g\ :sub:`2`
227 - b\ :sub:`2`
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| D | pixfmt-rgb.rst | 28 \setlength{\tabcolsep}{2pt}
34 :header-rows: 2
41 - :cspan:`7` Byte 2
50 - 2
59 - 2
68 - 2
77 - 2
85 - r\ :sub:`2`
88 - g\ :sub:`2`
100 - g\ :sub:`2`
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| D | crop.svg | 40 …2,0 0,1 -2,0 0,1 -2,0 0,1 -2,0 0,1 -2,0 0,1 -2,0 0,1 -2,0 0,1 -2,0 0,1 -2,0 0,1 -2,0 0,1 -2,0 0,1 …
41 …2,0 0,1 -1,0 0,2 2,0 0,-1 4,0 0,-1 5,0 0,-1 4,0 0,-1 5,0 0,-1 5,0 0,-1 4,0 0,-1 3,0 0,1 -2,0 0,1 -…
47 …2,0 0,-1 -3,0 0,-1 -3,0 0,-1 -3,0 0,-1 -3,0 0,-1 -3,0 0,-1 -3,0 0,-1 -3,0 0,-1 7,0 0,1 11,0 0,1 11…
64 inkscape:pageshadow="2"
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| D | pixfmt-packed-yuv.rst | 27 \setlength{\tabcolsep}{2pt}
34 :header-rows: 2
44 - :cspan:`7` Byte 2
55 - 2
64 - 2
73 - 2
82 - 2
92 - Cb\ :sub:`2`
96 - Cr\ :sub:`2`
101 - a\ :sub:`2`
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| /Documentation/admin-guide/device-mapper/ |
| D | dm-service-time.rst | 62 2. If the paths have the same 'in-flight-size', skip the division
78 In case that 2 paths (sda and sdb) are used with repeat_count == 128
82 # echo "0 10 multipath 0 0 1 1 service-time 0 2 2 8:0 128 1 8:16 128 4" \
86 test: 0 10 multipath 0 0 1 1 service-time 0 2 2 8:0 128 1 8:16 128 4
89 test: 0 10 multipath 2 0 0 0 1 1 E 0 2 2 8:0 A 0 0 1 8:16 A 0 0 4
92 Or '2' for sda and '8' for sdb would be also true::
94 # echo "0 10 multipath 0 0 1 1 service-time 0 2 2 8:0 128 2 8:16 128 8" \
98 test: 0 10 multipath 0 0 1 1 service-time 0 2 2 8:0 128 2 8:16 128 8
101 test: 0 10 multipath 2 0 0 0 1 1 E 0 2 2 8:0 A 0 0 2 8:16 A 0 0 8
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| /Documentation/input/devices/ |
| D | elantech.rst | 9 Version 2 (EeePC) hardware support based on patches
16 2. Extra knobs
22 5. Hardware version 2
26 5.2.2 One/Three finger touch
32 6.2.2 Two finger touch
37 7.2.2 Head packet
50 hardware versions unimaginatively called version 1,version 2, version 3
52 packet. Version 2 seems to be introduced with the EeePC and uses 6 bytes
55 for 2 fingers the concatenation of two 6 bytes packets) and allows tracking
77 Hardware version 2 seems to use some of the same registers but it is not
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| D | sentelic.rst | 19 2. Set sample rate to 200;
27 Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
29 1 |Y|X|y|x|1|M|R|L| 2 |X|X|X|X|X|X|X|X| 3 |Y|Y|Y|Y|Y|Y|Y|Y| 4 | | |B|F|W|W|W|W|
40 Byte 2: X Movement(9-bit 2's complement integers)
41 Byte 3: Y Movement(9-bit 2's complement integers)
59 Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
61 1 |Y|X|y|x|1|M|R|L| 2 |X|X|X|X|X|X|X|X| 3 |Y|Y|Y|Y|Y|Y|Y|Y| 4 | | |B|F|r|l|u|d|
72 Byte 2: X Movement(9-bit 2's complement integers)
73 Byte 3: Y Movement(9-bit 2's complement integers)
85 FSP uses 2 packets (8 Bytes) to represent Absolute Position.
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| /Documentation/media/v4l-drivers/ |
| D | sh_mobile_ceu_camera.rst | 23 -2-- -\
40 -2'- -/
57 (1) to (2) - sensor cropped left or top
58 (2) to (2') - sensor cropped width or height
63 (2) to (5) - reverse sensor scale applied to CEU cropped left or top
74 scale_s = ((2') - (2)) / ((3') - (3))
76 2. Calculate "effective" input crop (sensor subwindow) - CEU crop scaled back at
89 width_s_out = ((7') - (7)) = ((2') - (2)) / scale_comb
99 scale_s_new = ((3')_new - (3)_new) / ((2') - (2))
105 left_ceu = (4)_new - (3)_new = ((5) - (2)) / scale_s_new
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| /Documentation/devicetree/bindings/media/i2c/ |
| D | st,st-mipid02.txt | 1 STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge
3 MIPID02 has two CSI-2 input ports, only one of those ports can be active at a
6 CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2 second
32 0 CSI-2 first input port
33 1 CSI-2 second input port
34 2 PARALLEL output
36 Endpoint node required property for CSI-2 connection is:
38 <1 2> or <2 1>. For Port 0 single-lane operation shall be <1> or <2>.
39 Endpoint node optional property for CSI-2 connection is:
67 data-lanes = <1 2>;
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| /Documentation/devicetree/bindings/gpio/ |
| D | gpio-mxs.txt | 20 - #interrupt-cells : Should be 2. The first cell is the GPIO number.
23 2 = high-to-low edge triggered.
48 #gpio-cells = <2>;
50 #interrupt-cells = <2>;
57 #gpio-cells = <2>;
59 #interrupt-cells = <2>;
62 gpio2: gpio@2 {
66 #gpio-cells = <2>;
68 #interrupt-cells = <2>;
75 #gpio-cells = <2>;
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| /Documentation/filesystems/ |
| D | spufs.txt | 1 SPUFS(2) Linux Programmer's Manual SPUFS(2)
16 can use spu_create(2) to establish SPU contexts in the spufs root.
34 tem calls like read(2) or write(2), but often support only a subset of
39 All files that support the read(2) operation also support readv(2) and
40 all files that support the write(2) operation also support writev(2).
41 All files support the access(2) and stat(2) family of operations, but
45 All files support the chmod(2)/fchmod(2) and chown(2)/fchown(2) opera-
58 read(2), pread(2), write(2), pwrite(2), lseek(2)
59 These operate as documented, with the exception that seek(2),
60 write(2) and pwrite(2) are not supported beyond the end of the
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| /Documentation/devicetree/bindings/input/touchscreen/ |
| D | iqs5xx.txt | 20 - touchscreen-min-x : See [2].
22 - touchscreen-min-y : See [2].
24 - touchscreen-size-x : See [2]. If this property is omitted, the
28 - touchscreen-size-y : See [2]. If this property is omitted, the
32 - touchscreen-max-pressure : See [2]. Pressure is expressed as the sum of
39 - touchscreen-fuzz-x : See [2].
41 - touchscreen-fuzz-y : See [2].
43 - touchscreen-fuzz-pressure : See [2].
45 - touchscreen-inverted-x : See [2]. Inversion is applied relative to that
49 - touchscreen-inverted-y : See [2]. Inversion is applied relative to that
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| /Documentation/scsi/ |
| D | scsi_eh.txt | 13 [1-2] How do scmd's get completed?
14 [1-2-1] Completing a scmd w/ scsi_done
15 [1-2-2] Completing a scmd w/ timeout
17 [2] How SCSI EH works
18 [2-1] EH through fine-grained callbacks
19 [2-1-1] Overview
20 [2-1-2] Flow of scmds through EH
21 [2-1-3] Flow of control
22 [2-2] EH through transportt->eh_strategy_handler()
23 [2-2-1] Pre transportt->eh_strategy_handler() SCSI midlayer conditions
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| /Documentation/devicetree/bindings/net/dsa/ |
| D | mt7530.txt | 40 2. PHY of port 0 or port 4: PHY interfaces with an external MAC like 2nd GMAC
42 Note: On a MT7621 SOC with integrated switch: 2nd GMAC can only connected to
47 1. Port 5 is disabled and isolated: An external phy can interface to the 2nd
49 In the case of a build-in MT7530 switch, port 5 shares the RGMII bus with 2nd
51 2. Port 5 is muxed to PHY of port 0/4: Port 0/4 interfaces with 2nd GMAC.
58 4. Port 5 is muxed to GMAC5 and interfaces with the 2nd GAMC as 2nd CPU port.
59 Currently a 2nd CPU port is not supported by DSA code.
62 1. normal: The PHY can only connect to 2nd GMAC but not to the switch
63 2. swapped: RGMII TX, RX are swapped; external phy interface with the switch as
64 a ethernet port. But can't interface to the 2nd GMAC.
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| /Documentation/devicetree/bindings/clock/ |
| D | brcm,iproc-clocks.txt | 109 pwm crystal (ASIU) 2 BCM_CYGNUS_ASIU_PWM_CLK
113 250mhz genpll 2 BCM_CYGNUS_GENPLL_250MHZ_CLK
121 ddr_phy lcpll0 2 BCM_CYGNUS_LCPLL0_DDR_PHY_CLK
129 ch1_lcd mipipll 2 BCM_CYGNUS_MIPIPLL_CH1_LCD
137 ch1_audio audiopll 2 BCM_CYGNUS_AUDIOPLL_CH1
140 Hurricane 2
142 PLL and leaf clock compatible strings for Hurricane 2 are:
145 The following table defines the set of PLL/clock for Hurricane 2:
173 ethernetclk genpll 2 BCM_NSP_GENPLL_ENET_SW_CLK
181 sdio lcpll0 2 BCM_NSP_LCPLL0_SDIO_CLK
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| D | ste-u300-syscon-clock.txt | 11 2 = rest/remaining clock
30 1 2 I2C bus 1 clock
34 2 3 CPU clock
35 2 4 DMA controller clock
36 2 5 External Memory Interface (EMIF) clock
37 2 6 NAND flask interface clock
38 2 8 XGAM graphics engine clock
39 2 9 Shared External Memory Interface (SEMI) clock
40 2 10 AHB Subsystem Bridge clock
41 2 12 Interrupt controller clock
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| /Documentation/devicetree/bindings/sound/ |
| D | nau8825.txt | 20 2 - 125 kOhm
26 2 - VDDA * 1.1
44 2 - VDDA * 1.1
54 2 - 2 us
58 0 - 2 us
60 2 - 8 us
66 2 - 100 ms
69 - nuvoton,jack-insert-debounce: number from 0 to 7 that sets debounce time to 2^(n+2) ms
70 - nuvoton,jack-eject-debounce: number from 0 to 7 that sets debounce time to 2^(n+2) ms
89 nuvoton,vref-impedance = <2>;
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