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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Device Tree Source for AM43xx clock data
4 *
5 * Copyright (C) 2013 Texas Instruments, Inc.
6 */
7&scm_clocks {
8	sys_clkin_ck: sys_clkin_ck@40 {
9		#clock-cells = <0>;
10		compatible = "ti,mux-clock";
11		clocks = <&sysboot_freq_sel_ck>, <&crystal_freq_sel_ck>;
12		ti,bit-shift = <31>;
13		reg = <0x0040>;
14	};
15
16	crystal_freq_sel_ck: crystal_freq_sel_ck@40 {
17		#clock-cells = <0>;
18		compatible = "ti,mux-clock";
19		clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
20		ti,bit-shift = <29>;
21		reg = <0x0040>;
22	};
23
24	sysboot_freq_sel_ck: sysboot_freq_sel_ck@44e10040 {
25		#clock-cells = <0>;
26		compatible = "ti,mux-clock";
27		clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
28		ti,bit-shift = <22>;
29		reg = <0x0040>;
30	};
31
32	adc_tsc_fck: adc_tsc_fck {
33		#clock-cells = <0>;
34		compatible = "fixed-factor-clock";
35		clocks = <&sys_clkin_ck>;
36		clock-mult = <1>;
37		clock-div = <1>;
38	};
39
40	dcan0_fck: dcan0_fck {
41		#clock-cells = <0>;
42		compatible = "fixed-factor-clock";
43		clocks = <&sys_clkin_ck>;
44		clock-mult = <1>;
45		clock-div = <1>;
46	};
47
48	dcan1_fck: dcan1_fck {
49		#clock-cells = <0>;
50		compatible = "fixed-factor-clock";
51		clocks = <&sys_clkin_ck>;
52		clock-mult = <1>;
53		clock-div = <1>;
54	};
55
56	mcasp0_fck: mcasp0_fck {
57		#clock-cells = <0>;
58		compatible = "fixed-factor-clock";
59		clocks = <&sys_clkin_ck>;
60		clock-mult = <1>;
61		clock-div = <1>;
62	};
63
64	mcasp1_fck: mcasp1_fck {
65		#clock-cells = <0>;
66		compatible = "fixed-factor-clock";
67		clocks = <&sys_clkin_ck>;
68		clock-mult = <1>;
69		clock-div = <1>;
70	};
71
72	smartreflex0_fck: smartreflex0_fck {
73		#clock-cells = <0>;
74		compatible = "fixed-factor-clock";
75		clocks = <&sys_clkin_ck>;
76		clock-mult = <1>;
77		clock-div = <1>;
78	};
79
80	smartreflex1_fck: smartreflex1_fck {
81		#clock-cells = <0>;
82		compatible = "fixed-factor-clock";
83		clocks = <&sys_clkin_ck>;
84		clock-mult = <1>;
85		clock-div = <1>;
86	};
87
88	sha0_fck: sha0_fck {
89		#clock-cells = <0>;
90		compatible = "fixed-factor-clock";
91		clocks = <&sys_clkin_ck>;
92		clock-mult = <1>;
93		clock-div = <1>;
94	};
95
96	aes0_fck: aes0_fck {
97		#clock-cells = <0>;
98		compatible = "fixed-factor-clock";
99		clocks = <&sys_clkin_ck>;
100		clock-mult = <1>;
101		clock-div = <1>;
102	};
103
104	rng_fck: rng_fck {
105		#clock-cells = <0>;
106		compatible = "fixed-factor-clock";
107		clocks = <&sys_clkin_ck>;
108		clock-mult = <1>;
109		clock-div = <1>;
110	};
111
112	ehrpwm0_tbclk: ehrpwm0_tbclk@664 {
113		#clock-cells = <0>;
114		compatible = "ti,gate-clock";
115		clocks = <&l4ls_gclk>;
116		ti,bit-shift = <0>;
117		reg = <0x0664>;
118	};
119
120	ehrpwm1_tbclk: ehrpwm1_tbclk@664 {
121		#clock-cells = <0>;
122		compatible = "ti,gate-clock";
123		clocks = <&l4ls_gclk>;
124		ti,bit-shift = <1>;
125		reg = <0x0664>;
126	};
127
128	ehrpwm2_tbclk: ehrpwm2_tbclk@664 {
129		#clock-cells = <0>;
130		compatible = "ti,gate-clock";
131		clocks = <&l4ls_gclk>;
132		ti,bit-shift = <2>;
133		reg = <0x0664>;
134	};
135
136	ehrpwm3_tbclk: ehrpwm3_tbclk@664 {
137		#clock-cells = <0>;
138		compatible = "ti,gate-clock";
139		clocks = <&l4ls_gclk>;
140		ti,bit-shift = <4>;
141		reg = <0x0664>;
142	};
143
144	ehrpwm4_tbclk: ehrpwm4_tbclk@664 {
145		#clock-cells = <0>;
146		compatible = "ti,gate-clock";
147		clocks = <&l4ls_gclk>;
148		ti,bit-shift = <5>;
149		reg = <0x0664>;
150	};
151
152	ehrpwm5_tbclk: ehrpwm5_tbclk@664 {
153		#clock-cells = <0>;
154		compatible = "ti,gate-clock";
155		clocks = <&l4ls_gclk>;
156		ti,bit-shift = <6>;
157		reg = <0x0664>;
158	};
159};
160&prcm_clocks {
161	clk_32768_ck: clk_32768_ck {
162		#clock-cells = <0>;
163		compatible = "fixed-clock";
164		clock-frequency = <32768>;
165	};
166
167	clk_rc32k_ck: clk_rc32k_ck {
168		#clock-cells = <0>;
169		compatible = "fixed-clock";
170		clock-frequency = <32768>;
171	};
172
173	virt_19200000_ck: virt_19200000_ck {
174		#clock-cells = <0>;
175		compatible = "fixed-clock";
176		clock-frequency = <19200000>;
177	};
178
179	virt_24000000_ck: virt_24000000_ck {
180		#clock-cells = <0>;
181		compatible = "fixed-clock";
182		clock-frequency = <24000000>;
183	};
184
185	virt_25000000_ck: virt_25000000_ck {
186		#clock-cells = <0>;
187		compatible = "fixed-clock";
188		clock-frequency = <25000000>;
189	};
190
191	virt_26000000_ck: virt_26000000_ck {
192		#clock-cells = <0>;
193		compatible = "fixed-clock";
194		clock-frequency = <26000000>;
195	};
196
197	tclkin_ck: tclkin_ck {
198		#clock-cells = <0>;
199		compatible = "fixed-clock";
200		clock-frequency = <26000000>;
201	};
202
203	dpll_core_ck: dpll_core_ck@2d20 {
204		#clock-cells = <0>;
205		compatible = "ti,am3-dpll-core-clock";
206		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
207		reg = <0x2d20>, <0x2d24>, <0x2d2c>;
208	};
209
210	dpll_core_x2_ck: dpll_core_x2_ck {
211		#clock-cells = <0>;
212		compatible = "ti,am3-dpll-x2-clock";
213		clocks = <&dpll_core_ck>;
214	};
215
216	dpll_core_m4_ck: dpll_core_m4_ck@2d38 {
217		#clock-cells = <0>;
218		compatible = "ti,divider-clock";
219		clocks = <&dpll_core_x2_ck>;
220		ti,max-div = <31>;
221		ti,autoidle-shift = <8>;
222		reg = <0x2d38>;
223		ti,index-starts-at-one;
224		ti,invert-autoidle-bit;
225	};
226
227	dpll_core_m5_ck: dpll_core_m5_ck@2d3c {
228		#clock-cells = <0>;
229		compatible = "ti,divider-clock";
230		clocks = <&dpll_core_x2_ck>;
231		ti,max-div = <31>;
232		ti,autoidle-shift = <8>;
233		reg = <0x2d3c>;
234		ti,index-starts-at-one;
235		ti,invert-autoidle-bit;
236	};
237
238	dpll_core_m6_ck: dpll_core_m6_ck@2d40 {
239		#clock-cells = <0>;
240		compatible = "ti,divider-clock";
241		clocks = <&dpll_core_x2_ck>;
242		ti,max-div = <31>;
243		ti,autoidle-shift = <8>;
244		reg = <0x2d40>;
245		ti,index-starts-at-one;
246		ti,invert-autoidle-bit;
247	};
248
249	dpll_mpu_ck: dpll_mpu_ck@2d60 {
250		#clock-cells = <0>;
251		compatible = "ti,am3-dpll-clock";
252		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
253		reg = <0x2d60>, <0x2d64>, <0x2d6c>;
254	};
255
256	dpll_mpu_m2_ck: dpll_mpu_m2_ck@2d70 {
257		#clock-cells = <0>;
258		compatible = "ti,divider-clock";
259		clocks = <&dpll_mpu_ck>;
260		ti,max-div = <31>;
261		ti,autoidle-shift = <8>;
262		reg = <0x2d70>;
263		ti,index-starts-at-one;
264		ti,invert-autoidle-bit;
265	};
266
267	mpu_periphclk: mpu_periphclk {
268		#clock-cells = <0>;
269		compatible = "fixed-factor-clock";
270		clocks = <&dpll_mpu_m2_ck>;
271		clock-mult = <1>;
272		clock-div = <2>;
273	};
274
275	dpll_ddr_ck: dpll_ddr_ck@2da0 {
276		#clock-cells = <0>;
277		compatible = "ti,am3-dpll-clock";
278		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
279		reg = <0x2da0>, <0x2da4>, <0x2dac>;
280	};
281
282	dpll_ddr_m2_ck: dpll_ddr_m2_ck@2db0 {
283		#clock-cells = <0>;
284		compatible = "ti,divider-clock";
285		clocks = <&dpll_ddr_ck>;
286		ti,max-div = <31>;
287		ti,autoidle-shift = <8>;
288		reg = <0x2db0>;
289		ti,index-starts-at-one;
290		ti,invert-autoidle-bit;
291	};
292
293	dpll_disp_ck: dpll_disp_ck@2e20 {
294		#clock-cells = <0>;
295		compatible = "ti,am3-dpll-clock";
296		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
297		reg = <0x2e20>, <0x2e24>, <0x2e2c>;
298	};
299
300	dpll_disp_m2_ck: dpll_disp_m2_ck@2e30 {
301		#clock-cells = <0>;
302		compatible = "ti,divider-clock";
303		clocks = <&dpll_disp_ck>;
304		ti,max-div = <31>;
305		ti,autoidle-shift = <8>;
306		reg = <0x2e30>;
307		ti,index-starts-at-one;
308		ti,invert-autoidle-bit;
309		ti,set-rate-parent;
310	};
311
312	dpll_per_ck: dpll_per_ck@2de0 {
313		#clock-cells = <0>;
314		compatible = "ti,am3-dpll-j-type-clock";
315		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
316		reg = <0x2de0>, <0x2de4>, <0x2dec>;
317	};
318
319	dpll_per_m2_ck: dpll_per_m2_ck@2df0 {
320		#clock-cells = <0>;
321		compatible = "ti,divider-clock";
322		clocks = <&dpll_per_ck>;
323		ti,max-div = <127>;
324		ti,autoidle-shift = <8>;
325		reg = <0x2df0>;
326		ti,index-starts-at-one;
327		ti,invert-autoidle-bit;
328	};
329
330	dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck {
331		#clock-cells = <0>;
332		compatible = "fixed-factor-clock";
333		clocks = <&dpll_per_m2_ck>;
334		clock-mult = <1>;
335		clock-div = <4>;
336	};
337
338	dpll_per_m2_div4_ck: dpll_per_m2_div4_ck {
339		#clock-cells = <0>;
340		compatible = "fixed-factor-clock";
341		clocks = <&dpll_per_m2_ck>;
342		clock-mult = <1>;
343		clock-div = <4>;
344	};
345
346	clk_24mhz: clk_24mhz {
347		#clock-cells = <0>;
348		compatible = "fixed-factor-clock";
349		clocks = <&dpll_per_m2_ck>;
350		clock-mult = <1>;
351		clock-div = <8>;
352	};
353
354	clkdiv32k_ck: clkdiv32k_ck {
355		#clock-cells = <0>;
356		compatible = "fixed-factor-clock";
357		clocks = <&clk_24mhz>;
358		clock-mult = <1>;
359		clock-div = <732>;
360	};
361
362	clkdiv32k_ick: clkdiv32k_ick@2a38 {
363		#clock-cells = <0>;
364		compatible = "ti,gate-clock";
365		clocks = <&clkdiv32k_ck>;
366		ti,bit-shift = <8>;
367		reg = <0x2a38>;
368	};
369
370	sysclk_div: sysclk_div {
371		#clock-cells = <0>;
372		compatible = "fixed-factor-clock";
373		clocks = <&dpll_core_m4_ck>;
374		clock-mult = <1>;
375		clock-div = <1>;
376	};
377
378	pruss_ocp_gclk: pruss_ocp_gclk@4248 {
379		#clock-cells = <0>;
380		compatible = "ti,mux-clock";
381		clocks = <&sysclk_div>, <&dpll_disp_m2_ck>;
382		reg = <0x4248>;
383	};
384
385	clk_32k_tpm_ck: clk_32k_tpm_ck {
386		#clock-cells = <0>;
387		compatible = "fixed-clock";
388		clock-frequency = <32768>;
389	};
390
391	timer1_fck: timer1_fck@4200 {
392		#clock-cells = <0>;
393		compatible = "ti,mux-clock";
394		clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_32k_tpm_ck>;
395		reg = <0x4200>;
396	};
397
398	timer2_fck: timer2_fck@4204 {
399		#clock-cells = <0>;
400		compatible = "ti,mux-clock";
401		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
402		reg = <0x4204>;
403	};
404
405	timer3_fck: timer3_fck@4208 {
406		#clock-cells = <0>;
407		compatible = "ti,mux-clock";
408		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
409		reg = <0x4208>;
410	};
411
412	timer4_fck: timer4_fck@420c {
413		#clock-cells = <0>;
414		compatible = "ti,mux-clock";
415		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
416		reg = <0x420c>;
417	};
418
419	timer5_fck: timer5_fck@4210 {
420		#clock-cells = <0>;
421		compatible = "ti,mux-clock";
422		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
423		reg = <0x4210>;
424	};
425
426	timer6_fck: timer6_fck@4214 {
427		#clock-cells = <0>;
428		compatible = "ti,mux-clock";
429		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
430		reg = <0x4214>;
431	};
432
433	timer7_fck: timer7_fck@4218 {
434		#clock-cells = <0>;
435		compatible = "ti,mux-clock";
436		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
437		reg = <0x4218>;
438	};
439
440	wdt1_fck: wdt1_fck@422c {
441		#clock-cells = <0>;
442		compatible = "ti,mux-clock";
443		clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
444		reg = <0x422c>;
445	};
446
447	l3_gclk: l3_gclk {
448		#clock-cells = <0>;
449		compatible = "fixed-factor-clock";
450		clocks = <&dpll_core_m4_ck>;
451		clock-mult = <1>;
452		clock-div = <1>;
453	};
454
455	dpll_core_m4_div2_ck: dpll_core_m4_div2_ck {
456		#clock-cells = <0>;
457		compatible = "fixed-factor-clock";
458		clocks = <&sysclk_div>;
459		clock-mult = <1>;
460		clock-div = <2>;
461	};
462
463	l4hs_gclk: l4hs_gclk {
464		#clock-cells = <0>;
465		compatible = "fixed-factor-clock";
466		clocks = <&dpll_core_m4_ck>;
467		clock-mult = <1>;
468		clock-div = <1>;
469	};
470
471	l3s_gclk: l3s_gclk {
472		#clock-cells = <0>;
473		compatible = "fixed-factor-clock";
474		clocks = <&dpll_core_m4_div2_ck>;
475		clock-mult = <1>;
476		clock-div = <1>;
477	};
478
479	l4ls_gclk: l4ls_gclk {
480		#clock-cells = <0>;
481		compatible = "fixed-factor-clock";
482		clocks = <&dpll_core_m4_div2_ck>;
483		clock-mult = <1>;
484		clock-div = <1>;
485	};
486
487	cpsw_125mhz_gclk: cpsw_125mhz_gclk {
488		#clock-cells = <0>;
489		compatible = "fixed-factor-clock";
490		clocks = <&dpll_core_m5_ck>;
491		clock-mult = <1>;
492		clock-div = <2>;
493	};
494
495	cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@4238 {
496		#clock-cells = <0>;
497		compatible = "ti,mux-clock";
498		clocks = <&sysclk_div>, <&dpll_core_m5_ck>, <&dpll_disp_m2_ck>;
499		reg = <0x4238>;
500	};
501
502	dpll_clksel_mac_clk: dpll_clksel_mac_clk@4234 {
503		#clock-cells = <0>;
504		compatible = "ti,divider-clock";
505		clocks = <&dpll_core_m5_ck>;
506		reg = <0x4234>;
507		ti,bit-shift = <2>;
508		ti,dividers = <2>, <5>;
509	};
510
511	clk_32k_mosc_ck: clk_32k_mosc_ck {
512		#clock-cells = <0>;
513		compatible = "fixed-clock";
514		clock-frequency = <32768>;
515	};
516
517	gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@4240 {
518		#clock-cells = <0>;
519		compatible = "ti,mux-clock";
520		clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>, <&clk_32k_mosc_ck>, <&clk_32k_tpm_ck>;
521		reg = <0x4240>;
522	};
523
524	mmc_clk: mmc_clk {
525		#clock-cells = <0>;
526		compatible = "fixed-factor-clock";
527		clocks = <&dpll_per_m2_ck>;
528		clock-mult = <1>;
529		clock-div = <2>;
530	};
531
532	gfx_fclk_clksel_ck: gfx_fclk_clksel_ck@423c {
533		#clock-cells = <0>;
534		compatible = "ti,mux-clock";
535		clocks = <&sysclk_div>, <&dpll_per_m2_ck>;
536		ti,bit-shift = <1>;
537		reg = <0x423c>;
538	};
539
540	gfx_fck_div_ck: gfx_fck_div_ck@423c {
541		#clock-cells = <0>;
542		compatible = "ti,divider-clock";
543		clocks = <&gfx_fclk_clksel_ck>;
544		reg = <0x423c>;
545		ti,max-div = <2>;
546	};
547
548	disp_clk: disp_clk@4244 {
549		#clock-cells = <0>;
550		compatible = "ti,mux-clock";
551		clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
552		reg = <0x4244>;
553		ti,set-rate-parent;
554	};
555
556	dpll_extdev_ck: dpll_extdev_ck@2e60 {
557		#clock-cells = <0>;
558		compatible = "ti,am3-dpll-clock";
559		clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
560		reg = <0x2e60>, <0x2e64>, <0x2e6c>;
561	};
562
563	dpll_extdev_m2_ck: dpll_extdev_m2_ck@2e70 {
564		#clock-cells = <0>;
565		compatible = "ti,divider-clock";
566		clocks = <&dpll_extdev_ck>;
567		ti,max-div = <127>;
568		ti,autoidle-shift = <8>;
569		reg = <0x2e70>;
570		ti,index-starts-at-one;
571		ti,invert-autoidle-bit;
572	};
573
574	mux_synctimer32k_ck: mux_synctimer32k_ck@4230 {
575		#clock-cells = <0>;
576		compatible = "ti,mux-clock";
577		clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>, <&clkdiv32k_ick>;
578		reg = <0x4230>;
579	};
580
581	timer8_fck: timer8_fck@421c {
582		#clock-cells = <0>;
583		compatible = "ti,mux-clock";
584		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
585		reg = <0x421c>;
586	};
587
588	timer9_fck: timer9_fck@4220 {
589		#clock-cells = <0>;
590		compatible = "ti,mux-clock";
591		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
592		reg = <0x4220>;
593	};
594
595	timer10_fck: timer10_fck@4224 {
596		#clock-cells = <0>;
597		compatible = "ti,mux-clock";
598		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
599		reg = <0x4224>;
600	};
601
602	timer11_fck: timer11_fck@4228 {
603		#clock-cells = <0>;
604		compatible = "ti,mux-clock";
605		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
606		reg = <0x4228>;
607	};
608
609	cpsw_50m_clkdiv: cpsw_50m_clkdiv {
610		#clock-cells = <0>;
611		compatible = "fixed-factor-clock";
612		clocks = <&dpll_core_m5_ck>;
613		clock-mult = <1>;
614		clock-div = <1>;
615	};
616
617	cpsw_5m_clkdiv: cpsw_5m_clkdiv {
618		#clock-cells = <0>;
619		compatible = "fixed-factor-clock";
620		clocks = <&cpsw_50m_clkdiv>;
621		clock-mult = <1>;
622		clock-div = <10>;
623	};
624
625	dpll_ddr_x2_ck: dpll_ddr_x2_ck {
626		#clock-cells = <0>;
627		compatible = "ti,am3-dpll-x2-clock";
628		clocks = <&dpll_ddr_ck>;
629	};
630
631	dpll_ddr_m4_ck: dpll_ddr_m4_ck@2db8 {
632		#clock-cells = <0>;
633		compatible = "ti,divider-clock";
634		clocks = <&dpll_ddr_x2_ck>;
635		ti,max-div = <31>;
636		ti,autoidle-shift = <8>;
637		reg = <0x2db8>;
638		ti,index-starts-at-one;
639		ti,invert-autoidle-bit;
640	};
641
642	dpll_per_clkdcoldo: dpll_per_clkdcoldo@2e14 {
643		#clock-cells = <0>;
644		compatible = "ti,fixed-factor-clock";
645		clocks = <&dpll_per_ck>;
646		ti,clock-mult = <1>;
647		ti,clock-div = <1>;
648		ti,autoidle-shift = <8>;
649		reg = <0x2e14>;
650		ti,invert-autoidle-bit;
651	};
652
653	dll_aging_clk_div: dll_aging_clk_div@4250 {
654		#clock-cells = <0>;
655		compatible = "ti,divider-clock";
656		clocks = <&sys_clkin_ck>;
657		reg = <0x4250>;
658		ti,dividers = <8>, <16>, <32>;
659	};
660
661	div_core_25m_ck: div_core_25m_ck {
662		#clock-cells = <0>;
663		compatible = "fixed-factor-clock";
664		clocks = <&sysclk_div>;
665		clock-mult = <1>;
666		clock-div = <8>;
667	};
668
669	func_12m_clk: func_12m_clk {
670		#clock-cells = <0>;
671		compatible = "fixed-factor-clock";
672		clocks = <&dpll_per_m2_ck>;
673		clock-mult = <1>;
674		clock-div = <16>;
675	};
676
677	vtp_clk_div: vtp_clk_div {
678		#clock-cells = <0>;
679		compatible = "fixed-factor-clock";
680		clocks = <&sys_clkin_ck>;
681		clock-mult = <1>;
682		clock-div = <2>;
683	};
684
685	usbphy_32khz_clkmux: usbphy_32khz_clkmux@4260 {
686		#clock-cells = <0>;
687		compatible = "ti,mux-clock";
688		clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>;
689		reg = <0x4260>;
690	};
691
692	usb_phy0_always_on_clk32k: usb_phy0_always_on_clk32k@2a40 {
693		#clock-cells = <0>;
694		compatible = "ti,gate-clock";
695		clocks = <&usbphy_32khz_clkmux>;
696		ti,bit-shift = <8>;
697		reg = <0x2a40>;
698	};
699
700	usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@2a48 {
701		#clock-cells = <0>;
702		compatible = "ti,gate-clock";
703		clocks = <&usbphy_32khz_clkmux>;
704		ti,bit-shift = <8>;
705		reg = <0x2a48>;
706	};
707
708	clkout1_osc_div_ck: clkout1-osc-div-ck {
709		#clock-cells = <0>;
710		compatible = "ti,divider-clock";
711		clocks = <&sys_clkin_ck>;
712		ti,bit-shift = <20>;
713		ti,max-div = <4>;
714		reg = <0x4100>;
715	};
716
717	clkout1_src2_mux_ck: clkout1-src2-mux-ck {
718		#clock-cells = <0>;
719		compatible = "ti,mux-clock";
720		clocks = <&clk_rc32k_ck>, <&sysclk_div>, <&dpll_ddr_m2_ck>,
721			 <&dpll_per_m2_ck>, <&dpll_disp_m2_ck>,
722			 <&dpll_mpu_m2_ck>;
723		reg = <0x4100>;
724	};
725
726	clkout1_src2_pre_div_ck: clkout1-src2-pre-div-ck {
727		#clock-cells = <0>;
728		compatible = "ti,divider-clock";
729		clocks = <&clkout1_src2_mux_ck>;
730		ti,bit-shift = <4>;
731		ti,max-div = <8>;
732		reg = <0x4100>;
733	};
734
735	clkout1_src2_post_div_ck: clkout1-src2-post-div-ck {
736		#clock-cells = <0>;
737		compatible = "ti,divider-clock";
738		clocks = <&clkout1_src2_pre_div_ck>;
739		ti,bit-shift = <8>;
740		ti,max-div = <32>;
741		ti,index-power-of-two;
742		reg = <0x4100>;
743	};
744
745	clkout1_mux_ck: clkout1-mux-ck {
746		#clock-cells = <0>;
747		compatible = "ti,mux-clock";
748		clocks = <&clkout1_osc_div_ck>, <&clk_rc32k_ck>,
749			 <&clkout1_src2_post_div_ck>, <&dpll_extdev_m2_ck>;
750		ti,bit-shift = <16>;
751		reg = <0x4100>;
752	};
753
754	clkout1_ck: clkout1-ck {
755		#clock-cells = <0>;
756		compatible = "ti,gate-clock";
757		clocks = <&clkout1_mux_ck>;
758		ti,bit-shift = <23>;
759		reg = <0x4100>;
760	};
761};
762
763&prcm {
764	wkup_cm: wkup-cm@2800 {
765		compatible = "ti,omap4-cm";
766		reg = <0x2800 0x400>;
767		#address-cells = <1>;
768		#size-cells = <1>;
769		ranges = <0 0x2800 0x400>;
770
771		l3s_tsc_clkctrl: l3s-tsc-clkctrl@120 {
772			compatible = "ti,clkctrl";
773			reg = <0x120 0x4>;
774			#clock-cells = <2>;
775		};
776
777		l4_wkup_aon_clkctrl: l4-wkup-aon-clkctrl@228 {
778			compatible = "ti,clkctrl";
779			reg = <0x228 0xc>;
780			#clock-cells = <2>;
781		};
782
783		l4_wkup_clkctrl: l4-wkup-clkctrl@220 {
784			compatible = "ti,clkctrl";
785			reg = <0x220 0x4>, <0x328 0x44>;
786			#clock-cells = <2>;
787		};
788
789	};
790
791	mpu_cm: mpu-cm@8300 {
792		compatible = "ti,omap4-cm";
793		reg = <0x8300 0x100>;
794		#address-cells = <1>;
795		#size-cells = <1>;
796		ranges = <0 0x8300 0x100>;
797
798		mpu_clkctrl: mpu-clkctrl@20 {
799			compatible = "ti,clkctrl";
800			reg = <0x20 0x4>;
801			#clock-cells = <2>;
802		};
803	};
804
805	gfx_l3_cm: gfx-l3-cm@8400 {
806		compatible = "ti,omap4-cm";
807		reg = <0x8400 0x100>;
808		#address-cells = <1>;
809		#size-cells = <1>;
810		ranges = <0 0x8400 0x100>;
811
812		gfx_l3_clkctrl: gfx-l3-clkctrl@20 {
813			compatible = "ti,clkctrl";
814			reg = <0x20 0x4>;
815			#clock-cells = <2>;
816		};
817	};
818
819	l4_rtc_cm: l4-rtc-cm@8500 {
820		compatible = "ti,omap4-cm";
821		reg = <0x8500 0x100>;
822		#address-cells = <1>;
823		#size-cells = <1>;
824		ranges = <0 0x8500 0x100>;
825
826		l4_rtc_clkctrl: l4-rtc-clkctrl@20 {
827			compatible = "ti,clkctrl";
828			reg = <0x20 0x4>;
829			#clock-cells = <2>;
830		};
831	};
832
833	per_cm: per-cm@8800 {
834		compatible = "ti,omap4-cm";
835		reg = <0x8800 0xc00>;
836		#address-cells = <1>;
837		#size-cells = <1>;
838		ranges = <0 0x8800 0xc00>;
839
840		l3_clkctrl: l3-clkctrl@20 {
841			compatible = "ti,clkctrl";
842			reg = <0x20 0x3c>, <0x78 0x2c>;
843			#clock-cells = <2>;
844		};
845
846		l3s_clkctrl: l3s-clkctrl@68 {
847			compatible = "ti,clkctrl";
848			reg = <0x68 0xc>, <0x220 0x4c>;
849			#clock-cells = <2>;
850		};
851
852		pruss_ocp_clkctrl: pruss-ocp-clkctrl@320 {
853			compatible = "ti,clkctrl";
854			reg = <0x320 0x4>;
855			#clock-cells = <2>;
856		};
857
858		l4ls_clkctrl: l4ls-clkctrl@420 {
859			compatible = "ti,clkctrl";
860			reg = <0x420 0x1a4>;
861			#clock-cells = <2>;
862		};
863
864		emif_clkctrl: emif-clkctrl@720 {
865			compatible = "ti,clkctrl";
866			reg = <0x720 0x4>;
867			#clock-cells = <2>;
868		};
869
870		dss_clkctrl: dss-clkctrl@a20 {
871			compatible = "ti,clkctrl";
872			reg = <0xa20 0x4>;
873			#clock-cells = <2>;
874		};
875
876		cpsw_125mhz_clkctrl: cpsw-125mhz-clkctrl@b20 {
877			compatible = "ti,clkctrl";
878			reg = <0xb20 0x4>;
879			#clock-cells = <2>;
880		};
881
882	};
883};
884