1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * linux/arch/arm/kernel/head.S 4 * 5 * Copyright (C) 1994-2002 Russell King 6 * Copyright (c) 2003 ARM Limited 7 * All Rights Reserved 8 * 9 * Kernel startup code for all 32-bit CPUs 10 */ 11#include <linux/linkage.h> 12#include <linux/init.h> 13 14#include <asm/assembler.h> 15#include <asm/cp15.h> 16#include <asm/domain.h> 17#include <asm/ptrace.h> 18#include <asm/asm-offsets.h> 19#include <asm/memory.h> 20#include <asm/thread_info.h> 21#include <asm/pgtable.h> 22 23#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_SEMIHOSTING) 24#include CONFIG_DEBUG_LL_INCLUDE 25#endif 26 27/* 28 * swapper_pg_dir is the virtual address of the initial page table. 29 * We place the page tables 16K below KERNEL_RAM_VADDR. Therefore, we must 30 * make sure that KERNEL_RAM_VADDR is correctly set. Currently, we expect 31 * the least significant 16 bits to be 0x8000, but we could probably 32 * relax this restriction to KERNEL_RAM_VADDR >= PAGE_OFFSET + 0x4000. 33 */ 34#define KERNEL_RAM_VADDR (PAGE_OFFSET + TEXT_OFFSET) 35#if (KERNEL_RAM_VADDR & 0xffff) != 0x8000 36#error KERNEL_RAM_VADDR must start at 0xXXXX8000 37#endif 38 39#ifdef CONFIG_ARM_LPAE 40 /* LPAE requires an additional page for the PGD */ 41#define PG_DIR_SIZE 0x5000 42#define PMD_ORDER 3 43#else 44#define PG_DIR_SIZE 0x4000 45#define PMD_ORDER 2 46#endif 47 48 .globl swapper_pg_dir 49 .equ swapper_pg_dir, KERNEL_RAM_VADDR - PG_DIR_SIZE 50 51 .macro pgtbl, rd, phys 52 add \rd, \phys, #TEXT_OFFSET 53 sub \rd, \rd, #PG_DIR_SIZE 54 .endm 55 56/* 57 * Kernel startup entry point. 58 * --------------------------- 59 * 60 * This is normally called from the decompressor code. The requirements 61 * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0, 62 * r1 = machine nr, r2 = atags or dtb pointer. 63 * 64 * This code is mostly position independent, so if you link the kernel at 65 * 0xc0008000, you call this at __pa(0xc0008000). 66 * 67 * See linux/arch/arm/tools/mach-types for the complete list of machine 68 * numbers for r1. 69 * 70 * We're trying to keep crap to a minimum; DO NOT add any machine specific 71 * crap here - that's what the boot loader (or in extreme, well justified 72 * circumstances, zImage) is for. 73 */ 74 .arm 75 76 __HEAD 77ENTRY(stext) 78 ARM_BE8(setend be ) @ ensure we are in BE8 mode 79 80 THUMB( badr r9, 1f ) @ Kernel is always entered in ARM. 81 THUMB( bx r9 ) @ If this is a Thumb-2 kernel, 82 THUMB( .thumb ) @ switch to Thumb now. 83 THUMB(1: ) 84 85#ifdef CONFIG_ARM_VIRT_EXT 86 bl __hyp_stub_install 87#endif 88 @ ensure svc mode and all interrupts masked 89 safe_svcmode_maskall r9 90 91 mrc p15, 0, r9, c0, c0 @ get processor id 92 bl __lookup_processor_type @ r5=procinfo r9=cpuid 93 movs r10, r5 @ invalid processor (r5=0)? 94 THUMB( it eq ) @ force fixup-able long branch encoding 95 beq __error_p @ yes, error 'p' 96 97#ifdef CONFIG_ARM_LPAE 98 mrc p15, 0, r3, c0, c1, 4 @ read ID_MMFR0 99 and r3, r3, #0xf @ extract VMSA support 100 cmp r3, #5 @ long-descriptor translation table format? 101 THUMB( it lo ) @ force fixup-able long branch encoding 102 blo __error_lpae @ only classic page table format 103#endif 104 105#ifndef CONFIG_XIP_KERNEL 106 adr r3, 2f 107 ldmia r3, {r4, r8} 108 sub r4, r3, r4 @ (PHYS_OFFSET - PAGE_OFFSET) 109 add r8, r8, r4 @ PHYS_OFFSET 110#else 111 ldr r8, =PLAT_PHYS_OFFSET @ always constant in this case 112#endif 113 114 /* 115 * r1 = machine no, r2 = atags or dtb, 116 * r8 = phys_offset, r9 = cpuid, r10 = procinfo 117 */ 118 bl __vet_atags 119#ifdef CONFIG_SMP_ON_UP 120 bl __fixup_smp 121#endif 122#ifdef CONFIG_ARM_PATCH_PHYS_VIRT 123 bl __fixup_pv_table 124#endif 125 bl __create_page_tables 126 127 /* 128 * The following calls CPU specific code in a position independent 129 * manner. See arch/arm/mm/proc-*.S for details. r10 = base of 130 * xxx_proc_info structure selected by __lookup_processor_type 131 * above. 132 * 133 * The processor init function will be called with: 134 * r1 - machine type 135 * r2 - boot data (atags/dt) pointer 136 * r4 - translation table base (low word) 137 * r5 - translation table base (high word, if LPAE) 138 * r8 - translation table base 1 (pfn if LPAE) 139 * r9 - cpuid 140 * r13 - virtual address for __enable_mmu -> __turn_mmu_on 141 * 142 * On return, the CPU will be ready for the MMU to be turned on, 143 * r0 will hold the CPU control register value, r1, r2, r4, and 144 * r9 will be preserved. r5 will also be preserved if LPAE. 145 */ 146 ldr r13, =__mmap_switched @ address to jump to after 147 @ mmu has been enabled 148 badr lr, 1f @ return (PIC) address 149#ifdef CONFIG_ARM_LPAE 150 mov r5, #0 @ high TTBR0 151 mov r8, r4, lsr #12 @ TTBR1 is swapper_pg_dir pfn 152#else 153 mov r8, r4 @ set TTBR1 to swapper_pg_dir 154#endif 155 ldr r12, [r10, #PROCINFO_INITFUNC] 156 add r12, r12, r10 157 ret r12 1581: b __enable_mmu 159ENDPROC(stext) 160 .ltorg 161#ifndef CONFIG_XIP_KERNEL 1622: .long . 163 .long PAGE_OFFSET 164#endif 165 166/* 167 * Setup the initial page tables. We only setup the barest 168 * amount which are required to get the kernel running, which 169 * generally means mapping in the kernel code. 170 * 171 * r8 = phys_offset, r9 = cpuid, r10 = procinfo 172 * 173 * Returns: 174 * r0, r3, r5-r7 corrupted 175 * r4 = physical page table address 176 */ 177__create_page_tables: 178 pgtbl r4, r8 @ page table address 179 180 /* 181 * Clear the swapper page table 182 */ 183 mov r0, r4 184 mov r3, #0 185 add r6, r0, #PG_DIR_SIZE 1861: str r3, [r0], #4 187 str r3, [r0], #4 188 str r3, [r0], #4 189 str r3, [r0], #4 190 teq r0, r6 191 bne 1b 192 193#ifdef CONFIG_ARM_LPAE 194 /* 195 * Build the PGD table (first level) to point to the PMD table. A PGD 196 * entry is 64-bit wide. 197 */ 198 mov r0, r4 199 add r3, r4, #0x1000 @ first PMD table address 200 orr r3, r3, #3 @ PGD block type 201 mov r6, #4 @ PTRS_PER_PGD 202 mov r7, #1 << (55 - 32) @ L_PGD_SWAPPER 2031: 204#ifdef CONFIG_CPU_ENDIAN_BE8 205 str r7, [r0], #4 @ set top PGD entry bits 206 str r3, [r0], #4 @ set bottom PGD entry bits 207#else 208 str r3, [r0], #4 @ set bottom PGD entry bits 209 str r7, [r0], #4 @ set top PGD entry bits 210#endif 211 add r3, r3, #0x1000 @ next PMD table 212 subs r6, r6, #1 213 bne 1b 214 215 add r4, r4, #0x1000 @ point to the PMD tables 216#ifdef CONFIG_CPU_ENDIAN_BE8 217 add r4, r4, #4 @ we only write the bottom word 218#endif 219#endif 220 221 ldr r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags 222 223 /* 224 * Create identity mapping to cater for __enable_mmu. 225 * This identity mapping will be removed by paging_init(). 226 */ 227 adr r0, __turn_mmu_on_loc 228 ldmia r0, {r3, r5, r6} 229 sub r0, r0, r3 @ virt->phys offset 230 add r5, r5, r0 @ phys __turn_mmu_on 231 add r6, r6, r0 @ phys __turn_mmu_on_end 232 mov r5, r5, lsr #SECTION_SHIFT 233 mov r6, r6, lsr #SECTION_SHIFT 234 2351: orr r3, r7, r5, lsl #SECTION_SHIFT @ flags + kernel base 236 str r3, [r4, r5, lsl #PMD_ORDER] @ identity mapping 237 cmp r5, r6 238 addlo r5, r5, #1 @ next section 239 blo 1b 240 241 /* 242 * Map our RAM from the start to the end of the kernel .bss section. 243 */ 244 add r0, r4, #PAGE_OFFSET >> (SECTION_SHIFT - PMD_ORDER) 245 ldr r6, =(_end - 1) 246 orr r3, r8, r7 247 add r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER) 2481: str r3, [r0], #1 << PMD_ORDER 249 add r3, r3, #1 << SECTION_SHIFT 250 cmp r0, r6 251 bls 1b 252 253#ifdef CONFIG_XIP_KERNEL 254 /* 255 * Map the kernel image separately as it is not located in RAM. 256 */ 257#define XIP_START XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR) 258 mov r3, pc 259 mov r3, r3, lsr #SECTION_SHIFT 260 orr r3, r7, r3, lsl #SECTION_SHIFT 261 add r0, r4, #(XIP_START & 0xff000000) >> (SECTION_SHIFT - PMD_ORDER) 262 str r3, [r0, #((XIP_START & 0x00f00000) >> SECTION_SHIFT) << PMD_ORDER]! 263 ldr r6, =(_edata_loc - 1) 264 add r0, r0, #1 << PMD_ORDER 265 add r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER) 2661: cmp r0, r6 267 add r3, r3, #1 << SECTION_SHIFT 268 strls r3, [r0], #1 << PMD_ORDER 269 bls 1b 270#endif 271 272 /* 273 * Then map boot params address in r2 if specified. 274 * We map 2 sections in case the ATAGs/DTB crosses a section boundary. 275 */ 276 mov r0, r2, lsr #SECTION_SHIFT 277 cmp r2, #0 278 ldrne r3, =FDT_FIXED_BASE >> (SECTION_SHIFT - PMD_ORDER) 279 addne r3, r3, r4 280 orrne r6, r7, r0, lsl #SECTION_SHIFT 281 strne r6, [r3], #1 << PMD_ORDER 282 addne r6, r6, #1 << SECTION_SHIFT 283 strne r6, [r3] 284 285#if defined(CONFIG_ARM_LPAE) && defined(CONFIG_CPU_ENDIAN_BE8) 286 sub r4, r4, #4 @ Fixup page table pointer 287 @ for 64-bit descriptors 288#endif 289 290#ifdef CONFIG_DEBUG_LL 291#if !defined(CONFIG_DEBUG_ICEDCC) && !defined(CONFIG_DEBUG_SEMIHOSTING) 292 /* 293 * Map in IO space for serial debugging. 294 * This allows debug messages to be output 295 * via a serial console before paging_init. 296 */ 297 addruart r7, r3, r0 298 299 mov r3, r3, lsr #SECTION_SHIFT 300 mov r3, r3, lsl #PMD_ORDER 301 302 add r0, r4, r3 303 mov r3, r7, lsr #SECTION_SHIFT 304 ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags 305 orr r3, r7, r3, lsl #SECTION_SHIFT 306#ifdef CONFIG_ARM_LPAE 307 mov r7, #1 << (54 - 32) @ XN 308#ifdef CONFIG_CPU_ENDIAN_BE8 309 str r7, [r0], #4 310 str r3, [r0], #4 311#else 312 str r3, [r0], #4 313 str r7, [r0], #4 314#endif 315#else 316 orr r3, r3, #PMD_SECT_XN 317 str r3, [r0], #4 318#endif 319 320#else /* CONFIG_DEBUG_ICEDCC || CONFIG_DEBUG_SEMIHOSTING */ 321 /* we don't need any serial debugging mappings */ 322 ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags 323#endif 324 325#if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS) 326 /* 327 * If we're using the NetWinder or CATS, we also need to map 328 * in the 16550-type serial port for the debug messages 329 */ 330 add r0, r4, #0xff000000 >> (SECTION_SHIFT - PMD_ORDER) 331 orr r3, r7, #0x7c000000 332 str r3, [r0] 333#endif 334#ifdef CONFIG_ARCH_RPC 335 /* 336 * Map in screen at 0x02000000 & SCREEN2_BASE 337 * Similar reasons here - for debug. This is 338 * only for Acorn RiscPC architectures. 339 */ 340 add r0, r4, #0x02000000 >> (SECTION_SHIFT - PMD_ORDER) 341 orr r3, r7, #0x02000000 342 str r3, [r0] 343 add r0, r4, #0xd8000000 >> (SECTION_SHIFT - PMD_ORDER) 344 str r3, [r0] 345#endif 346#endif 347#ifdef CONFIG_ARM_LPAE 348 sub r4, r4, #0x1000 @ point to the PGD table 349#endif 350 ret lr 351ENDPROC(__create_page_tables) 352 .ltorg 353 .align 354__turn_mmu_on_loc: 355 .long . 356 .long __turn_mmu_on 357 .long __turn_mmu_on_end 358 359#if defined(CONFIG_SMP) 360 .text 361 .arm 362ENTRY(secondary_startup_arm) 363 THUMB( badr r9, 1f ) @ Kernel is entered in ARM. 364 THUMB( bx r9 ) @ If this is a Thumb-2 kernel, 365 THUMB( .thumb ) @ switch to Thumb now. 366 THUMB(1: ) 367ENTRY(secondary_startup) 368 /* 369 * Common entry point for secondary CPUs. 370 * 371 * Ensure that we're in SVC mode, and IRQs are disabled. Lookup 372 * the processor type - there is no need to check the machine type 373 * as it has already been validated by the primary processor. 374 */ 375 376 ARM_BE8(setend be) @ ensure we are in BE8 mode 377 378#ifdef CONFIG_ARM_VIRT_EXT 379 bl __hyp_stub_install_secondary 380#endif 381 safe_svcmode_maskall r9 382 383 mrc p15, 0, r9, c0, c0 @ get processor id 384 bl __lookup_processor_type 385 movs r10, r5 @ invalid processor? 386 moveq r0, #'p' @ yes, error 'p' 387 THUMB( it eq ) @ force fixup-able long branch encoding 388 beq __error_p 389 390 /* 391 * Use the page tables supplied from __cpu_up. 392 */ 393 adr r4, __secondary_data 394 ldmia r4, {r5, r7, r12} @ address to jump to after 395 sub lr, r4, r5 @ mmu has been enabled 396 add r3, r7, lr 397 ldrd r4, r5, [r3, #0] @ get secondary_data.pgdir 398ARM_BE8(eor r4, r4, r5) @ Swap r5 and r4 in BE: 399ARM_BE8(eor r5, r4, r5) @ it can be done in 3 steps 400ARM_BE8(eor r4, r4, r5) @ without using a temp reg. 401 ldr r8, [r3, #8] @ get secondary_data.swapper_pg_dir 402 badr lr, __enable_mmu @ return address 403 mov r13, r12 @ __secondary_switched address 404 ldr r12, [r10, #PROCINFO_INITFUNC] 405 add r12, r12, r10 @ initialise processor 406 @ (return control reg) 407 ret r12 408ENDPROC(secondary_startup) 409ENDPROC(secondary_startup_arm) 410 411 /* 412 * r6 = &secondary_data 413 */ 414ENTRY(__secondary_switched) 415 ldr sp, [r7, #12] @ get secondary_data.stack 416 mov fp, #0 417 b secondary_start_kernel 418ENDPROC(__secondary_switched) 419 420 .align 421 422 .type __secondary_data, %object 423__secondary_data: 424 .long . 425 .long secondary_data 426 .long __secondary_switched 427#endif /* defined(CONFIG_SMP) */ 428 429 430 431/* 432 * Setup common bits before finally enabling the MMU. Essentially 433 * this is just loading the page table pointer and domain access 434 * registers. All these registers need to be preserved by the 435 * processor setup function (or set in the case of r0) 436 * 437 * r0 = cp#15 control register 438 * r1 = machine ID 439 * r2 = atags or dtb pointer 440 * r4 = TTBR pointer (low word) 441 * r5 = TTBR pointer (high word if LPAE) 442 * r9 = processor ID 443 * r13 = *virtual* address to jump to upon completion 444 */ 445__enable_mmu: 446#if defined(CONFIG_ALIGNMENT_TRAP) && __LINUX_ARM_ARCH__ < 6 447 orr r0, r0, #CR_A 448#else 449 bic r0, r0, #CR_A 450#endif 451#ifdef CONFIG_CPU_DCACHE_DISABLE 452 bic r0, r0, #CR_C 453#endif 454#ifdef CONFIG_CPU_BPREDICT_DISABLE 455 bic r0, r0, #CR_Z 456#endif 457#ifdef CONFIG_CPU_ICACHE_DISABLE 458 bic r0, r0, #CR_I 459#endif 460#ifdef CONFIG_ARM_LPAE 461 mcrr p15, 0, r4, r5, c2 @ load TTBR0 462#else 463 mov r5, #DACR_INIT 464 mcr p15, 0, r5, c3, c0, 0 @ load domain access register 465 mcr p15, 0, r4, c2, c0, 0 @ load page table pointer 466#endif 467 b __turn_mmu_on 468ENDPROC(__enable_mmu) 469 470/* 471 * Enable the MMU. This completely changes the structure of the visible 472 * memory space. You will not be able to trace execution through this. 473 * If you have an enquiry about this, *please* check the linux-arm-kernel 474 * mailing list archives BEFORE sending another post to the list. 475 * 476 * r0 = cp#15 control register 477 * r1 = machine ID 478 * r2 = atags or dtb pointer 479 * r9 = processor ID 480 * r13 = *virtual* address to jump to upon completion 481 * 482 * other registers depend on the function called upon completion 483 */ 484 .align 5 485 .pushsection .idmap.text, "ax" 486ENTRY(__turn_mmu_on) 487 mov r0, r0 488 instr_sync 489 mcr p15, 0, r0, c1, c0, 0 @ write control reg 490 mrc p15, 0, r3, c0, c0, 0 @ read id reg 491 instr_sync 492 mov r3, r3 493 mov r3, r13 494 ret r3 495__turn_mmu_on_end: 496ENDPROC(__turn_mmu_on) 497 .popsection 498 499 500#ifdef CONFIG_SMP_ON_UP 501 __HEAD 502__fixup_smp: 503 and r3, r9, #0x000f0000 @ architecture version 504 teq r3, #0x000f0000 @ CPU ID supported? 505 bne __fixup_smp_on_up @ no, assume UP 506 507 bic r3, r9, #0x00ff0000 508 bic r3, r3, #0x0000000f @ mask 0xff00fff0 509 mov r4, #0x41000000 510 orr r4, r4, #0x0000b000 511 orr r4, r4, #0x00000020 @ val 0x4100b020 512 teq r3, r4 @ ARM 11MPCore? 513 reteq lr @ yes, assume SMP 514 515 mrc p15, 0, r0, c0, c0, 5 @ read MPIDR 516 and r0, r0, #0xc0000000 @ multiprocessing extensions and 517 teq r0, #0x80000000 @ not part of a uniprocessor system? 518 bne __fixup_smp_on_up @ no, assume UP 519 520 @ Core indicates it is SMP. Check for Aegis SOC where a single 521 @ Cortex-A9 CPU is present but SMP operations fault. 522 mov r4, #0x41000000 523 orr r4, r4, #0x0000c000 524 orr r4, r4, #0x00000090 525 teq r3, r4 @ Check for ARM Cortex-A9 526 retne lr @ Not ARM Cortex-A9, 527 528 @ If a future SoC *does* use 0x0 as the PERIPH_BASE, then the 529 @ below address check will need to be #ifdef'd or equivalent 530 @ for the Aegis platform. 531 mrc p15, 4, r0, c15, c0 @ get SCU base address 532 teq r0, #0x0 @ '0' on actual UP A9 hardware 533 beq __fixup_smp_on_up @ So its an A9 UP 534 ldr r0, [r0, #4] @ read SCU Config 535ARM_BE8(rev r0, r0) @ byteswap if big endian 536 and r0, r0, #0x3 @ number of CPUs 537 teq r0, #0x0 @ is 1? 538 retne lr 539 540__fixup_smp_on_up: 541 adr r0, 1f 542 ldmia r0, {r3 - r5} 543 sub r3, r0, r3 544 add r4, r4, r3 545 add r5, r5, r3 546 b __do_fixup_smp_on_up 547ENDPROC(__fixup_smp) 548 549 .align 5501: .word . 551 .word __smpalt_begin 552 .word __smpalt_end 553 554 .pushsection .data 555 .align 2 556 .globl smp_on_up 557smp_on_up: 558 ALT_SMP(.long 1) 559 ALT_UP(.long 0) 560 .popsection 561#endif 562 563 .text 564__do_fixup_smp_on_up: 565 cmp r4, r5 566 reths lr 567 ldmia r4!, {r0, r6} 568 ARM( str r6, [r0, r3] ) 569 THUMB( add r0, r0, r3 ) 570#ifdef __ARMEB__ 571 THUMB( mov r6, r6, ror #16 ) @ Convert word order for big-endian. 572#endif 573 THUMB( strh r6, [r0], #2 ) @ For Thumb-2, store as two halfwords 574 THUMB( mov r6, r6, lsr #16 ) @ to be robust against misaligned r3. 575 THUMB( strh r6, [r0] ) 576 b __do_fixup_smp_on_up 577ENDPROC(__do_fixup_smp_on_up) 578 579ENTRY(fixup_smp) 580 stmfd sp!, {r4 - r6, lr} 581 mov r4, r0 582 add r5, r0, r1 583 mov r3, #0 584 bl __do_fixup_smp_on_up 585 ldmfd sp!, {r4 - r6, pc} 586ENDPROC(fixup_smp) 587 588#ifdef __ARMEB__ 589#define LOW_OFFSET 0x4 590#define HIGH_OFFSET 0x0 591#else 592#define LOW_OFFSET 0x0 593#define HIGH_OFFSET 0x4 594#endif 595 596#ifdef CONFIG_ARM_PATCH_PHYS_VIRT 597 598/* __fixup_pv_table - patch the stub instructions with the delta between 599 * PHYS_OFFSET and PAGE_OFFSET, which is assumed to be 16MiB aligned and 600 * can be expressed by an immediate shifter operand. The stub instruction 601 * has a form of '(add|sub) rd, rn, #imm'. 602 */ 603 __HEAD 604__fixup_pv_table: 605 adr r0, 1f 606 ldmia r0, {r3-r7} 607 mvn ip, #0 608 subs r3, r0, r3 @ PHYS_OFFSET - PAGE_OFFSET 609 add r4, r4, r3 @ adjust table start address 610 add r5, r5, r3 @ adjust table end address 611 add r6, r6, r3 @ adjust __pv_phys_pfn_offset address 612 add r7, r7, r3 @ adjust __pv_offset address 613 mov r0, r8, lsr #PAGE_SHIFT @ convert to PFN 614 str r0, [r6] @ save computed PHYS_OFFSET to __pv_phys_pfn_offset 615 strcc ip, [r7, #HIGH_OFFSET] @ save to __pv_offset high bits 616 mov r6, r3, lsr #24 @ constant for add/sub instructions 617 teq r3, r6, lsl #24 @ must be 16MiB aligned 618THUMB( it ne @ cross section branch ) 619 bne __error 620 str r3, [r7, #LOW_OFFSET] @ save to __pv_offset low bits 621 b __fixup_a_pv_table 622ENDPROC(__fixup_pv_table) 623 624 .align 6251: .long . 626 .long __pv_table_begin 627 .long __pv_table_end 6282: .long __pv_phys_pfn_offset 629 .long __pv_offset 630 631 .text 632__fixup_a_pv_table: 633 adr r0, 3f 634 ldr r6, [r0] 635 add r6, r6, r3 636 ldr r0, [r6, #HIGH_OFFSET] @ pv_offset high word 637 ldr r6, [r6, #LOW_OFFSET] @ pv_offset low word 638 mov r6, r6, lsr #24 639 cmn r0, #1 640#ifdef CONFIG_THUMB2_KERNEL 641 moveq r0, #0x200000 @ set bit 21, mov to mvn instruction 642 lsls r6, #24 643 beq 2f 644 clz r7, r6 645 lsr r6, #24 646 lsl r6, r7 647 bic r6, #0x0080 648 lsrs r7, #1 649 orrcs r6, #0x0080 650 orr r6, r6, r7, lsl #12 651 orr r6, #0x4000 652 b 2f 6531: add r7, r3 654 ldrh ip, [r7, #2] 655ARM_BE8(rev16 ip, ip) 656 tst ip, #0x4000 657 and ip, #0x8f00 658 orrne ip, r6 @ mask in offset bits 31-24 659 orreq ip, r0 @ mask in offset bits 7-0 660ARM_BE8(rev16 ip, ip) 661 strh ip, [r7, #2] 662 bne 2f 663 ldrh ip, [r7] 664ARM_BE8(rev16 ip, ip) 665 bic ip, #0x20 666 orr ip, ip, r0, lsr #16 667ARM_BE8(rev16 ip, ip) 668 strh ip, [r7] 6692: cmp r4, r5 670 ldrcc r7, [r4], #4 @ use branch for delay slot 671 bcc 1b 672 bx lr 673#else 674 moveq r0, #0x400000 @ set bit 22, mov to mvn instruction 675 b 2f 6761: ldr ip, [r7, r3] 677#ifdef CONFIG_CPU_ENDIAN_BE8 678 @ in BE8, we load data in BE, but instructions still in LE 679 bic ip, ip, #0xff000000 680 tst ip, #0x000f0000 @ check the rotation field 681 orrne ip, ip, r6, lsl #24 @ mask in offset bits 31-24 682 biceq ip, ip, #0x00004000 @ clear bit 22 683 orreq ip, ip, r0, ror #8 @ mask in offset bits 7-0 684#else 685 bic ip, ip, #0x000000ff 686 tst ip, #0xf00 @ check the rotation field 687 orrne ip, ip, r6 @ mask in offset bits 31-24 688 biceq ip, ip, #0x400000 @ clear bit 22 689 orreq ip, ip, r0 @ mask in offset bits 7-0 690#endif 691 str ip, [r7, r3] 6922: cmp r4, r5 693 ldrcc r7, [r4], #4 @ use branch for delay slot 694 bcc 1b 695 ret lr 696#endif 697ENDPROC(__fixup_a_pv_table) 698 699 .align 7003: .long __pv_offset 701 702ENTRY(fixup_pv_table) 703 stmfd sp!, {r4 - r7, lr} 704 mov r3, #0 @ no offset 705 mov r4, r0 @ r0 = table start 706 add r5, r0, r1 @ r1 = table size 707 bl __fixup_a_pv_table 708 ldmfd sp!, {r4 - r7, pc} 709ENDPROC(fixup_pv_table) 710 711 .data 712 .align 2 713 .globl __pv_phys_pfn_offset 714 .type __pv_phys_pfn_offset, %object 715__pv_phys_pfn_offset: 716 .word 0 717 .size __pv_phys_pfn_offset, . -__pv_phys_pfn_offset 718 719 .globl __pv_offset 720 .type __pv_offset, %object 721__pv_offset: 722 .quad 0 723 .size __pv_offset, . -__pv_offset 724#endif 725 726#include "head-common.S" 727