1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_POWERPC_BOOK3S_64_MMU_H_
3 #define _ASM_POWERPC_BOOK3S_64_MMU_H_
4
5 #include <asm/page.h>
6
7 #ifndef __ASSEMBLY__
8 /*
9 * Page size definition
10 *
11 * shift : is the "PAGE_SHIFT" value for that page size
12 * sllp : is a bit mask with the value of SLB L || LP to be or'ed
13 * directly to a slbmte "vsid" value
14 * penc : is the HPTE encoding mask for the "LP" field:
15 *
16 */
17 struct mmu_psize_def {
18 unsigned int shift; /* number of bits */
19 int penc[MMU_PAGE_COUNT]; /* HPTE encoding */
20 unsigned int tlbiel; /* tlbiel supported for that page size */
21 unsigned long avpnm; /* bits to mask out in AVPN in the HPTE */
22 union {
23 unsigned long sllp; /* SLB L||LP (exact mask to use in slbmte) */
24 unsigned long ap; /* Ap encoding used by PowerISA 3.0 */
25 };
26 };
27 extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
28 #endif /* __ASSEMBLY__ */
29
30 /*
31 * If we store section details in page->flags we can't increase the MAX_PHYSMEM_BITS
32 * if we increase SECTIONS_WIDTH we will not store node details in page->flags and
33 * page_to_nid does a page->section->node lookup
34 * Hence only increase for VMEMMAP. Further depending on SPARSEMEM_EXTREME reduce
35 * memory requirements with large number of sections.
36 * 51 bits is the max physical real address on POWER9
37 */
38 #if defined(CONFIG_SPARSEMEM_VMEMMAP) && defined(CONFIG_SPARSEMEM_EXTREME) && \
39 defined(CONFIG_PPC_64K_PAGES)
40 #define MAX_PHYSMEM_BITS 51
41 #else
42 #define MAX_PHYSMEM_BITS 46
43 #endif
44
45 /* 64-bit classic hash table MMU */
46 #include <asm/book3s/64/mmu-hash.h>
47
48 #ifndef __ASSEMBLY__
49 /*
50 * ISA 3.0 partition and process table entry format
51 */
52 struct prtb_entry {
53 __be64 prtb0;
54 __be64 prtb1;
55 };
56 extern struct prtb_entry *process_tb;
57
58 struct patb_entry {
59 __be64 patb0;
60 __be64 patb1;
61 };
62 extern struct patb_entry *partition_tb;
63
64 /* Bits in patb0 field */
65 #define PATB_HR (1UL << 63)
66 #define RPDB_MASK 0x0fffffffffffff00UL
67 #define RPDB_SHIFT (1UL << 8)
68 #define RTS1_SHIFT 61 /* top 2 bits of radix tree size */
69 #define RTS1_MASK (3UL << RTS1_SHIFT)
70 #define RTS2_SHIFT 5 /* bottom 3 bits of radix tree size */
71 #define RTS2_MASK (7UL << RTS2_SHIFT)
72 #define RPDS_MASK 0x1f /* root page dir. size field */
73
74 /* Bits in patb1 field */
75 #define PATB_GR (1UL << 63) /* guest uses radix; must match HR */
76 #define PRTS_MASK 0x1f /* process table size field */
77 #define PRTB_MASK 0x0ffffffffffff000UL
78
79 /* Number of supported PID bits */
80 extern unsigned int mmu_pid_bits;
81
82 /* Base PID to allocate from */
83 extern unsigned int mmu_base_pid;
84
85 #define PRTB_SIZE_SHIFT (mmu_pid_bits + 4)
86 #define PRTB_ENTRIES (1ul << mmu_pid_bits)
87
88 /*
89 * Power9 currently only support 64K partition table size.
90 */
91 #define PATB_SIZE_SHIFT 16
92
93 typedef unsigned long mm_context_id_t;
94 struct spinlock;
95
96 /* Maximum possible number of NPUs in a system. */
97 #define NV_MAX_NPUS 8
98
99 typedef struct {
100 union {
101 /*
102 * We use id as the PIDR content for radix. On hash we can use
103 * more than one id. The extended ids are used when we start
104 * having address above 512TB. We allocate one extended id
105 * for each 512TB. The new id is then used with the 49 bit
106 * EA to build a new VA. We always use ESID_BITS_1T_MASK bits
107 * from EA and new context ids to build the new VAs.
108 */
109 mm_context_id_t id;
110 mm_context_id_t extended_id[TASK_SIZE_USER64/TASK_CONTEXT_SIZE];
111 };
112
113 /* Number of bits in the mm_cpumask */
114 atomic_t active_cpus;
115
116 /* Number of users of the external (Nest) MMU */
117 atomic_t copros;
118
119 struct hash_mm_context *hash_context;
120
121 unsigned long vdso_base;
122 /*
123 * pagetable fragment support
124 */
125 void *pte_frag;
126 void *pmd_frag;
127 #ifdef CONFIG_SPAPR_TCE_IOMMU
128 struct list_head iommu_group_mem_list;
129 #endif
130
131 #ifdef CONFIG_PPC_MEM_KEYS
132 /*
133 * Each bit represents one protection key.
134 * bit set -> key allocated
135 * bit unset -> key available for allocation
136 */
137 u32 pkey_allocation_map;
138 s16 execute_only_pkey; /* key holding execute-only protection */
139 #endif
140 } mm_context_t;
141
mm_ctx_user_psize(mm_context_t * ctx)142 static inline u16 mm_ctx_user_psize(mm_context_t *ctx)
143 {
144 return ctx->hash_context->user_psize;
145 }
146
mm_ctx_set_user_psize(mm_context_t * ctx,u16 user_psize)147 static inline void mm_ctx_set_user_psize(mm_context_t *ctx, u16 user_psize)
148 {
149 ctx->hash_context->user_psize = user_psize;
150 }
151
mm_ctx_low_slices(mm_context_t * ctx)152 static inline unsigned char *mm_ctx_low_slices(mm_context_t *ctx)
153 {
154 return ctx->hash_context->low_slices_psize;
155 }
156
mm_ctx_high_slices(mm_context_t * ctx)157 static inline unsigned char *mm_ctx_high_slices(mm_context_t *ctx)
158 {
159 return ctx->hash_context->high_slices_psize;
160 }
161
mm_ctx_slb_addr_limit(mm_context_t * ctx)162 static inline unsigned long mm_ctx_slb_addr_limit(mm_context_t *ctx)
163 {
164 return ctx->hash_context->slb_addr_limit;
165 }
166
mm_ctx_set_slb_addr_limit(mm_context_t * ctx,unsigned long limit)167 static inline void mm_ctx_set_slb_addr_limit(mm_context_t *ctx, unsigned long limit)
168 {
169 ctx->hash_context->slb_addr_limit = limit;
170 }
171
slice_mask_for_size(mm_context_t * ctx,int psize)172 static inline struct slice_mask *slice_mask_for_size(mm_context_t *ctx, int psize)
173 {
174 #ifdef CONFIG_PPC_64K_PAGES
175 if (psize == MMU_PAGE_64K)
176 return &ctx->hash_context->mask_64k;
177 #endif
178 #ifdef CONFIG_HUGETLB_PAGE
179 if (psize == MMU_PAGE_16M)
180 return &ctx->hash_context->mask_16m;
181 if (psize == MMU_PAGE_16G)
182 return &ctx->hash_context->mask_16g;
183 #endif
184 BUG_ON(psize != MMU_PAGE_4K);
185
186 return &ctx->hash_context->mask_4k;
187 }
188
189 #ifdef CONFIG_PPC_SUBPAGE_PROT
mm_ctx_subpage_prot(mm_context_t * ctx)190 static inline struct subpage_prot_table *mm_ctx_subpage_prot(mm_context_t *ctx)
191 {
192 return ctx->hash_context->spt;
193 }
194 #endif
195
196 /*
197 * The current system page and segment sizes
198 */
199 extern int mmu_linear_psize;
200 extern int mmu_virtual_psize;
201 extern int mmu_vmalloc_psize;
202 extern int mmu_vmemmap_psize;
203 extern int mmu_io_psize;
204
205 /* MMU initialization */
206 void mmu_early_init_devtree(void);
207 void hash__early_init_devtree(void);
208 void radix__early_init_devtree(void);
209 extern void hash__early_init_mmu(void);
210 extern void radix__early_init_mmu(void);
early_init_mmu(void)211 static inline void early_init_mmu(void)
212 {
213 if (radix_enabled())
214 return radix__early_init_mmu();
215 return hash__early_init_mmu();
216 }
217 extern void hash__early_init_mmu_secondary(void);
218 extern void radix__early_init_mmu_secondary(void);
early_init_mmu_secondary(void)219 static inline void early_init_mmu_secondary(void)
220 {
221 if (radix_enabled())
222 return radix__early_init_mmu_secondary();
223 return hash__early_init_mmu_secondary();
224 }
225
226 extern void hash__setup_initial_memory_limit(phys_addr_t first_memblock_base,
227 phys_addr_t first_memblock_size);
setup_initial_memory_limit(phys_addr_t first_memblock_base,phys_addr_t first_memblock_size)228 static inline void setup_initial_memory_limit(phys_addr_t first_memblock_base,
229 phys_addr_t first_memblock_size)
230 {
231 /*
232 * Hash has more strict restrictions. At this point we don't
233 * know which translations we will pick. Hence go with hash
234 * restrictions.
235 */
236 return hash__setup_initial_memory_limit(first_memblock_base,
237 first_memblock_size);
238 }
239
240 #ifdef CONFIG_PPC_PSERIES
241 extern void radix_init_pseries(void);
242 #else
radix_init_pseries(void)243 static inline void radix_init_pseries(void) { };
244 #endif
245
get_user_context(mm_context_t * ctx,unsigned long ea)246 static inline int get_user_context(mm_context_t *ctx, unsigned long ea)
247 {
248 int index = ea >> MAX_EA_BITS_PER_CONTEXT;
249
250 if (likely(index < ARRAY_SIZE(ctx->extended_id)))
251 return ctx->extended_id[index];
252
253 /* should never happen */
254 WARN_ON(1);
255 return 0;
256 }
257
get_user_vsid(mm_context_t * ctx,unsigned long ea,int ssize)258 static inline unsigned long get_user_vsid(mm_context_t *ctx,
259 unsigned long ea, int ssize)
260 {
261 unsigned long context = get_user_context(ctx, ea);
262
263 return get_vsid(context, ea, ssize);
264 }
265
266 #endif /* __ASSEMBLY__ */
267 #endif /* _ASM_POWERPC_BOOK3S_64_MMU_H_ */
268