1// SPDX-License-Identifier: GPL-2.0 2// 3// Copyright 2014 Freescale Semiconductor, Inc. 4 5#include <dt-bindings/clock/imx6sx-clock.h> 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/input/input.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include "imx6sx-pinfunc.h" 10 11/ { 12 #address-cells = <1>; 13 #size-cells = <1>; 14 /* 15 * The decompressor and also some bootloaders rely on a 16 * pre-existing /chosen node to be available to insert the 17 * command line and merge other ATAGS info. 18 */ 19 chosen {}; 20 21 aliases { 22 can0 = &flexcan1; 23 can1 = &flexcan2; 24 ethernet0 = &fec1; 25 ethernet1 = &fec2; 26 gpio0 = &gpio1; 27 gpio1 = &gpio2; 28 gpio2 = &gpio3; 29 gpio3 = &gpio4; 30 gpio4 = &gpio5; 31 gpio5 = &gpio6; 32 gpio6 = &gpio7; 33 i2c0 = &i2c1; 34 i2c1 = &i2c2; 35 i2c2 = &i2c3; 36 i2c3 = &i2c4; 37 mmc0 = &usdhc1; 38 mmc1 = &usdhc2; 39 mmc2 = &usdhc3; 40 mmc3 = &usdhc4; 41 serial0 = &uart1; 42 serial1 = &uart2; 43 serial2 = &uart3; 44 serial3 = &uart4; 45 serial4 = &uart5; 46 serial5 = &uart6; 47 spi0 = &ecspi1; 48 spi1 = &ecspi2; 49 spi2 = &ecspi3; 50 spi3 = &ecspi4; 51 spi4 = &ecspi5; 52 usb0 = &usbotg1; 53 usb1 = &usbotg2; 54 usb2 = &usbh; 55 usbphy0 = &usbphy1; 56 usbphy1 = &usbphy2; 57 }; 58 59 cpus { 60 #address-cells = <1>; 61 #size-cells = <0>; 62 63 cpu0: cpu@0 { 64 compatible = "arm,cortex-a9"; 65 device_type = "cpu"; 66 reg = <0>; 67 next-level-cache = <&L2>; 68 operating-points = < 69 /* kHz uV */ 70 996000 1250000 71 792000 1175000 72 396000 1075000 73 198000 975000 74 >; 75 fsl,soc-operating-points = < 76 /* ARM kHz SOC uV */ 77 996000 1175000 78 792000 1175000 79 396000 1175000 80 198000 1175000 81 >; 82 clock-latency = <61036>; /* two CLK32 periods */ 83 #cooling-cells = <2>; 84 clocks = <&clks IMX6SX_CLK_ARM>, 85 <&clks IMX6SX_CLK_PLL2_PFD2>, 86 <&clks IMX6SX_CLK_STEP>, 87 <&clks IMX6SX_CLK_PLL1_SW>, 88 <&clks IMX6SX_CLK_PLL1_SYS>; 89 clock-names = "arm", "pll2_pfd2_396m", "step", 90 "pll1_sw", "pll1_sys"; 91 arm-supply = <®_arm>; 92 soc-supply = <®_soc>; 93 }; 94 }; 95 96 ckil: clock-ckil { 97 compatible = "fixed-clock"; 98 #clock-cells = <0>; 99 clock-frequency = <32768>; 100 clock-output-names = "ckil"; 101 }; 102 103 osc: clock-osc { 104 compatible = "fixed-clock"; 105 #clock-cells = <0>; 106 clock-frequency = <24000000>; 107 clock-output-names = "osc"; 108 }; 109 110 ipp_di0: clock-ipp-di0 { 111 compatible = "fixed-clock"; 112 #clock-cells = <0>; 113 clock-frequency = <0>; 114 clock-output-names = "ipp_di0"; 115 }; 116 117 ipp_di1: clock-ipp-di1 { 118 compatible = "fixed-clock"; 119 #clock-cells = <0>; 120 clock-frequency = <0>; 121 clock-output-names = "ipp_di1"; 122 }; 123 124 anaclk1: clock-anaclk1 { 125 compatible = "fixed-clock"; 126 #clock-cells = <0>; 127 clock-frequency = <0>; 128 clock-output-names = "anaclk1"; 129 }; 130 131 anaclk2: clock-anaclk2 { 132 compatible = "fixed-clock"; 133 #clock-cells = <0>; 134 clock-frequency = <0>; 135 clock-output-names = "anaclk2"; 136 }; 137 138 tempmon: tempmon { 139 compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon"; 140 interrupt-parent = <&gpc>; 141 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 142 fsl,tempmon = <&anatop>; 143 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; 144 nvmem-cell-names = "calib", "temp_grade"; 145 clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>; 146 }; 147 148 pmu { 149 compatible = "arm,cortex-a9-pmu"; 150 interrupt-parent = <&gpc>; 151 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 152 }; 153 154 usbphynop1: usbphynop1 { 155 compatible = "usb-nop-xceiv"; 156 #phy-cells = <0>; 157 }; 158 159 soc { 160 #address-cells = <1>; 161 #size-cells = <1>; 162 compatible = "simple-bus"; 163 interrupt-parent = <&gpc>; 164 ranges; 165 166 ocram_s: sram@8f8000 { 167 compatible = "mmio-sram"; 168 reg = <0x008f8000 0x4000>; 169 ranges = <0 0x008f8000 0x4000>; 170 #address-cells = <1>; 171 #size-cells = <1>; 172 clocks = <&clks IMX6SX_CLK_OCRAM_S>; 173 }; 174 175 ocram: sram@900000 { 176 compatible = "mmio-sram"; 177 reg = <0x00900000 0x20000>; 178 ranges = <0 0x00900000 0x20000>; 179 #address-cells = <1>; 180 #size-cells = <1>; 181 clocks = <&clks IMX6SX_CLK_OCRAM>; 182 }; 183 184 intc: interrupt-controller@a01000 { 185 compatible = "arm,cortex-a9-gic"; 186 #interrupt-cells = <3>; 187 interrupt-controller; 188 reg = <0x00a01000 0x1000>, 189 <0x00a00100 0x100>; 190 interrupt-parent = <&intc>; 191 }; 192 193 L2: cache-controller@a02000 { 194 compatible = "arm,pl310-cache"; 195 reg = <0x00a02000 0x1000>; 196 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 197 cache-unified; 198 cache-level = <2>; 199 arm,tag-latency = <4 2 3>; 200 arm,data-latency = <4 2 3>; 201 }; 202 203 gpu: gpu@1800000 { 204 compatible = "vivante,gc"; 205 reg = <0x01800000 0x4000>; 206 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 207 clocks = <&clks IMX6SX_CLK_GPU>, 208 <&clks IMX6SX_CLK_GPU>, 209 <&clks IMX6SX_CLK_GPU>; 210 clock-names = "bus", "core", "shader"; 211 power-domains = <&pd_pu>; 212 }; 213 214 dma_apbh: dma-controller@1804000 { 215 compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh"; 216 reg = <0x01804000 0x2000>; 217 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 220 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 221 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; 222 #dma-cells = <1>; 223 dma-channels = <4>; 224 clocks = <&clks IMX6SX_CLK_APBH_DMA>; 225 }; 226 227 gpmi: gpmi-nand@1806000{ 228 compatible = "fsl,imx6sx-gpmi-nand"; 229 #address-cells = <1>; 230 #size-cells = <1>; 231 reg = <0x01806000 0x2000>, <0x01808000 0x4000>; 232 reg-names = "gpmi-nand", "bch"; 233 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 234 interrupt-names = "bch"; 235 clocks = <&clks IMX6SX_CLK_GPMI_IO>, 236 <&clks IMX6SX_CLK_GPMI_APB>, 237 <&clks IMX6SX_CLK_GPMI_BCH>, 238 <&clks IMX6SX_CLK_GPMI_BCH_APB>, 239 <&clks IMX6SX_CLK_PER1_BCH>; 240 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", 241 "gpmi_bch_apb", "per1_bch"; 242 dmas = <&dma_apbh 0>; 243 dma-names = "rx-tx"; 244 status = "disabled"; 245 }; 246 247 aips1: aips-bus@2000000 { 248 compatible = "fsl,aips-bus", "simple-bus"; 249 #address-cells = <1>; 250 #size-cells = <1>; 251 reg = <0x02000000 0x100000>; 252 ranges; 253 254 spba-bus@2000000 { 255 compatible = "fsl,spba-bus", "simple-bus"; 256 #address-cells = <1>; 257 #size-cells = <1>; 258 reg = <0x02000000 0x40000>; 259 ranges; 260 261 spdif: spdif@2004000 { 262 compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif"; 263 reg = <0x02004000 0x4000>; 264 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 265 dmas = <&sdma 14 18 0>, 266 <&sdma 15 18 0>; 267 dma-names = "rx", "tx"; 268 clocks = <&clks IMX6SX_CLK_SPDIF_GCLK>, 269 <&clks IMX6SX_CLK_OSC>, 270 <&clks IMX6SX_CLK_SPDIF>, 271 <&clks 0>, <&clks 0>, <&clks 0>, 272 <&clks IMX6SX_CLK_IPG>, 273 <&clks 0>, <&clks 0>, 274 <&clks IMX6SX_CLK_SPBA>; 275 clock-names = "core", "rxtx0", 276 "rxtx1", "rxtx2", 277 "rxtx3", "rxtx4", 278 "rxtx5", "rxtx6", 279 "rxtx7", "spba"; 280 status = "disabled"; 281 }; 282 283 ecspi1: spi@2008000 { 284 #address-cells = <1>; 285 #size-cells = <0>; 286 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; 287 reg = <0x02008000 0x4000>; 288 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 289 clocks = <&clks IMX6SX_CLK_ECSPI1>, 290 <&clks IMX6SX_CLK_ECSPI1>; 291 clock-names = "ipg", "per"; 292 status = "disabled"; 293 }; 294 295 ecspi2: spi@200c000 { 296 #address-cells = <1>; 297 #size-cells = <0>; 298 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; 299 reg = <0x0200c000 0x4000>; 300 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 301 clocks = <&clks IMX6SX_CLK_ECSPI2>, 302 <&clks IMX6SX_CLK_ECSPI2>; 303 clock-names = "ipg", "per"; 304 status = "disabled"; 305 }; 306 307 ecspi3: spi@2010000 { 308 #address-cells = <1>; 309 #size-cells = <0>; 310 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; 311 reg = <0x02010000 0x4000>; 312 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 313 clocks = <&clks IMX6SX_CLK_ECSPI3>, 314 <&clks IMX6SX_CLK_ECSPI3>; 315 clock-names = "ipg", "per"; 316 status = "disabled"; 317 }; 318 319 ecspi4: spi@2014000 { 320 #address-cells = <1>; 321 #size-cells = <0>; 322 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; 323 reg = <0x02014000 0x4000>; 324 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 325 clocks = <&clks IMX6SX_CLK_ECSPI4>, 326 <&clks IMX6SX_CLK_ECSPI4>; 327 clock-names = "ipg", "per"; 328 status = "disabled"; 329 }; 330 331 uart1: serial@2020000 { 332 compatible = "fsl,imx6sx-uart", 333 "fsl,imx6q-uart", "fsl,imx21-uart"; 334 reg = <0x02020000 0x4000>; 335 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 336 clocks = <&clks IMX6SX_CLK_UART_IPG>, 337 <&clks IMX6SX_CLK_UART_SERIAL>; 338 clock-names = "ipg", "per"; 339 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; 340 dma-names = "rx", "tx"; 341 status = "disabled"; 342 }; 343 344 esai: esai@2024000 { 345 reg = <0x02024000 0x4000>; 346 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 347 clocks = <&clks IMX6SX_CLK_ESAI_IPG>, 348 <&clks IMX6SX_CLK_ESAI_MEM>, 349 <&clks IMX6SX_CLK_ESAI_EXTAL>, 350 <&clks IMX6SX_CLK_ESAI_IPG>, 351 <&clks IMX6SX_CLK_SPBA>; 352 clock-names = "core", "mem", "extal", 353 "fsys", "spba"; 354 status = "disabled"; 355 }; 356 357 ssi1: ssi@2028000 { 358 #sound-dai-cells = <0>; 359 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; 360 reg = <0x02028000 0x4000>; 361 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 362 clocks = <&clks IMX6SX_CLK_SSI1_IPG>, 363 <&clks IMX6SX_CLK_SSI1>; 364 clock-names = "ipg", "baud"; 365 dmas = <&sdma 37 1 0>, <&sdma 38 1 0>; 366 dma-names = "rx", "tx"; 367 fsl,fifo-depth = <15>; 368 status = "disabled"; 369 }; 370 371 ssi2: ssi@202c000 { 372 #sound-dai-cells = <0>; 373 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; 374 reg = <0x0202c000 0x4000>; 375 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 376 clocks = <&clks IMX6SX_CLK_SSI2_IPG>, 377 <&clks IMX6SX_CLK_SSI2>; 378 clock-names = "ipg", "baud"; 379 dmas = <&sdma 41 1 0>, <&sdma 42 1 0>; 380 dma-names = "rx", "tx"; 381 fsl,fifo-depth = <15>; 382 status = "disabled"; 383 }; 384 385 ssi3: ssi@2030000 { 386 #sound-dai-cells = <0>; 387 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; 388 reg = <0x02030000 0x4000>; 389 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 390 clocks = <&clks IMX6SX_CLK_SSI3_IPG>, 391 <&clks IMX6SX_CLK_SSI3>; 392 clock-names = "ipg", "baud"; 393 dmas = <&sdma 45 1 0>, <&sdma 46 1 0>; 394 dma-names = "rx", "tx"; 395 fsl,fifo-depth = <15>; 396 status = "disabled"; 397 }; 398 399 asrc: asrc@2034000 { 400 reg = <0x02034000 0x4000>; 401 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 402 clocks = <&clks IMX6SX_CLK_ASRC_MEM>, 403 <&clks IMX6SX_CLK_ASRC_IPG>, 404 <&clks IMX6SX_CLK_SPDIF>, 405 <&clks IMX6SX_CLK_SPBA>; 406 clock-names = "mem", "ipg", "asrck", "spba"; 407 dmas = <&sdma 17 20 1>, <&sdma 18 20 1>, 408 <&sdma 19 20 1>, <&sdma 20 20 1>, 409 <&sdma 21 20 1>, <&sdma 22 20 1>; 410 dma-names = "rxa", "rxb", "rxc", 411 "txa", "txb", "txc"; 412 status = "okay"; 413 }; 414 }; 415 416 pwm1: pwm@2080000 { 417 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 418 reg = <0x02080000 0x4000>; 419 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 420 clocks = <&clks IMX6SX_CLK_PWM1>, 421 <&clks IMX6SX_CLK_PWM1>; 422 clock-names = "ipg", "per"; 423 #pwm-cells = <2>; 424 }; 425 426 pwm2: pwm@2084000 { 427 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 428 reg = <0x02084000 0x4000>; 429 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 430 clocks = <&clks IMX6SX_CLK_PWM2>, 431 <&clks IMX6SX_CLK_PWM2>; 432 clock-names = "ipg", "per"; 433 #pwm-cells = <2>; 434 }; 435 436 pwm3: pwm@2088000 { 437 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 438 reg = <0x02088000 0x4000>; 439 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 440 clocks = <&clks IMX6SX_CLK_PWM3>, 441 <&clks IMX6SX_CLK_PWM3>; 442 clock-names = "ipg", "per"; 443 #pwm-cells = <2>; 444 }; 445 446 pwm4: pwm@208c000 { 447 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 448 reg = <0x0208c000 0x4000>; 449 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 450 clocks = <&clks IMX6SX_CLK_PWM4>, 451 <&clks IMX6SX_CLK_PWM4>; 452 clock-names = "ipg", "per"; 453 #pwm-cells = <2>; 454 }; 455 456 flexcan1: can@2090000 { 457 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan"; 458 reg = <0x02090000 0x4000>; 459 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 460 clocks = <&clks IMX6SX_CLK_CAN1_IPG>, 461 <&clks IMX6SX_CLK_CAN1_SERIAL>; 462 clock-names = "ipg", "per"; 463 fsl,stop-mode = <&gpr 0x10 1 0x10 17>; 464 status = "disabled"; 465 }; 466 467 flexcan2: can@2094000 { 468 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan"; 469 reg = <0x02094000 0x4000>; 470 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 471 clocks = <&clks IMX6SX_CLK_CAN2_IPG>, 472 <&clks IMX6SX_CLK_CAN2_SERIAL>; 473 clock-names = "ipg", "per"; 474 fsl,stop-mode = <&gpr 0x10 2 0x10 18>; 475 status = "disabled"; 476 }; 477 478 gpt: timer@2098000 { 479 compatible = "fsl,imx6sx-gpt", "fsl,imx6dl-gpt"; 480 reg = <0x02098000 0x4000>; 481 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 482 clocks = <&clks IMX6SX_CLK_GPT_BUS>, 483 <&clks IMX6SX_CLK_GPT_3M>; 484 clock-names = "ipg", "per"; 485 }; 486 487 gpio1: gpio@209c000 { 488 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; 489 reg = <0x0209c000 0x4000>; 490 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 491 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 492 gpio-controller; 493 #gpio-cells = <2>; 494 interrupt-controller; 495 #interrupt-cells = <2>; 496 gpio-ranges = <&iomuxc 0 5 26>; 497 }; 498 499 gpio2: gpio@20a0000 { 500 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; 501 reg = <0x020a0000 0x4000>; 502 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 503 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 504 gpio-controller; 505 #gpio-cells = <2>; 506 interrupt-controller; 507 #interrupt-cells = <2>; 508 gpio-ranges = <&iomuxc 0 31 20>; 509 }; 510 511 gpio3: gpio@20a4000 { 512 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; 513 reg = <0x020a4000 0x4000>; 514 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 516 gpio-controller; 517 #gpio-cells = <2>; 518 interrupt-controller; 519 #interrupt-cells = <2>; 520 gpio-ranges = <&iomuxc 0 51 29>; 521 }; 522 523 gpio4: gpio@20a8000 { 524 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; 525 reg = <0x020a8000 0x4000>; 526 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 527 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 528 gpio-controller; 529 #gpio-cells = <2>; 530 interrupt-controller; 531 #interrupt-cells = <2>; 532 gpio-ranges = <&iomuxc 0 80 32>; 533 }; 534 535 gpio5: gpio@20ac000 { 536 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; 537 reg = <0x020ac000 0x4000>; 538 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 539 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 540 gpio-controller; 541 #gpio-cells = <2>; 542 interrupt-controller; 543 #interrupt-cells = <2>; 544 gpio-ranges = <&iomuxc 0 112 24>; 545 }; 546 547 gpio6: gpio@20b0000 { 548 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; 549 reg = <0x020b0000 0x4000>; 550 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 551 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 552 gpio-controller; 553 #gpio-cells = <2>; 554 interrupt-controller; 555 #interrupt-cells = <2>; 556 gpio-ranges = <&iomuxc 0 136 12>, <&iomuxc 12 158 11>; 557 }; 558 559 gpio7: gpio@20b4000 { 560 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio"; 561 reg = <0x020b4000 0x4000>; 562 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 563 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 564 gpio-controller; 565 #gpio-cells = <2>; 566 interrupt-controller; 567 #interrupt-cells = <2>; 568 gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>; 569 }; 570 571 kpp: kpp@20b8000 { 572 compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp"; 573 reg = <0x020b8000 0x4000>; 574 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 575 clocks = <&clks IMX6SX_CLK_IPG>; 576 status = "disabled"; 577 }; 578 579 wdog1: wdog@20bc000 { 580 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; 581 reg = <0x020bc000 0x4000>; 582 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 583 clocks = <&clks IMX6SX_CLK_IPG>; 584 }; 585 586 wdog2: wdog@20c0000 { 587 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; 588 reg = <0x020c0000 0x4000>; 589 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 590 clocks = <&clks IMX6SX_CLK_IPG>; 591 status = "disabled"; 592 }; 593 594 clks: ccm@20c4000 { 595 compatible = "fsl,imx6sx-ccm"; 596 reg = <0x020c4000 0x4000>; 597 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 599 #clock-cells = <1>; 600 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>, <&anaclk1>, <&anaclk2>; 601 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1", "anaclk1", "anaclk2"; 602 }; 603 604 anatop: anatop@20c8000 { 605 compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop", 606 "syscon", "simple-bus"; 607 reg = <0x020c8000 0x1000>; 608 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 609 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 610 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 611 612 reg_vdd1p1: regulator-1p1 { 613 compatible = "fsl,anatop-regulator"; 614 regulator-name = "vdd1p1"; 615 regulator-min-microvolt = <1000000>; 616 regulator-max-microvolt = <1200000>; 617 regulator-always-on; 618 anatop-reg-offset = <0x110>; 619 anatop-vol-bit-shift = <8>; 620 anatop-vol-bit-width = <5>; 621 anatop-min-bit-val = <4>; 622 anatop-min-voltage = <800000>; 623 anatop-max-voltage = <1375000>; 624 anatop-enable-bit = <0>; 625 }; 626 627 reg_vdd3p0: regulator-3p0 { 628 compatible = "fsl,anatop-regulator"; 629 regulator-name = "vdd3p0"; 630 regulator-min-microvolt = <2800000>; 631 regulator-max-microvolt = <3150000>; 632 regulator-always-on; 633 anatop-reg-offset = <0x120>; 634 anatop-vol-bit-shift = <8>; 635 anatop-vol-bit-width = <5>; 636 anatop-min-bit-val = <0>; 637 anatop-min-voltage = <2625000>; 638 anatop-max-voltage = <3400000>; 639 anatop-enable-bit = <0>; 640 }; 641 642 reg_vdd2p5: regulator-2p5 { 643 compatible = "fsl,anatop-regulator"; 644 regulator-name = "vdd2p5"; 645 regulator-min-microvolt = <2250000>; 646 regulator-max-microvolt = <2750000>; 647 regulator-always-on; 648 anatop-reg-offset = <0x130>; 649 anatop-vol-bit-shift = <8>; 650 anatop-vol-bit-width = <5>; 651 anatop-min-bit-val = <0>; 652 anatop-min-voltage = <2100000>; 653 anatop-max-voltage = <2875000>; 654 anatop-enable-bit = <0>; 655 }; 656 657 reg_arm: regulator-vddcore { 658 compatible = "fsl,anatop-regulator"; 659 regulator-name = "vddarm"; 660 regulator-min-microvolt = <725000>; 661 regulator-max-microvolt = <1450000>; 662 regulator-always-on; 663 anatop-reg-offset = <0x140>; 664 anatop-vol-bit-shift = <0>; 665 anatop-vol-bit-width = <5>; 666 anatop-delay-reg-offset = <0x170>; 667 anatop-delay-bit-shift = <24>; 668 anatop-delay-bit-width = <2>; 669 anatop-min-bit-val = <1>; 670 anatop-min-voltage = <725000>; 671 anatop-max-voltage = <1450000>; 672 }; 673 674 reg_pcie: regulator-vddpcie { 675 compatible = "fsl,anatop-regulator"; 676 regulator-name = "vddpcie"; 677 regulator-min-microvolt = <725000>; 678 regulator-max-microvolt = <1450000>; 679 anatop-reg-offset = <0x140>; 680 anatop-vol-bit-shift = <9>; 681 anatop-vol-bit-width = <5>; 682 anatop-delay-reg-offset = <0x170>; 683 anatop-delay-bit-shift = <26>; 684 anatop-delay-bit-width = <2>; 685 anatop-min-bit-val = <1>; 686 anatop-min-voltage = <725000>; 687 anatop-max-voltage = <1450000>; 688 }; 689 690 reg_soc: regulator-vddsoc { 691 compatible = "fsl,anatop-regulator"; 692 regulator-name = "vddsoc"; 693 regulator-min-microvolt = <725000>; 694 regulator-max-microvolt = <1450000>; 695 regulator-always-on; 696 anatop-reg-offset = <0x140>; 697 anatop-vol-bit-shift = <18>; 698 anatop-vol-bit-width = <5>; 699 anatop-delay-reg-offset = <0x170>; 700 anatop-delay-bit-shift = <28>; 701 anatop-delay-bit-width = <2>; 702 anatop-min-bit-val = <1>; 703 anatop-min-voltage = <725000>; 704 anatop-max-voltage = <1450000>; 705 }; 706 }; 707 708 usbphy1: usbphy@20c9000 { 709 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy"; 710 reg = <0x020c9000 0x1000>; 711 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 712 clocks = <&clks IMX6SX_CLK_USBPHY1>; 713 fsl,anatop = <&anatop>; 714 }; 715 716 usbphy2: usbphy@20ca000 { 717 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy"; 718 reg = <0x020ca000 0x1000>; 719 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 720 clocks = <&clks IMX6SX_CLK_USBPHY2>; 721 fsl,anatop = <&anatop>; 722 }; 723 724 snvs: snvs@20cc000 { 725 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; 726 reg = <0x020cc000 0x4000>; 727 728 snvs_rtc: snvs-rtc-lp { 729 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 730 regmap = <&snvs>; 731 offset = <0x34>; 732 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 733 }; 734 735 snvs_poweroff: snvs-poweroff { 736 compatible = "syscon-poweroff"; 737 regmap = <&snvs>; 738 offset = <0x38>; 739 value = <0x60>; 740 mask = <0x60>; 741 status = "disabled"; 742 }; 743 744 snvs_pwrkey: snvs-powerkey { 745 compatible = "fsl,sec-v4.0-pwrkey"; 746 regmap = <&snvs>; 747 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 748 linux,keycode = <KEY_POWER>; 749 wakeup-source; 750 status = "disabled"; 751 }; 752 }; 753 754 epit1: epit@20d0000 { 755 reg = <0x020d0000 0x4000>; 756 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 757 }; 758 759 epit2: epit@20d4000 { 760 reg = <0x020d4000 0x4000>; 761 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 762 }; 763 764 src: src@20d8000 { 765 compatible = "fsl,imx6sx-src", "fsl,imx51-src"; 766 reg = <0x020d8000 0x4000>; 767 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 768 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 769 #reset-cells = <1>; 770 }; 771 772 gpc: gpc@20dc000 { 773 compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc"; 774 reg = <0x020dc000 0x4000>; 775 interrupt-controller; 776 #interrupt-cells = <3>; 777 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 778 interrupt-parent = <&intc>; 779 clocks = <&clks IMX6SX_CLK_IPG>; 780 clock-names = "ipg"; 781 782 pgc { 783 #address-cells = <1>; 784 #size-cells = <0>; 785 786 power-domain@0 { 787 reg = <0>; 788 #power-domain-cells = <0>; 789 }; 790 791 pd_pu: power-domain@1 { 792 reg = <1>; 793 #power-domain-cells = <0>; 794 power-supply = <®_soc>; 795 clocks = <&clks IMX6SX_CLK_GPU>; 796 }; 797 798 pd_disp: power-domain@2 { 799 reg = <2>; 800 #power-domain-cells = <0>; 801 clocks = <&clks IMX6SX_CLK_PXP_AXI>, 802 <&clks IMX6SX_CLK_DISPLAY_AXI>, 803 <&clks IMX6SX_CLK_LCDIF1_PIX>, 804 <&clks IMX6SX_CLK_LCDIF_APB>, 805 <&clks IMX6SX_CLK_LCDIF2_PIX>, 806 <&clks IMX6SX_CLK_CSI>, 807 <&clks IMX6SX_CLK_VADC>; 808 }; 809 810 pd_pci: power-domain@3 { 811 reg = <3>; 812 #power-domain-cells = <0>; 813 power-supply = <®_pcie>; 814 }; 815 }; 816 }; 817 818 iomuxc: iomuxc@20e0000 { 819 compatible = "fsl,imx6sx-iomuxc"; 820 reg = <0x020e0000 0x4000>; 821 }; 822 823 gpr: iomuxc-gpr@20e4000 { 824 compatible = "fsl,imx6sx-iomuxc-gpr", 825 "fsl,imx6q-iomuxc-gpr", "syscon"; 826 reg = <0x020e4000 0x4000>; 827 }; 828 829 sdma: sdma@20ec000 { 830 compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma"; 831 reg = <0x020ec000 0x4000>; 832 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 833 clocks = <&clks IMX6SX_CLK_IPG>, 834 <&clks IMX6SX_CLK_SDMA>; 835 clock-names = "ipg", "ahb"; 836 #dma-cells = <3>; 837 /* imx6sx reuses imx6q sdma firmware */ 838 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; 839 }; 840 }; 841 842 aips2: aips-bus@2100000 { 843 compatible = "fsl,aips-bus", "simple-bus"; 844 #address-cells = <1>; 845 #size-cells = <1>; 846 reg = <0x02100000 0x100000>; 847 ranges; 848 849 crypto: caam@2100000 { 850 compatible = "fsl,sec-v4.0"; 851 #address-cells = <1>; 852 #size-cells = <1>; 853 reg = <0x2100000 0x10000>; 854 ranges = <0 0x2100000 0x10000>; 855 interrupt-parent = <&intc>; 856 clocks = <&clks IMX6SX_CLK_CAAM_MEM>, 857 <&clks IMX6SX_CLK_CAAM_ACLK>, 858 <&clks IMX6SX_CLK_CAAM_IPG>, 859 <&clks IMX6SX_CLK_EIM_SLOW>; 860 clock-names = "mem", "aclk", "ipg", "emi_slow"; 861 862 sec_jr0: jr0@1000 { 863 compatible = "fsl,sec-v4.0-job-ring"; 864 reg = <0x1000 0x1000>; 865 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 866 }; 867 868 sec_jr1: jr1@2000 { 869 compatible = "fsl,sec-v4.0-job-ring"; 870 reg = <0x2000 0x1000>; 871 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 872 }; 873 }; 874 875 usbotg1: usb@2184000 { 876 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb"; 877 reg = <0x02184000 0x200>; 878 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 879 clocks = <&clks IMX6SX_CLK_USBOH3>; 880 fsl,usbphy = <&usbphy1>; 881 fsl,usbmisc = <&usbmisc 0>; 882 fsl,anatop = <&anatop>; 883 ahb-burst-config = <0x0>; 884 tx-burst-size-dword = <0x10>; 885 rx-burst-size-dword = <0x10>; 886 status = "disabled"; 887 }; 888 889 usbotg2: usb@2184200 { 890 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb"; 891 reg = <0x02184200 0x200>; 892 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 893 clocks = <&clks IMX6SX_CLK_USBOH3>; 894 fsl,usbphy = <&usbphy2>; 895 fsl,usbmisc = <&usbmisc 1>; 896 ahb-burst-config = <0x0>; 897 tx-burst-size-dword = <0x10>; 898 rx-burst-size-dword = <0x10>; 899 status = "disabled"; 900 }; 901 902 usbh: usb@2184400 { 903 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb"; 904 reg = <0x02184400 0x200>; 905 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 906 clocks = <&clks IMX6SX_CLK_USBOH3>; 907 fsl,usbphy = <&usbphynop1>; 908 fsl,usbmisc = <&usbmisc 2>; 909 phy_type = "hsic"; 910 fsl,anatop = <&anatop>; 911 dr_mode = "host"; 912 ahb-burst-config = <0x0>; 913 tx-burst-size-dword = <0x10>; 914 rx-burst-size-dword = <0x10>; 915 status = "disabled"; 916 }; 917 918 usbmisc: usbmisc@2184800 { 919 #index-cells = <1>; 920 compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc"; 921 reg = <0x02184800 0x200>; 922 clocks = <&clks IMX6SX_CLK_USBOH3>; 923 }; 924 925 fec1: ethernet@2188000 { 926 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec"; 927 reg = <0x02188000 0x4000>; 928 interrupt-names = "int0", "pps"; 929 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 930 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 931 clocks = <&clks IMX6SX_CLK_ENET>, 932 <&clks IMX6SX_CLK_ENET_AHB>, 933 <&clks IMX6SX_CLK_ENET_PTP>, 934 <&clks IMX6SX_CLK_ENET_REF>, 935 <&clks IMX6SX_CLK_ENET_PTP>; 936 clock-names = "ipg", "ahb", "ptp", 937 "enet_clk_ref", "enet_out"; 938 fsl,num-tx-queues = <3>; 939 fsl,num-rx-queues = <3>; 940 status = "disabled"; 941 }; 942 943 mlb: mlb@218c000 { 944 reg = <0x0218c000 0x4000>; 945 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 948 clocks = <&clks IMX6SX_CLK_MLB>; 949 status = "disabled"; 950 }; 951 952 usdhc1: usdhc@2190000 { 953 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; 954 reg = <0x02190000 0x4000>; 955 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 956 clocks = <&clks IMX6SX_CLK_USDHC1>, 957 <&clks IMX6SX_CLK_USDHC1>, 958 <&clks IMX6SX_CLK_USDHC1>; 959 clock-names = "ipg", "ahb", "per"; 960 bus-width = <4>; 961 fsl,tuning-start-tap = <20>; 962 fsl,tuning-step= <2>; 963 status = "disabled"; 964 }; 965 966 usdhc2: usdhc@2194000 { 967 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; 968 reg = <0x02194000 0x4000>; 969 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 970 clocks = <&clks IMX6SX_CLK_USDHC2>, 971 <&clks IMX6SX_CLK_USDHC2>, 972 <&clks IMX6SX_CLK_USDHC2>; 973 clock-names = "ipg", "ahb", "per"; 974 bus-width = <4>; 975 fsl,tuning-start-tap = <20>; 976 fsl,tuning-step= <2>; 977 status = "disabled"; 978 }; 979 980 usdhc3: usdhc@2198000 { 981 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; 982 reg = <0x02198000 0x4000>; 983 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 984 clocks = <&clks IMX6SX_CLK_USDHC3>, 985 <&clks IMX6SX_CLK_USDHC3>, 986 <&clks IMX6SX_CLK_USDHC3>; 987 clock-names = "ipg", "ahb", "per"; 988 bus-width = <4>; 989 fsl,tuning-start-tap = <20>; 990 fsl,tuning-step= <2>; 991 status = "disabled"; 992 }; 993 994 usdhc4: usdhc@219c000 { 995 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc"; 996 reg = <0x0219c000 0x4000>; 997 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 998 clocks = <&clks IMX6SX_CLK_USDHC4>, 999 <&clks IMX6SX_CLK_USDHC4>, 1000 <&clks IMX6SX_CLK_USDHC4>; 1001 clock-names = "ipg", "ahb", "per"; 1002 bus-width = <4>; 1003 status = "disabled"; 1004 }; 1005 1006 i2c1: i2c@21a0000 { 1007 #address-cells = <1>; 1008 #size-cells = <0>; 1009 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; 1010 reg = <0x021a0000 0x4000>; 1011 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1012 clocks = <&clks IMX6SX_CLK_I2C1>; 1013 status = "disabled"; 1014 }; 1015 1016 i2c2: i2c@21a4000 { 1017 #address-cells = <1>; 1018 #size-cells = <0>; 1019 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; 1020 reg = <0x021a4000 0x4000>; 1021 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1022 clocks = <&clks IMX6SX_CLK_I2C2>; 1023 status = "disabled"; 1024 }; 1025 1026 i2c3: i2c@21a8000 { 1027 #address-cells = <1>; 1028 #size-cells = <0>; 1029 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; 1030 reg = <0x021a8000 0x4000>; 1031 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 1032 clocks = <&clks IMX6SX_CLK_I2C3>; 1033 status = "disabled"; 1034 }; 1035 1036 memory-controller@21b0000 { 1037 compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc"; 1038 reg = <0x021b0000 0x4000>; 1039 clocks = <&clks IMX6SX_CLK_MMDC_P0_IPG>; 1040 }; 1041 1042 fec2: ethernet@21b4000 { 1043 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec"; 1044 reg = <0x021b4000 0x4000>; 1045 interrupt-names = "int0", "pps"; 1046 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1047 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1048 clocks = <&clks IMX6SX_CLK_ENET>, 1049 <&clks IMX6SX_CLK_ENET_AHB>, 1050 <&clks IMX6SX_CLK_ENET_PTP>, 1051 <&clks IMX6SX_CLK_ENET2_REF_125M>, 1052 <&clks IMX6SX_CLK_ENET_PTP>; 1053 clock-names = "ipg", "ahb", "ptp", 1054 "enet_clk_ref", "enet_out"; 1055 status = "disabled"; 1056 }; 1057 1058 weim: weim@21b8000 { 1059 #address-cells = <2>; 1060 #size-cells = <1>; 1061 compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim"; 1062 reg = <0x021b8000 0x4000>; 1063 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1064 clocks = <&clks IMX6SX_CLK_EIM_SLOW>; 1065 fsl,weim-cs-gpr = <&gpr>; 1066 status = "disabled"; 1067 }; 1068 1069 ocotp: ocotp@21bc000 { 1070 #address-cells = <1>; 1071 #size-cells = <1>; 1072 compatible = "fsl,imx6sx-ocotp", "syscon"; 1073 reg = <0x021bc000 0x4000>; 1074 clocks = <&clks IMX6SX_CLK_OCOTP>; 1075 1076 tempmon_calib: calib@38 { 1077 reg = <0x38 4>; 1078 }; 1079 1080 tempmon_temp_grade: temp-grade@20 { 1081 reg = <0x20 4>; 1082 }; 1083 }; 1084 1085 sai1: sai@21d4000 { 1086 compatible = "fsl,imx6sx-sai"; 1087 reg = <0x021d4000 0x4000>; 1088 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1089 clocks = <&clks IMX6SX_CLK_SAI1_IPG>, 1090 <&clks IMX6SX_CLK_SAI1>, 1091 <&clks 0>, <&clks 0>; 1092 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 1093 dma-names = "rx", "tx"; 1094 dmas = <&sdma 31 24 0>, <&sdma 32 24 0>; 1095 status = "disabled"; 1096 }; 1097 1098 audmux: audmux@21d8000 { 1099 compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux"; 1100 reg = <0x021d8000 0x4000>; 1101 status = "disabled"; 1102 }; 1103 1104 sai2: sai@21dc000 { 1105 compatible = "fsl,imx6sx-sai"; 1106 reg = <0x021dc000 0x4000>; 1107 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1108 clocks = <&clks IMX6SX_CLK_SAI2_IPG>, 1109 <&clks IMX6SX_CLK_SAI2>, 1110 <&clks 0>, <&clks 0>; 1111 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 1112 dma-names = "rx", "tx"; 1113 dmas = <&sdma 33 24 0>, <&sdma 34 24 0>; 1114 status = "disabled"; 1115 }; 1116 1117 qspi1: spi@21e0000 { 1118 #address-cells = <1>; 1119 #size-cells = <0>; 1120 compatible = "fsl,imx6sx-qspi"; 1121 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>; 1122 reg-names = "QuadSPI", "QuadSPI-memory"; 1123 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1124 clocks = <&clks IMX6SX_CLK_QSPI1>, 1125 <&clks IMX6SX_CLK_QSPI1>; 1126 clock-names = "qspi_en", "qspi"; 1127 status = "disabled"; 1128 }; 1129 1130 qspi2: spi@21e4000 { 1131 #address-cells = <1>; 1132 #size-cells = <0>; 1133 compatible = "fsl,imx6sx-qspi"; 1134 reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>; 1135 reg-names = "QuadSPI", "QuadSPI-memory"; 1136 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 1137 clocks = <&clks IMX6SX_CLK_QSPI2>, 1138 <&clks IMX6SX_CLK_QSPI2>; 1139 clock-names = "qspi_en", "qspi"; 1140 status = "disabled"; 1141 }; 1142 1143 uart2: serial@21e8000 { 1144 compatible = "fsl,imx6sx-uart", 1145 "fsl,imx6q-uart", "fsl,imx21-uart"; 1146 reg = <0x021e8000 0x4000>; 1147 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 1148 clocks = <&clks IMX6SX_CLK_UART_IPG>, 1149 <&clks IMX6SX_CLK_UART_SERIAL>; 1150 clock-names = "ipg", "per"; 1151 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; 1152 dma-names = "rx", "tx"; 1153 status = "disabled"; 1154 }; 1155 1156 uart3: serial@21ec000 { 1157 compatible = "fsl,imx6sx-uart", 1158 "fsl,imx6q-uart", "fsl,imx21-uart"; 1159 reg = <0x021ec000 0x4000>; 1160 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 1161 clocks = <&clks IMX6SX_CLK_UART_IPG>, 1162 <&clks IMX6SX_CLK_UART_SERIAL>; 1163 clock-names = "ipg", "per"; 1164 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; 1165 dma-names = "rx", "tx"; 1166 status = "disabled"; 1167 }; 1168 1169 uart4: serial@21f0000 { 1170 compatible = "fsl,imx6sx-uart", 1171 "fsl,imx6q-uart", "fsl,imx21-uart"; 1172 reg = <0x021f0000 0x4000>; 1173 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1174 clocks = <&clks IMX6SX_CLK_UART_IPG>, 1175 <&clks IMX6SX_CLK_UART_SERIAL>; 1176 clock-names = "ipg", "per"; 1177 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; 1178 dma-names = "rx", "tx"; 1179 status = "disabled"; 1180 }; 1181 1182 uart5: serial@21f4000 { 1183 compatible = "fsl,imx6sx-uart", 1184 "fsl,imx6q-uart", "fsl,imx21-uart"; 1185 reg = <0x021f4000 0x4000>; 1186 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1187 clocks = <&clks IMX6SX_CLK_UART_IPG>, 1188 <&clks IMX6SX_CLK_UART_SERIAL>; 1189 clock-names = "ipg", "per"; 1190 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; 1191 dma-names = "rx", "tx"; 1192 status = "disabled"; 1193 }; 1194 1195 i2c4: i2c@21f8000 { 1196 #address-cells = <1>; 1197 #size-cells = <0>; 1198 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c"; 1199 reg = <0x021f8000 0x4000>; 1200 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1201 clocks = <&clks IMX6SX_CLK_I2C4>; 1202 status = "disabled"; 1203 }; 1204 }; 1205 1206 aips3: aips-bus@2200000 { 1207 compatible = "fsl,aips-bus", "simple-bus"; 1208 #address-cells = <1>; 1209 #size-cells = <1>; 1210 reg = <0x02200000 0x100000>; 1211 ranges; 1212 1213 spba-bus@2240000 { 1214 compatible = "fsl,spba-bus", "simple-bus"; 1215 #address-cells = <1>; 1216 #size-cells = <1>; 1217 reg = <0x02240000 0x40000>; 1218 ranges; 1219 1220 csi1: csi@2214000 { 1221 reg = <0x02214000 0x4000>; 1222 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1223 clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>, 1224 <&clks IMX6SX_CLK_CSI>, 1225 <&clks IMX6SX_CLK_DCIC1>; 1226 clock-names = "disp-axi", "csi_mclk", "dcic"; 1227 status = "disabled"; 1228 }; 1229 1230 pxp: pxp@2218000 { 1231 compatible = "fsl,imx6sx-pxp", "fsl,imx6ull-pxp"; 1232 reg = <0x02218000 0x4000>; 1233 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1234 clocks = <&clks IMX6SX_CLK_PXP_AXI>; 1235 clock-names = "axi"; 1236 power-domains = <&pd_disp>; 1237 status = "disabled"; 1238 }; 1239 1240 csi2: csi@221c000 { 1241 reg = <0x0221c000 0x4000>; 1242 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1243 clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>, 1244 <&clks IMX6SX_CLK_CSI>, 1245 <&clks IMX6SX_CLK_DCIC2>; 1246 clock-names = "disp-axi", "csi_mclk", "dcic"; 1247 status = "disabled"; 1248 }; 1249 1250 lcdif1: lcdif@2220000 { 1251 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif"; 1252 reg = <0x02220000 0x4000>; 1253 interrupts = <GIC_SPI 5 IRQ_TYPE_EDGE_RISING>; 1254 clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>, 1255 <&clks IMX6SX_CLK_LCDIF_APB>, 1256 <&clks IMX6SX_CLK_DISPLAY_AXI>; 1257 clock-names = "pix", "axi", "disp_axi"; 1258 power-domains = <&pd_disp>; 1259 status = "disabled"; 1260 }; 1261 1262 lcdif2: lcdif@2224000 { 1263 compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif"; 1264 reg = <0x02224000 0x4000>; 1265 interrupts = <GIC_SPI 6 IRQ_TYPE_EDGE_RISING>; 1266 clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>, 1267 <&clks IMX6SX_CLK_LCDIF_APB>, 1268 <&clks IMX6SX_CLK_DISPLAY_AXI>; 1269 clock-names = "pix", "axi", "disp_axi"; 1270 power-domains = <&pd_disp>; 1271 status = "disabled"; 1272 }; 1273 1274 vadc: vadc@2228000 { 1275 reg = <0x02228000 0x4000>, <0x0222c000 0x4000>; 1276 reg-names = "vadc-vafe", "vadc-vdec"; 1277 clocks = <&clks IMX6SX_CLK_VADC>, 1278 <&clks IMX6SX_CLK_CSI>; 1279 clock-names = "vadc", "csi"; 1280 power-domains = <&pd_disp>; 1281 status = "disabled"; 1282 }; 1283 }; 1284 1285 adc1: adc@2280000 { 1286 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc"; 1287 reg = <0x02280000 0x4000>; 1288 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 1289 clocks = <&clks IMX6SX_CLK_IPG>; 1290 clock-names = "adc"; 1291 fsl,adck-max-frequency = <30000000>, <40000000>, 1292 <20000000>; 1293 status = "disabled"; 1294 }; 1295 1296 adc2: adc@2284000 { 1297 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc"; 1298 reg = <0x02284000 0x4000>; 1299 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1300 clocks = <&clks IMX6SX_CLK_IPG>; 1301 clock-names = "adc"; 1302 fsl,adck-max-frequency = <30000000>, <40000000>, 1303 <20000000>; 1304 status = "disabled"; 1305 }; 1306 1307 wdog3: wdog@2288000 { 1308 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt"; 1309 reg = <0x02288000 0x4000>; 1310 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1311 clocks = <&clks IMX6SX_CLK_IPG>; 1312 status = "disabled"; 1313 }; 1314 1315 ecspi5: spi@228c000 { 1316 #address-cells = <1>; 1317 #size-cells = <0>; 1318 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi"; 1319 reg = <0x0228c000 0x4000>; 1320 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 1321 clocks = <&clks IMX6SX_CLK_ECSPI5>, 1322 <&clks IMX6SX_CLK_ECSPI5>; 1323 clock-names = "ipg", "per"; 1324 status = "disabled"; 1325 }; 1326 1327 uart6: serial@22a0000 { 1328 compatible = "fsl,imx6sx-uart", 1329 "fsl,imx6q-uart", "fsl,imx21-uart"; 1330 reg = <0x022a0000 0x4000>; 1331 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1332 clocks = <&clks IMX6SX_CLK_UART_IPG>, 1333 <&clks IMX6SX_CLK_UART_SERIAL>; 1334 clock-names = "ipg", "per"; 1335 dmas = <&sdma 0 4 0>, <&sdma 47 4 0>; 1336 dma-names = "rx", "tx"; 1337 status = "disabled"; 1338 }; 1339 1340 pwm5: pwm@22a4000 { 1341 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 1342 reg = <0x022a4000 0x4000>; 1343 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1344 clocks = <&clks IMX6SX_CLK_PWM5>, 1345 <&clks IMX6SX_CLK_PWM5>; 1346 clock-names = "ipg", "per"; 1347 #pwm-cells = <2>; 1348 }; 1349 1350 pwm6: pwm@22a8000 { 1351 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 1352 reg = <0x022a8000 0x4000>; 1353 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1354 clocks = <&clks IMX6SX_CLK_PWM6>, 1355 <&clks IMX6SX_CLK_PWM6>; 1356 clock-names = "ipg", "per"; 1357 #pwm-cells = <2>; 1358 }; 1359 1360 pwm7: pwm@22ac000 { 1361 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 1362 reg = <0x022ac000 0x4000>; 1363 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 1364 clocks = <&clks IMX6SX_CLK_PWM7>, 1365 <&clks IMX6SX_CLK_PWM7>; 1366 clock-names = "ipg", "per"; 1367 #pwm-cells = <2>; 1368 }; 1369 1370 pwm8: pwm@22b0000 { 1371 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm"; 1372 reg = <0x0022b0000 0x4000>; 1373 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1374 clocks = <&clks IMX6SX_CLK_PWM8>, 1375 <&clks IMX6SX_CLK_PWM8>; 1376 clock-names = "ipg", "per"; 1377 #pwm-cells = <2>; 1378 }; 1379 }; 1380 1381 pcie: pcie@8ffc000 { 1382 compatible = "fsl,imx6sx-pcie", "snps,dw-pcie"; 1383 reg = <0x08ffc000 0x04000>, <0x08f00000 0x80000>; 1384 reg-names = "dbi", "config"; 1385 #address-cells = <3>; 1386 #size-cells = <2>; 1387 device_type = "pci"; 1388 bus-range = <0x00 0xff>; 1389 ranges = <0x81000000 0 0 0x08f80000 0 0x00010000 /* downstream I/O */ 1390 0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */ 1391 num-lanes = <1>; 1392 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 1393 interrupt-names = "msi"; 1394 #interrupt-cells = <1>; 1395 interrupt-map-mask = <0 0 0 0x7>; 1396 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1397 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1398 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1399 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 1400 clocks = <&clks IMX6SX_CLK_PCIE_AXI>, 1401 <&clks IMX6SX_CLK_LVDS1_OUT>, 1402 <&clks IMX6SX_CLK_PCIE_REF_125M>, 1403 <&clks IMX6SX_CLK_DISPLAY_AXI>; 1404 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi"; 1405 power-domains = <&pd_disp>, <&pd_pci>; 1406 power-domain-names = "pcie", "pcie_phy"; 1407 status = "disabled"; 1408 }; 1409 }; 1410}; 1411