1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Keystone 2 Edison SoC specific device tree 4 * 5 * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/ 6 */ 7 8clocks { 9 mainpllclk: mainpllclk@2310110 { 10 #clock-cells = <0>; 11 compatible = "ti,keystone,main-pll-clock"; 12 clocks = <&refclksys>; 13 reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>; 14 reg-names = "control", "multiplier", "post-divider"; 15 }; 16 17 papllclk: papllclk@2620358 { 18 #clock-cells = <0>; 19 compatible = "ti,keystone,pll-clock"; 20 clocks = <&refclkpass>; 21 clock-output-names = "papllclk"; 22 reg = <0x02620358 4>; 23 reg-names = "control"; 24 }; 25 26 ddr3apllclk: ddr3apllclk@2620360 { 27 #clock-cells = <0>; 28 compatible = "ti,keystone,pll-clock"; 29 clocks = <&refclkddr3a>; 30 clock-output-names = "ddr-3a-pll-clk"; 31 reg = <0x02620360 4>; 32 reg-names = "control"; 33 }; 34 35 clkusb1: clkusb1@2350004 { 36 #clock-cells = <0>; 37 compatible = "ti,keystone,psc-clock"; 38 clocks = <&chipclk16>; 39 clock-output-names = "usb1"; 40 reg = <0x02350004 0xb00>, <0x02350000 0x400>; 41 reg-names = "control", "domain"; 42 domain-id = <0>; 43 }; 44 45 clkhyperlink0: clkhyperlink0@2350030 { 46 #clock-cells = <0>; 47 compatible = "ti,keystone,psc-clock"; 48 clocks = <&chipclk12>; 49 clock-output-names = "hyperlink-0"; 50 reg = <0x02350030 0xb00>, <0x02350014 0x400>; 51 reg-names = "control", "domain"; 52 domain-id = <5>; 53 }; 54 55 clkpcie1: clkpcie1@235006c { 56 #clock-cells = <0>; 57 compatible = "ti,keystone,psc-clock"; 58 clocks = <&chipclk12>; 59 clock-output-names = "pcie1"; 60 reg = <0x0235006c 0xb00>, <0x02350048 0x400>; 61 reg-names = "control", "domain"; 62 domain-id = <18>; 63 }; 64 65 clkxge: clkxge@23500c8 { 66 #clock-cells = <0>; 67 compatible = "ti,keystone,psc-clock"; 68 clocks = <&chipclk13>; 69 clock-output-names = "xge"; 70 reg = <0x023500c8 0xb00>, <0x02350074 0x400>; 71 reg-names = "control", "domain"; 72 domain-id = <29>; 73 }; 74}; 75