1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Driver for the Synopsys DesignWare DMA Controller 4 * 5 * Copyright (C) 2007 Atmel Corporation 6 * Copyright (C) 2010-2011 ST Microelectronics 7 */ 8 #ifndef _PLATFORM_DATA_DMA_DW_H 9 #define _PLATFORM_DATA_DMA_DW_H 10 11 #include <linux/device.h> 12 13 #define DW_DMA_MAX_NR_MASTERS 4 14 #define DW_DMA_MAX_NR_CHANNELS 8 15 16 /** 17 * struct dw_dma_slave - Controller-specific information about a slave 18 * 19 * @dma_dev: required DMA master device 20 * @src_id: src request line 21 * @dst_id: dst request line 22 * @m_master: memory master for transfers on allocated channel 23 * @p_master: peripheral master for transfers on allocated channel 24 * @channels: mask of the channels permitted for allocation (zero value means any) 25 * @hs_polarity:set active low polarity of handshake interface 26 */ 27 struct dw_dma_slave { 28 struct device *dma_dev; 29 u8 src_id; 30 u8 dst_id; 31 u8 m_master; 32 u8 p_master; 33 u8 channels; 34 bool hs_polarity; 35 }; 36 37 /** 38 * struct dw_dma_platform_data - Controller configuration parameters 39 * @nr_channels: Number of channels supported by hardware (max 8) 40 * @chan_allocation_order: Allocate channels starting from 0 or 7 41 * @chan_priority: Set channel priority increasing from 0 to 7 or 7 to 0. 42 * @block_size: Maximum block size supported by the controller 43 * @nr_masters: Number of AHB masters supported by the controller 44 * @data_width: Maximum data width supported by hardware per AHB master 45 * (in bytes, power of 2) 46 * @multi_block: Multi block transfers supported by hardware per channel. 47 * @protctl: Protection control signals setting per channel. 48 */ 49 struct dw_dma_platform_data { 50 unsigned int nr_channels; 51 #define CHAN_ALLOCATION_ASCENDING 0 /* zero to seven */ 52 #define CHAN_ALLOCATION_DESCENDING 1 /* seven to zero */ 53 unsigned char chan_allocation_order; 54 #define CHAN_PRIORITY_ASCENDING 0 /* chan0 highest */ 55 #define CHAN_PRIORITY_DESCENDING 1 /* chan7 highest */ 56 unsigned char chan_priority; 57 unsigned int block_size; 58 unsigned char nr_masters; 59 unsigned char data_width[DW_DMA_MAX_NR_MASTERS]; 60 unsigned char multi_block[DW_DMA_MAX_NR_CHANNELS]; 61 #define CHAN_PROTCTL_PRIVILEGED BIT(0) 62 #define CHAN_PROTCTL_BUFFERABLE BIT(1) 63 #define CHAN_PROTCTL_CACHEABLE BIT(2) 64 #define CHAN_PROTCTL_MASK GENMASK(2, 0) 65 unsigned char protctl; 66 }; 67 68 #endif /* _PLATFORM_DATA_DMA_DW_H */ 69