1/* 2 * Copyright 2013-2014 Freescale Semiconductor, Inc. 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This file is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This file is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public 20 * License along with this file; if not, write to the Free 21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, 22 * MA 02110-1301 USA 23 * 24 * Or, alternatively, 25 * 26 * b) Permission is hereby granted, free of charge, to any person 27 * obtaining a copy of this software and associated documentation 28 * files (the "Software"), to deal in the Software without 29 * restriction, including without limitation the rights to use, 30 * copy, modify, merge, publish, distribute, sublicense, and/or 31 * sell copies of the Software, and to permit persons to whom the 32 * Software is furnished to do so, subject to the following 33 * conditions: 34 * 35 * The above copyright notice and this permission notice shall be 36 * included in all copies or substantial portions of the Software. 37 * 38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 45 * OTHER DEALINGS IN THE SOFTWARE. 46 */ 47 48#include <dt-bindings/interrupt-controller/arm-gic.h> 49#include <dt-bindings/thermal/thermal.h> 50 51/ { 52 #address-cells = <2>; 53 #size-cells = <2>; 54 compatible = "fsl,ls1021a"; 55 interrupt-parent = <&gic>; 56 57 aliases { 58 crypto = &crypto; 59 ethernet0 = &enet0; 60 ethernet1 = &enet1; 61 ethernet2 = &enet2; 62 serial0 = &lpuart0; 63 serial1 = &lpuart1; 64 serial2 = &lpuart2; 65 serial3 = &lpuart3; 66 serial4 = &lpuart4; 67 serial5 = &lpuart5; 68 sysclk = &sysclk; 69 }; 70 71 cpus { 72 #address-cells = <1>; 73 #size-cells = <0>; 74 75 cpu0: cpu@f00 { 76 compatible = "arm,cortex-a7"; 77 device_type = "cpu"; 78 reg = <0xf00>; 79 clocks = <&clockgen 1 0>; 80 #cooling-cells = <2>; 81 }; 82 83 cpu1: cpu@f01 { 84 compatible = "arm,cortex-a7"; 85 device_type = "cpu"; 86 reg = <0xf01>; 87 clocks = <&clockgen 1 0>; 88 #cooling-cells = <2>; 89 }; 90 }; 91 92 memory { 93 device_type = "memory"; 94 reg = <0x0 0x0 0x0 0x0>; 95 }; 96 97 sysclk: sysclk { 98 compatible = "fixed-clock"; 99 #clock-cells = <0>; 100 clock-frequency = <100000000>; 101 clock-output-names = "sysclk"; 102 }; 103 104 timer { 105 compatible = "arm,armv7-timer"; 106 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 107 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 108 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 109 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 110 }; 111 112 pmu { 113 compatible = "arm,cortex-a7-pmu"; 114 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 115 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 116 interrupt-affinity = <&cpu0>, <&cpu1>; 117 }; 118 119 reboot { 120 compatible = "syscon-reboot"; 121 regmap = <&dcfg>; 122 offset = <0xb0>; 123 mask = <0x02>; 124 }; 125 126 soc { 127 compatible = "simple-bus"; 128 #address-cells = <2>; 129 #size-cells = <2>; 130 device_type = "soc"; 131 interrupt-parent = <&gic>; 132 ranges; 133 134 ddr: memory-controller@1080000 { 135 compatible = "fsl,qoriq-memory-controller"; 136 reg = <0x0 0x1080000 0x0 0x1000>; 137 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 138 big-endian; 139 }; 140 141 gic: interrupt-controller@1400000 { 142 compatible = "arm,gic-400", "arm,cortex-a7-gic"; 143 #interrupt-cells = <3>; 144 interrupt-controller; 145 reg = <0x0 0x1401000 0x0 0x1000>, 146 <0x0 0x1402000 0x0 0x2000>, 147 <0x0 0x1404000 0x0 0x2000>, 148 <0x0 0x1406000 0x0 0x2000>; 149 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 150 151 }; 152 153 msi1: msi-controller@1570e00 { 154 compatible = "fsl,ls1021a-msi"; 155 reg = <0x0 0x1570e00 0x0 0x8>; 156 msi-controller; 157 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 158 }; 159 160 msi2: msi-controller@1570e08 { 161 compatible = "fsl,ls1021a-msi"; 162 reg = <0x0 0x1570e08 0x0 0x8>; 163 msi-controller; 164 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 165 }; 166 167 ifc: ifc@1530000 { 168 compatible = "fsl,ifc", "simple-bus"; 169 reg = <0x0 0x1530000 0x0 0x10000>; 170 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 171 }; 172 173 dcfg: dcfg@1ee0000 { 174 compatible = "fsl,ls1021a-dcfg", "syscon"; 175 reg = <0x0 0x1ee0000 0x0 0x10000>; 176 big-endian; 177 }; 178 179 qspi: spi@1550000 { 180 compatible = "fsl,ls1021a-qspi"; 181 #address-cells = <1>; 182 #size-cells = <0>; 183 reg = <0x0 0x1550000 0x0 0x10000>, 184 <0x0 0x40000000 0x0 0x20000000>; 185 reg-names = "QuadSPI", "QuadSPI-memory"; 186 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 187 clock-names = "qspi_en", "qspi"; 188 clocks = <&clockgen 4 1>, <&clockgen 4 1>; 189 status = "disabled"; 190 }; 191 192 esdhc: esdhc@1560000 { 193 compatible = "fsl,ls1021a-esdhc", "fsl,esdhc"; 194 reg = <0x0 0x1560000 0x0 0x10000>; 195 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 196 clock-frequency = <0>; 197 voltage-ranges = <1800 1800 3300 3300>; 198 sdhci,auto-cmd12; 199 big-endian; 200 bus-width = <4>; 201 status = "disabled"; 202 }; 203 204 sata: sata@3200000 { 205 compatible = "fsl,ls1021a-ahci"; 206 reg = <0x0 0x3200000 0x0 0x10000>, 207 <0x0 0x20220520 0x0 0x4>; 208 reg-names = "ahci", "sata-ecc"; 209 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 210 clocks = <&clockgen 4 1>; 211 dma-coherent; 212 status = "disabled"; 213 }; 214 215 scfg: scfg@1570000 { 216 compatible = "fsl,ls1021a-scfg", "syscon"; 217 reg = <0x0 0x1570000 0x0 0x10000>; 218 big-endian; 219 }; 220 221 crypto: crypto@1700000 { 222 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 223 fsl,sec-era = <7>; 224 #address-cells = <1>; 225 #size-cells = <1>; 226 reg = <0x0 0x1700000 0x0 0x100000>; 227 ranges = <0x0 0x0 0x1700000 0x100000>; 228 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 229 230 sec_jr0: jr@10000 { 231 compatible = "fsl,sec-v5.0-job-ring", 232 "fsl,sec-v4.0-job-ring"; 233 reg = <0x10000 0x10000>; 234 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 235 }; 236 237 sec_jr1: jr@20000 { 238 compatible = "fsl,sec-v5.0-job-ring", 239 "fsl,sec-v4.0-job-ring"; 240 reg = <0x20000 0x10000>; 241 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 242 }; 243 244 sec_jr2: jr@30000 { 245 compatible = "fsl,sec-v5.0-job-ring", 246 "fsl,sec-v4.0-job-ring"; 247 reg = <0x30000 0x10000>; 248 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 249 }; 250 251 sec_jr3: jr@40000 { 252 compatible = "fsl,sec-v5.0-job-ring", 253 "fsl,sec-v4.0-job-ring"; 254 reg = <0x40000 0x10000>; 255 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 256 }; 257 258 }; 259 260 clockgen: clocking@1ee1000 { 261 compatible = "fsl,ls1021a-clockgen"; 262 reg = <0x0 0x1ee1000 0x0 0x1000>; 263 #clock-cells = <2>; 264 clocks = <&sysclk>; 265 }; 266 267 tmu: tmu@1f00000 { 268 compatible = "fsl,qoriq-tmu"; 269 reg = <0x0 0x1f00000 0x0 0x10000>; 270 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 271 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x30061>; 272 fsl,tmu-calibration = <0x00000000 0x0000000f 273 0x00000001 0x00000017 274 0x00000002 0x0000001e 275 0x00000003 0x00000026 276 0x00000004 0x0000002e 277 0x00000005 0x00000035 278 0x00000006 0x0000003d 279 0x00000007 0x00000044 280 0x00000008 0x0000004c 281 0x00000009 0x00000053 282 0x0000000a 0x0000005b 283 0x0000000b 0x00000064 284 285 0x00010000 0x00000011 286 0x00010001 0x0000001c 287 0x00010002 0x00000024 288 0x00010003 0x0000002b 289 0x00010004 0x00000034 290 0x00010005 0x00000039 291 0x00010006 0x00000042 292 0x00010007 0x0000004c 293 0x00010008 0x00000051 294 0x00010009 0x0000005a 295 0x0001000a 0x00000063 296 297 0x00020000 0x00000013 298 0x00020001 0x00000019 299 0x00020002 0x00000024 300 0x00020003 0x0000002c 301 0x00020004 0x00000035 302 0x00020005 0x0000003d 303 0x00020006 0x00000046 304 0x00020007 0x00000050 305 0x00020008 0x00000059 306 307 0x00030000 0x00000002 308 0x00030001 0x0000000d 309 0x00030002 0x00000019 310 0x00030003 0x00000024>; 311 #thermal-sensor-cells = <1>; 312 }; 313 314 dspi0: spi@2100000 { 315 compatible = "fsl,ls1021a-v1.0-dspi"; 316 #address-cells = <1>; 317 #size-cells = <0>; 318 reg = <0x0 0x2100000 0x0 0x10000>; 319 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 320 clock-names = "dspi"; 321 clocks = <&clockgen 4 1>; 322 spi-num-chipselects = <6>; 323 big-endian; 324 status = "disabled"; 325 }; 326 327 dspi1: spi@2110000 { 328 compatible = "fsl,ls1021a-v1.0-dspi"; 329 #address-cells = <1>; 330 #size-cells = <0>; 331 reg = <0x0 0x2110000 0x0 0x10000>; 332 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 333 clock-names = "dspi"; 334 clocks = <&clockgen 4 1>; 335 spi-num-chipselects = <6>; 336 big-endian; 337 status = "disabled"; 338 }; 339 340 i2c0: i2c@2180000 { 341 compatible = "fsl,vf610-i2c"; 342 #address-cells = <1>; 343 #size-cells = <0>; 344 reg = <0x0 0x2180000 0x0 0x10000>; 345 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 346 clock-names = "i2c"; 347 clocks = <&clockgen 4 1>; 348 dma-names = "tx", "rx"; 349 dmas = <&edma0 1 39>, <&edma0 1 38>; 350 status = "disabled"; 351 }; 352 353 i2c1: i2c@2190000 { 354 compatible = "fsl,vf610-i2c"; 355 #address-cells = <1>; 356 #size-cells = <0>; 357 reg = <0x0 0x2190000 0x0 0x10000>; 358 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 359 clock-names = "i2c"; 360 clocks = <&clockgen 4 1>; 361 dma-names = "tx", "rx"; 362 dmas = <&edma0 1 37>, <&edma0 1 36>; 363 status = "disabled"; 364 }; 365 366 i2c2: i2c@21a0000 { 367 compatible = "fsl,vf610-i2c"; 368 #address-cells = <1>; 369 #size-cells = <0>; 370 reg = <0x0 0x21a0000 0x0 0x10000>; 371 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 372 clock-names = "i2c"; 373 clocks = <&clockgen 4 1>; 374 dma-names = "tx", "rx"; 375 dmas = <&edma0 1 35>, <&edma0 1 34>; 376 status = "disabled"; 377 }; 378 379 uart0: serial@21c0500 { 380 compatible = "fsl,16550-FIFO64", "ns16550a"; 381 reg = <0x0 0x21c0500 0x0 0x100>; 382 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 383 clock-frequency = <0>; 384 fifo-size = <15>; 385 status = "disabled"; 386 }; 387 388 uart1: serial@21c0600 { 389 compatible = "fsl,16550-FIFO64", "ns16550a"; 390 reg = <0x0 0x21c0600 0x0 0x100>; 391 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 392 clock-frequency = <0>; 393 fifo-size = <15>; 394 status = "disabled"; 395 }; 396 397 uart2: serial@21d0500 { 398 compatible = "fsl,16550-FIFO64", "ns16550a"; 399 reg = <0x0 0x21d0500 0x0 0x100>; 400 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 401 clock-frequency = <0>; 402 fifo-size = <15>; 403 status = "disabled"; 404 }; 405 406 uart3: serial@21d0600 { 407 compatible = "fsl,16550-FIFO64", "ns16550a"; 408 reg = <0x0 0x21d0600 0x0 0x100>; 409 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 410 clock-frequency = <0>; 411 fifo-size = <15>; 412 status = "disabled"; 413 }; 414 415 counter0: counter@29d0000 { 416 compatible = "fsl,ftm-quaddec"; 417 reg = <0x0 0x29d0000 0x0 0x10000>; 418 big-endian; 419 status = "disabled"; 420 }; 421 422 counter1: counter@29e0000 { 423 compatible = "fsl,ftm-quaddec"; 424 reg = <0x0 0x29e0000 0x0 0x10000>; 425 big-endian; 426 status = "disabled"; 427 }; 428 429 counter2: counter@29f0000 { 430 compatible = "fsl,ftm-quaddec"; 431 reg = <0x0 0x29f0000 0x0 0x10000>; 432 big-endian; 433 status = "disabled"; 434 }; 435 436 counter3: counter@2a00000 { 437 compatible = "fsl,ftm-quaddec"; 438 reg = <0x0 0x2a00000 0x0 0x10000>; 439 big-endian; 440 status = "disabled"; 441 }; 442 443 gpio0: gpio@2300000 { 444 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; 445 reg = <0x0 0x2300000 0x0 0x10000>; 446 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 447 gpio-controller; 448 #gpio-cells = <2>; 449 interrupt-controller; 450 #interrupt-cells = <2>; 451 }; 452 453 gpio1: gpio@2310000 { 454 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; 455 reg = <0x0 0x2310000 0x0 0x10000>; 456 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 457 gpio-controller; 458 #gpio-cells = <2>; 459 interrupt-controller; 460 #interrupt-cells = <2>; 461 }; 462 463 gpio2: gpio@2320000 { 464 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; 465 reg = <0x0 0x2320000 0x0 0x10000>; 466 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 467 gpio-controller; 468 #gpio-cells = <2>; 469 interrupt-controller; 470 #interrupt-cells = <2>; 471 }; 472 473 gpio3: gpio@2330000 { 474 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; 475 reg = <0x0 0x2330000 0x0 0x10000>; 476 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 477 gpio-controller; 478 #gpio-cells = <2>; 479 interrupt-controller; 480 #interrupt-cells = <2>; 481 }; 482 483 lpuart0: serial@2950000 { 484 compatible = "fsl,ls1021a-lpuart"; 485 reg = <0x0 0x2950000 0x0 0x1000>; 486 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 487 clocks = <&sysclk>; 488 clock-names = "ipg"; 489 status = "disabled"; 490 }; 491 492 lpuart1: serial@2960000 { 493 compatible = "fsl,ls1021a-lpuart"; 494 reg = <0x0 0x2960000 0x0 0x1000>; 495 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 496 clocks = <&clockgen 4 1>; 497 clock-names = "ipg"; 498 status = "disabled"; 499 }; 500 501 lpuart2: serial@2970000 { 502 compatible = "fsl,ls1021a-lpuart"; 503 reg = <0x0 0x2970000 0x0 0x1000>; 504 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 505 clocks = <&clockgen 4 1>; 506 clock-names = "ipg"; 507 status = "disabled"; 508 }; 509 510 lpuart3: serial@2980000 { 511 compatible = "fsl,ls1021a-lpuart"; 512 reg = <0x0 0x2980000 0x0 0x1000>; 513 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 514 clocks = <&clockgen 4 1>; 515 clock-names = "ipg"; 516 status = "disabled"; 517 }; 518 519 lpuart4: serial@2990000 { 520 compatible = "fsl,ls1021a-lpuart"; 521 reg = <0x0 0x2990000 0x0 0x1000>; 522 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 523 clocks = <&clockgen 4 1>; 524 clock-names = "ipg"; 525 status = "disabled"; 526 }; 527 528 lpuart5: serial@29a0000 { 529 compatible = "fsl,ls1021a-lpuart"; 530 reg = <0x0 0x29a0000 0x0 0x1000>; 531 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 532 clocks = <&clockgen 4 1>; 533 clock-names = "ipg"; 534 status = "disabled"; 535 }; 536 537 pwm0: pwm@29d0000 { 538 compatible = "fsl,vf610-ftm-pwm"; 539 #pwm-cells = <3>; 540 reg = <0x0 0x29d0000 0x0 0x10000>; 541 clock-names = "ftm_sys", "ftm_ext", 542 "ftm_fix", "ftm_cnt_clk_en"; 543 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 544 <&clockgen 4 1>, <&clockgen 4 1>; 545 big-endian; 546 status = "disabled"; 547 }; 548 549 pwm1: pwm@29e0000 { 550 compatible = "fsl,vf610-ftm-pwm"; 551 #pwm-cells = <3>; 552 reg = <0x0 0x29e0000 0x0 0x10000>; 553 clock-names = "ftm_sys", "ftm_ext", 554 "ftm_fix", "ftm_cnt_clk_en"; 555 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 556 <&clockgen 4 1>, <&clockgen 4 1>; 557 big-endian; 558 status = "disabled"; 559 }; 560 561 pwm2: pwm@29f0000 { 562 compatible = "fsl,vf610-ftm-pwm"; 563 #pwm-cells = <3>; 564 reg = <0x0 0x29f0000 0x0 0x10000>; 565 clock-names = "ftm_sys", "ftm_ext", 566 "ftm_fix", "ftm_cnt_clk_en"; 567 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 568 <&clockgen 4 1>, <&clockgen 4 1>; 569 big-endian; 570 status = "disabled"; 571 }; 572 573 pwm3: pwm@2a00000 { 574 compatible = "fsl,vf610-ftm-pwm"; 575 #pwm-cells = <3>; 576 reg = <0x0 0x2a00000 0x0 0x10000>; 577 clock-names = "ftm_sys", "ftm_ext", 578 "ftm_fix", "ftm_cnt_clk_en"; 579 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 580 <&clockgen 4 1>, <&clockgen 4 1>; 581 big-endian; 582 status = "disabled"; 583 }; 584 585 pwm4: pwm@2a10000 { 586 compatible = "fsl,vf610-ftm-pwm"; 587 #pwm-cells = <3>; 588 reg = <0x0 0x2a10000 0x0 0x10000>; 589 clock-names = "ftm_sys", "ftm_ext", 590 "ftm_fix", "ftm_cnt_clk_en"; 591 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 592 <&clockgen 4 1>, <&clockgen 4 1>; 593 big-endian; 594 status = "disabled"; 595 }; 596 597 pwm5: pwm@2a20000 { 598 compatible = "fsl,vf610-ftm-pwm"; 599 #pwm-cells = <3>; 600 reg = <0x0 0x2a20000 0x0 0x10000>; 601 clock-names = "ftm_sys", "ftm_ext", 602 "ftm_fix", "ftm_cnt_clk_en"; 603 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 604 <&clockgen 4 1>, <&clockgen 4 1>; 605 big-endian; 606 status = "disabled"; 607 }; 608 609 pwm6: pwm@2a30000 { 610 compatible = "fsl,vf610-ftm-pwm"; 611 #pwm-cells = <3>; 612 reg = <0x0 0x2a30000 0x0 0x10000>; 613 clock-names = "ftm_sys", "ftm_ext", 614 "ftm_fix", "ftm_cnt_clk_en"; 615 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 616 <&clockgen 4 1>, <&clockgen 4 1>; 617 big-endian; 618 status = "disabled"; 619 }; 620 621 pwm7: pwm@2a40000 { 622 compatible = "fsl,vf610-ftm-pwm"; 623 #pwm-cells = <3>; 624 reg = <0x0 0x2a40000 0x0 0x10000>; 625 clock-names = "ftm_sys", "ftm_ext", 626 "ftm_fix", "ftm_cnt_clk_en"; 627 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 628 <&clockgen 4 1>, <&clockgen 4 1>; 629 big-endian; 630 status = "disabled"; 631 }; 632 633 wdog0: watchdog@2ad0000 { 634 compatible = "fsl,imx21-wdt"; 635 reg = <0x0 0x2ad0000 0x0 0x10000>; 636 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 637 clocks = <&clockgen 4 1>; 638 clock-names = "wdog-en"; 639 big-endian; 640 }; 641 642 sai1: sai@2b50000 { 643 #sound-dai-cells = <0>; 644 compatible = "fsl,vf610-sai"; 645 reg = <0x0 0x2b50000 0x0 0x10000>; 646 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 647 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 648 <&clockgen 4 1>, <&clockgen 4 1>; 649 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 650 dma-names = "tx", "rx"; 651 dmas = <&edma0 1 47>, 652 <&edma0 1 46>; 653 status = "disabled"; 654 }; 655 656 sai2: sai@2b60000 { 657 #sound-dai-cells = <0>; 658 compatible = "fsl,vf610-sai"; 659 reg = <0x0 0x2b60000 0x0 0x10000>; 660 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 661 clocks = <&clockgen 4 1>, <&clockgen 4 1>, 662 <&clockgen 4 1>, <&clockgen 4 1>; 663 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 664 dma-names = "tx", "rx"; 665 dmas = <&edma0 1 45>, 666 <&edma0 1 44>; 667 status = "disabled"; 668 }; 669 670 edma0: edma@2c00000 { 671 #dma-cells = <2>; 672 compatible = "fsl,vf610-edma"; 673 reg = <0x0 0x2c00000 0x0 0x10000>, 674 <0x0 0x2c10000 0x0 0x10000>, 675 <0x0 0x2c20000 0x0 0x10000>; 676 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 677 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 678 interrupt-names = "edma-tx", "edma-err"; 679 dma-channels = <32>; 680 big-endian; 681 clock-names = "dmamux0", "dmamux1"; 682 clocks = <&clockgen 4 1>, 683 <&clockgen 4 1>; 684 }; 685 686 dcu: dcu@2ce0000 { 687 compatible = "fsl,ls1021a-dcu"; 688 reg = <0x0 0x2ce0000 0x0 0x10000>; 689 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 690 clocks = <&clockgen 4 0>, 691 <&clockgen 4 0>; 692 clock-names = "dcu", "pix"; 693 big-endian; 694 status = "disabled"; 695 }; 696 697 mdio0: mdio@2d24000 { 698 compatible = "gianfar"; 699 device_type = "mdio"; 700 #address-cells = <1>; 701 #size-cells = <0>; 702 reg = <0x0 0x2d24000 0x0 0x4000>, 703 <0x0 0x2d10030 0x0 0x4>; 704 }; 705 706 mdio1: mdio@2d64000 { 707 compatible = "gianfar"; 708 device_type = "mdio"; 709 #address-cells = <1>; 710 #size-cells = <0>; 711 reg = <0x0 0x2d64000 0x0 0x4000>, 712 <0x0 0x2d50030 0x0 0x4>; 713 }; 714 715 ptp_clock@2d10e00 { 716 compatible = "fsl,etsec-ptp"; 717 reg = <0x0 0x2d10e00 0x0 0xb0>; 718 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 719 fsl,tclk-period = <5>; 720 fsl,tmr-prsc = <2>; 721 fsl,tmr-add = <0xaaaaaaab>; 722 fsl,tmr-fiper1 = <999999995>; 723 fsl,tmr-fiper2 = <999999995>; 724 fsl,max-adj = <499999999>; 725 fsl,extts-fifo; 726 }; 727 728 enet0: ethernet@2d10000 { 729 compatible = "fsl,etsec2"; 730 device_type = "network"; 731 #address-cells = <2>; 732 #size-cells = <2>; 733 interrupt-parent = <&gic>; 734 model = "eTSEC"; 735 fsl,magic-packet; 736 ranges; 737 dma-coherent; 738 739 queue-group@2d10000 { 740 #address-cells = <2>; 741 #size-cells = <2>; 742 reg = <0x0 0x2d10000 0x0 0x1000>; 743 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 744 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 745 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 746 }; 747 748 queue-group@2d14000 { 749 #address-cells = <2>; 750 #size-cells = <2>; 751 reg = <0x0 0x2d14000 0x0 0x1000>; 752 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 753 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 754 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 755 }; 756 }; 757 758 enet1: ethernet@2d50000 { 759 compatible = "fsl,etsec2"; 760 device_type = "network"; 761 #address-cells = <2>; 762 #size-cells = <2>; 763 interrupt-parent = <&gic>; 764 model = "eTSEC"; 765 ranges; 766 dma-coherent; 767 768 queue-group@2d50000 { 769 #address-cells = <2>; 770 #size-cells = <2>; 771 reg = <0x0 0x2d50000 0x0 0x1000>; 772 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 773 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 774 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 775 }; 776 777 queue-group@2d54000 { 778 #address-cells = <2>; 779 #size-cells = <2>; 780 reg = <0x0 0x2d54000 0x0 0x1000>; 781 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 782 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 783 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 784 }; 785 }; 786 787 enet2: ethernet@2d90000 { 788 compatible = "fsl,etsec2"; 789 device_type = "network"; 790 #address-cells = <2>; 791 #size-cells = <2>; 792 interrupt-parent = <&gic>; 793 model = "eTSEC"; 794 ranges; 795 dma-coherent; 796 797 queue-group@2d90000 { 798 #address-cells = <2>; 799 #size-cells = <2>; 800 reg = <0x0 0x2d90000 0x0 0x1000>; 801 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 802 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 803 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 804 }; 805 806 queue-group@2d94000 { 807 #address-cells = <2>; 808 #size-cells = <2>; 809 reg = <0x0 0x2d94000 0x0 0x1000>; 810 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 811 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 812 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 813 }; 814 }; 815 816 usb2: usb@8600000 { 817 compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr"; 818 reg = <0x0 0x8600000 0x0 0x1000>; 819 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 820 dr_mode = "host"; 821 phy_type = "ulpi"; 822 }; 823 824 usb3: usb3@3100000 { 825 compatible = "snps,dwc3"; 826 reg = <0x0 0x3100000 0x0 0x10000>; 827 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 828 dr_mode = "host"; 829 snps,quirk-frame-length-adjustment = <0x20>; 830 snps,dis_rxdet_inp3_quirk; 831 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 832 }; 833 834 pcie@3400000 { 835 compatible = "fsl,ls1021a-pcie"; 836 reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */ 837 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ 838 reg-names = "regs", "config"; 839 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 840 fsl,pcie-scfg = <&scfg 0>; 841 #address-cells = <3>; 842 #size-cells = <2>; 843 device_type = "pci"; 844 num-viewport = <6>; 845 bus-range = <0x0 0xff>; 846 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ 847 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 848 msi-parent = <&msi1>, <&msi2>; 849 #interrupt-cells = <1>; 850 interrupt-map-mask = <0 0 0 7>; 851 interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 852 <0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 853 <0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 854 <0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 855 status = "disabled"; 856 }; 857 858 pcie@3500000 { 859 compatible = "fsl,ls1021a-pcie"; 860 reg = <0x00 0x03500000 0x0 0x00010000 /* controller registers */ 861 0x48 0x00000000 0x0 0x00002000>; /* configuration space */ 862 reg-names = "regs", "config"; 863 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 864 fsl,pcie-scfg = <&scfg 1>; 865 #address-cells = <3>; 866 #size-cells = <2>; 867 device_type = "pci"; 868 num-viewport = <6>; 869 bus-range = <0x0 0xff>; 870 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ 871 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 872 msi-parent = <&msi1>, <&msi2>; 873 #interrupt-cells = <1>; 874 interrupt-map-mask = <0 0 0 7>; 875 interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 876 <0000 0 0 2 &gic GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 877 <0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 878 <0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 879 status = "disabled"; 880 }; 881 882 can0: can@2a70000 { 883 compatible = "fsl,ls1021ar2-flexcan"; 884 reg = <0x0 0x2a70000 0x0 0x1000>; 885 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 886 clocks = <&clockgen 4 1>, <&clockgen 4 1>; 887 clock-names = "ipg", "per"; 888 big-endian; 889 }; 890 891 can1: can@2a80000 { 892 compatible = "fsl,ls1021ar2-flexcan"; 893 reg = <0x0 0x2a80000 0x0 0x1000>; 894 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 895 clocks = <&clockgen 4 1>, <&clockgen 4 1>; 896 clock-names = "ipg", "per"; 897 big-endian; 898 }; 899 900 can2: can@2a90000 { 901 compatible = "fsl,ls1021ar2-flexcan"; 902 reg = <0x0 0x2a90000 0x0 0x1000>; 903 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 904 clocks = <&clockgen 4 1>, <&clockgen 4 1>; 905 clock-names = "ipg", "per"; 906 big-endian; 907 }; 908 909 can3: can@2aa0000 { 910 compatible = "fsl,ls1021ar2-flexcan"; 911 reg = <0x0 0x2aa0000 0x0 0x1000>; 912 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 913 clocks = <&clockgen 4 1>, <&clockgen 4 1>; 914 clock-names = "ipg", "per"; 915 big-endian; 916 }; 917 918 ocram1: sram@10000000 { 919 compatible = "mmio-sram"; 920 reg = <0x0 0x10000000 0x0 0x10000>; 921 #address-cells = <1>; 922 #size-cells = <1>; 923 ranges = <0x0 0x0 0x10000000 0x10000>; 924 }; 925 926 ocram2: sram@10010000 { 927 compatible = "mmio-sram"; 928 reg = <0x0 0x10010000 0x0 0x10000>; 929 #address-cells = <1>; 930 #size-cells = <1>; 931 ranges = <0x0 0x0 0x10010000 0x10000>; 932 }; 933 934 qdma: dma-controller@8390000 { 935 compatible = "fsl,ls1021a-qdma"; 936 reg = <0x0 0x8388000 0x0 0x1000>, /* Controller regs */ 937 <0x0 0x8389000 0x0 0x1000>, /* Status regs */ 938 <0x0 0x838a000 0x0 0x2000>; /* Block regs */ 939 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 940 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 941 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 942 interrupt-names = "qdma-error", 943 "qdma-queue0", "qdma-queue1"; 944 dma-channels = <8>; 945 block-number = <1>; 946 block-offset = <0x1000>; 947 fsl,dma-queues = <2>; 948 status-sizes = <64>; 949 queue-sizes = <64 64>; 950 big-endian; 951 }; 952 953 }; 954 955 thermal-zones { 956 cpu_thermal: cpu-thermal { 957 polling-delay-passive = <1000>; 958 polling-delay = <5000>; 959 960 thermal-sensors = <&tmu 0>; 961 962 trips { 963 cpu_alert: cpu-alert { 964 temperature = <85000>; 965 hysteresis = <2000>; 966 type = "passive"; 967 }; 968 cpu_crit: cpu-crit { 969 temperature = <95000>; 970 hysteresis = <2000>; 971 type = "critical"; 972 }; 973 }; 974 975 cooling-maps { 976 map0 { 977 trip = <&cpu_alert>; 978 cooling-device = 979 <&cpu0 THERMAL_NO_LIMIT 980 THERMAL_NO_LIMIT>, 981 <&cpu1 THERMAL_NO_LIMIT 982 THERMAL_NO_LIMIT>; 983 }; 984 }; 985 }; 986 }; 987}; 988