1// SPDX-License-Identifier: GPL-2.0 2/* 3 * SDM845 SoC device tree source 4 * 5 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,dispcc-sdm845.h> 9#include <dt-bindings/clock/qcom,gcc-sdm845.h> 10#include <dt-bindings/clock/qcom,gpucc-sdm845.h> 11#include <dt-bindings/clock/qcom,lpass-sdm845.h> 12#include <dt-bindings/clock/qcom,rpmh.h> 13#include <dt-bindings/clock/qcom,videocc-sdm845.h> 14#include <dt-bindings/interconnect/qcom,sdm845.h> 15#include <dt-bindings/interrupt-controller/arm-gic.h> 16#include <dt-bindings/phy/phy-qcom-qusb2.h> 17#include <dt-bindings/power/qcom-rpmpd.h> 18#include <dt-bindings/reset/qcom,sdm845-aoss.h> 19#include <dt-bindings/reset/qcom,sdm845-pdc.h> 20#include <dt-bindings/soc/qcom,rpmh-rsc.h> 21#include <dt-bindings/clock/qcom,gcc-sdm845.h> 22#include <dt-bindings/thermal/thermal.h> 23 24/ { 25 interrupt-parent = <&intc>; 26 27 #address-cells = <2>; 28 #size-cells = <2>; 29 30 aliases { 31 i2c0 = &i2c0; 32 i2c1 = &i2c1; 33 i2c2 = &i2c2; 34 i2c3 = &i2c3; 35 i2c4 = &i2c4; 36 i2c5 = &i2c5; 37 i2c6 = &i2c6; 38 i2c7 = &i2c7; 39 i2c8 = &i2c8; 40 i2c9 = &i2c9; 41 i2c10 = &i2c10; 42 i2c11 = &i2c11; 43 i2c12 = &i2c12; 44 i2c13 = &i2c13; 45 i2c14 = &i2c14; 46 i2c15 = &i2c15; 47 spi0 = &spi0; 48 spi1 = &spi1; 49 spi2 = &spi2; 50 spi3 = &spi3; 51 spi4 = &spi4; 52 spi5 = &spi5; 53 spi6 = &spi6; 54 spi7 = &spi7; 55 spi8 = &spi8; 56 spi9 = &spi9; 57 spi10 = &spi10; 58 spi11 = &spi11; 59 spi12 = &spi12; 60 spi13 = &spi13; 61 spi14 = &spi14; 62 spi15 = &spi15; 63 }; 64 65 chosen { }; 66 67 memory@80000000 { 68 device_type = "memory"; 69 /* We expect the bootloader to fill in the size */ 70 reg = <0 0x80000000 0 0>; 71 }; 72 73 reserved-memory { 74 #address-cells = <2>; 75 #size-cells = <2>; 76 ranges; 77 78 hyp_mem: memory@85700000 { 79 reg = <0 0x85700000 0 0x600000>; 80 no-map; 81 }; 82 83 xbl_mem: memory@85e00000 { 84 reg = <0 0x85e00000 0 0x100000>; 85 no-map; 86 }; 87 88 aop_mem: memory@85fc0000 { 89 reg = <0 0x85fc0000 0 0x20000>; 90 no-map; 91 }; 92 93 aop_cmd_db_mem: memory@85fe0000 { 94 compatible = "qcom,cmd-db"; 95 reg = <0x0 0x85fe0000 0 0x20000>; 96 no-map; 97 }; 98 99 smem_mem: memory@86000000 { 100 reg = <0x0 0x86000000 0 0x200000>; 101 no-map; 102 }; 103 104 tz_mem: memory@86200000 { 105 reg = <0 0x86200000 0 0x2d00000>; 106 no-map; 107 }; 108 109 rmtfs_mem: memory@88f00000 { 110 compatible = "qcom,rmtfs-mem"; 111 reg = <0 0x88f00000 0 0x200000>; 112 no-map; 113 114 qcom,client-id = <1>; 115 qcom,vmid = <15>; 116 }; 117 118 qseecom_mem: memory@8ab00000 { 119 reg = <0 0x8ab00000 0 0x1400000>; 120 no-map; 121 }; 122 123 camera_mem: memory@8bf00000 { 124 reg = <0 0x8bf00000 0 0x500000>; 125 no-map; 126 }; 127 128 ipa_fw_mem: memory@8c400000 { 129 reg = <0 0x8c400000 0 0x10000>; 130 no-map; 131 }; 132 133 ipa_gsi_mem: memory@8c410000 { 134 reg = <0 0x8c410000 0 0x5000>; 135 no-map; 136 }; 137 138 gpu_mem: memory@8c415000 { 139 reg = <0 0x8c415000 0 0x2000>; 140 no-map; 141 }; 142 143 adsp_mem: memory@8c500000 { 144 reg = <0 0x8c500000 0 0x1a00000>; 145 no-map; 146 }; 147 148 wlan_msa_mem: memory@8df00000 { 149 reg = <0 0x8df00000 0 0x100000>; 150 no-map; 151 }; 152 153 mpss_region: memory@8e000000 { 154 reg = <0 0x8e000000 0 0x7800000>; 155 no-map; 156 }; 157 158 venus_mem: memory@95800000 { 159 reg = <0 0x95800000 0 0x500000>; 160 no-map; 161 }; 162 163 cdsp_mem: memory@95d00000 { 164 reg = <0 0x95d00000 0 0x800000>; 165 no-map; 166 }; 167 168 mba_region: memory@96500000 { 169 reg = <0 0x96500000 0 0x200000>; 170 no-map; 171 }; 172 173 slpi_mem: memory@96700000 { 174 reg = <0 0x96700000 0 0x1400000>; 175 no-map; 176 }; 177 178 spss_mem: memory@97b00000 { 179 reg = <0 0x97b00000 0 0x100000>; 180 no-map; 181 }; 182 }; 183 184 cpus { 185 #address-cells = <2>; 186 #size-cells = <0>; 187 188 CPU0: cpu@0 { 189 device_type = "cpu"; 190 compatible = "qcom,kryo385"; 191 reg = <0x0 0x0>; 192 enable-method = "psci"; 193 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 194 &LITTLE_CPU_SLEEP_1 195 &CLUSTER_SLEEP_0>; 196 capacity-dmips-mhz = <607>; 197 dynamic-power-coefficient = <100>; 198 qcom,freq-domain = <&cpufreq_hw 0>; 199 #cooling-cells = <2>; 200 next-level-cache = <&L2_0>; 201 L2_0: l2-cache { 202 compatible = "cache"; 203 next-level-cache = <&L3_0>; 204 L3_0: l3-cache { 205 compatible = "cache"; 206 }; 207 }; 208 }; 209 210 CPU1: cpu@100 { 211 device_type = "cpu"; 212 compatible = "qcom,kryo385"; 213 reg = <0x0 0x100>; 214 enable-method = "psci"; 215 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 216 &LITTLE_CPU_SLEEP_1 217 &CLUSTER_SLEEP_0>; 218 capacity-dmips-mhz = <607>; 219 dynamic-power-coefficient = <100>; 220 qcom,freq-domain = <&cpufreq_hw 0>; 221 #cooling-cells = <2>; 222 next-level-cache = <&L2_100>; 223 L2_100: l2-cache { 224 compatible = "cache"; 225 next-level-cache = <&L3_0>; 226 }; 227 }; 228 229 CPU2: cpu@200 { 230 device_type = "cpu"; 231 compatible = "qcom,kryo385"; 232 reg = <0x0 0x200>; 233 enable-method = "psci"; 234 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 235 &LITTLE_CPU_SLEEP_1 236 &CLUSTER_SLEEP_0>; 237 capacity-dmips-mhz = <607>; 238 dynamic-power-coefficient = <100>; 239 qcom,freq-domain = <&cpufreq_hw 0>; 240 #cooling-cells = <2>; 241 next-level-cache = <&L2_200>; 242 L2_200: l2-cache { 243 compatible = "cache"; 244 next-level-cache = <&L3_0>; 245 }; 246 }; 247 248 CPU3: cpu@300 { 249 device_type = "cpu"; 250 compatible = "qcom,kryo385"; 251 reg = <0x0 0x300>; 252 enable-method = "psci"; 253 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 254 &LITTLE_CPU_SLEEP_1 255 &CLUSTER_SLEEP_0>; 256 capacity-dmips-mhz = <607>; 257 dynamic-power-coefficient = <100>; 258 qcom,freq-domain = <&cpufreq_hw 0>; 259 #cooling-cells = <2>; 260 next-level-cache = <&L2_300>; 261 L2_300: l2-cache { 262 compatible = "cache"; 263 next-level-cache = <&L3_0>; 264 }; 265 }; 266 267 CPU4: cpu@400 { 268 device_type = "cpu"; 269 compatible = "qcom,kryo385"; 270 reg = <0x0 0x400>; 271 enable-method = "psci"; 272 capacity-dmips-mhz = <1024>; 273 cpu-idle-states = <&BIG_CPU_SLEEP_0 274 &BIG_CPU_SLEEP_1 275 &CLUSTER_SLEEP_0>; 276 dynamic-power-coefficient = <396>; 277 qcom,freq-domain = <&cpufreq_hw 1>; 278 #cooling-cells = <2>; 279 next-level-cache = <&L2_400>; 280 L2_400: l2-cache { 281 compatible = "cache"; 282 next-level-cache = <&L3_0>; 283 }; 284 }; 285 286 CPU5: cpu@500 { 287 device_type = "cpu"; 288 compatible = "qcom,kryo385"; 289 reg = <0x0 0x500>; 290 enable-method = "psci"; 291 capacity-dmips-mhz = <1024>; 292 cpu-idle-states = <&BIG_CPU_SLEEP_0 293 &BIG_CPU_SLEEP_1 294 &CLUSTER_SLEEP_0>; 295 dynamic-power-coefficient = <396>; 296 qcom,freq-domain = <&cpufreq_hw 1>; 297 #cooling-cells = <2>; 298 next-level-cache = <&L2_500>; 299 L2_500: l2-cache { 300 compatible = "cache"; 301 next-level-cache = <&L3_0>; 302 }; 303 }; 304 305 CPU6: cpu@600 { 306 device_type = "cpu"; 307 compatible = "qcom,kryo385"; 308 reg = <0x0 0x600>; 309 enable-method = "psci"; 310 capacity-dmips-mhz = <1024>; 311 cpu-idle-states = <&BIG_CPU_SLEEP_0 312 &BIG_CPU_SLEEP_1 313 &CLUSTER_SLEEP_0>; 314 dynamic-power-coefficient = <396>; 315 qcom,freq-domain = <&cpufreq_hw 1>; 316 #cooling-cells = <2>; 317 next-level-cache = <&L2_600>; 318 L2_600: l2-cache { 319 compatible = "cache"; 320 next-level-cache = <&L3_0>; 321 }; 322 }; 323 324 CPU7: cpu@700 { 325 device_type = "cpu"; 326 compatible = "qcom,kryo385"; 327 reg = <0x0 0x700>; 328 enable-method = "psci"; 329 capacity-dmips-mhz = <1024>; 330 cpu-idle-states = <&BIG_CPU_SLEEP_0 331 &BIG_CPU_SLEEP_1 332 &CLUSTER_SLEEP_0>; 333 dynamic-power-coefficient = <396>; 334 qcom,freq-domain = <&cpufreq_hw 1>; 335 #cooling-cells = <2>; 336 next-level-cache = <&L2_700>; 337 L2_700: l2-cache { 338 compatible = "cache"; 339 next-level-cache = <&L3_0>; 340 }; 341 }; 342 343 cpu-map { 344 cluster0 { 345 core0 { 346 cpu = <&CPU0>; 347 }; 348 349 core1 { 350 cpu = <&CPU1>; 351 }; 352 353 core2 { 354 cpu = <&CPU2>; 355 }; 356 357 core3 { 358 cpu = <&CPU3>; 359 }; 360 361 core4 { 362 cpu = <&CPU4>; 363 }; 364 365 core5 { 366 cpu = <&CPU5>; 367 }; 368 369 core6 { 370 cpu = <&CPU6>; 371 }; 372 373 core7 { 374 cpu = <&CPU7>; 375 }; 376 }; 377 }; 378 379 idle-states { 380 entry-method = "psci"; 381 382 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 383 compatible = "arm,idle-state"; 384 idle-state-name = "little-power-down"; 385 arm,psci-suspend-param = <0x40000003>; 386 entry-latency-us = <350>; 387 exit-latency-us = <461>; 388 min-residency-us = <1890>; 389 local-timer-stop; 390 }; 391 392 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 393 compatible = "arm,idle-state"; 394 idle-state-name = "little-rail-power-down"; 395 arm,psci-suspend-param = <0x40000004>; 396 entry-latency-us = <360>; 397 exit-latency-us = <531>; 398 min-residency-us = <3934>; 399 local-timer-stop; 400 }; 401 402 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 403 compatible = "arm,idle-state"; 404 idle-state-name = "big-power-down"; 405 arm,psci-suspend-param = <0x40000003>; 406 entry-latency-us = <264>; 407 exit-latency-us = <621>; 408 min-residency-us = <952>; 409 local-timer-stop; 410 }; 411 412 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 413 compatible = "arm,idle-state"; 414 idle-state-name = "big-rail-power-down"; 415 arm,psci-suspend-param = <0x40000004>; 416 entry-latency-us = <702>; 417 exit-latency-us = <1061>; 418 min-residency-us = <4488>; 419 local-timer-stop; 420 }; 421 422 CLUSTER_SLEEP_0: cluster-sleep-0 { 423 compatible = "arm,idle-state"; 424 idle-state-name = "cluster-power-down"; 425 arm,psci-suspend-param = <0x400000F4>; 426 entry-latency-us = <3263>; 427 exit-latency-us = <6562>; 428 min-residency-us = <9987>; 429 local-timer-stop; 430 }; 431 }; 432 }; 433 434 pmu { 435 compatible = "arm,armv8-pmuv3"; 436 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 437 }; 438 439 timer { 440 compatible = "arm,armv8-timer"; 441 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 442 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 443 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 444 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 445 }; 446 447 clocks { 448 xo_board: xo-board { 449 compatible = "fixed-clock"; 450 #clock-cells = <0>; 451 clock-frequency = <38400000>; 452 clock-output-names = "xo_board"; 453 }; 454 455 sleep_clk: sleep-clk { 456 compatible = "fixed-clock"; 457 #clock-cells = <0>; 458 clock-frequency = <32764>; 459 }; 460 }; 461 462 firmware { 463 scm { 464 compatible = "qcom,scm-sdm845", "qcom,scm"; 465 }; 466 }; 467 468 adsp_pas: remoteproc-adsp { 469 compatible = "qcom,sdm845-adsp-pas"; 470 471 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 472 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 473 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 474 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 475 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 476 interrupt-names = "wdog", "fatal", "ready", 477 "handover", "stop-ack"; 478 479 clocks = <&rpmhcc RPMH_CXO_CLK>; 480 clock-names = "xo"; 481 482 memory-region = <&adsp_mem>; 483 484 qcom,smem-states = <&adsp_smp2p_out 0>; 485 qcom,smem-state-names = "stop"; 486 487 status = "disabled"; 488 489 glink-edge { 490 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 491 label = "lpass"; 492 qcom,remote-pid = <2>; 493 mboxes = <&apss_shared 8>; 494 fastrpc { 495 compatible = "qcom,fastrpc"; 496 qcom,glink-channels = "fastrpcglink-apps-dsp"; 497 label = "adsp"; 498 #address-cells = <1>; 499 #size-cells = <0>; 500 501 compute-cb@3 { 502 compatible = "qcom,fastrpc-compute-cb"; 503 reg = <3>; 504 iommus = <&apps_smmu 0x1823 0x0>; 505 }; 506 507 compute-cb@4 { 508 compatible = "qcom,fastrpc-compute-cb"; 509 reg = <4>; 510 iommus = <&apps_smmu 0x1824 0x0>; 511 }; 512 }; 513 }; 514 }; 515 516 cdsp_pas: remoteproc-cdsp { 517 compatible = "qcom,sdm845-cdsp-pas"; 518 519 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 520 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 521 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 522 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 523 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 524 interrupt-names = "wdog", "fatal", "ready", 525 "handover", "stop-ack"; 526 527 clocks = <&rpmhcc RPMH_CXO_CLK>; 528 clock-names = "xo"; 529 530 memory-region = <&cdsp_mem>; 531 532 qcom,smem-states = <&cdsp_smp2p_out 0>; 533 qcom,smem-state-names = "stop"; 534 535 status = "disabled"; 536 537 glink-edge { 538 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 539 label = "turing"; 540 qcom,remote-pid = <5>; 541 mboxes = <&apss_shared 4>; 542 fastrpc { 543 compatible = "qcom,fastrpc"; 544 qcom,glink-channels = "fastrpcglink-apps-dsp"; 545 label = "cdsp"; 546 #address-cells = <1>; 547 #size-cells = <0>; 548 549 compute-cb@1 { 550 compatible = "qcom,fastrpc-compute-cb"; 551 reg = <1>; 552 iommus = <&apps_smmu 0x1401 0x30>; 553 }; 554 555 compute-cb@2 { 556 compatible = "qcom,fastrpc-compute-cb"; 557 reg = <2>; 558 iommus = <&apps_smmu 0x1402 0x30>; 559 }; 560 561 compute-cb@3 { 562 compatible = "qcom,fastrpc-compute-cb"; 563 reg = <3>; 564 iommus = <&apps_smmu 0x1403 0x30>; 565 }; 566 567 compute-cb@4 { 568 compatible = "qcom,fastrpc-compute-cb"; 569 reg = <4>; 570 iommus = <&apps_smmu 0x1404 0x30>; 571 }; 572 573 compute-cb@5 { 574 compatible = "qcom,fastrpc-compute-cb"; 575 reg = <5>; 576 iommus = <&apps_smmu 0x1405 0x30>; 577 }; 578 579 compute-cb@6 { 580 compatible = "qcom,fastrpc-compute-cb"; 581 reg = <6>; 582 iommus = <&apps_smmu 0x1406 0x30>; 583 }; 584 585 compute-cb@7 { 586 compatible = "qcom,fastrpc-compute-cb"; 587 reg = <7>; 588 iommus = <&apps_smmu 0x1407 0x30>; 589 }; 590 591 compute-cb@8 { 592 compatible = "qcom,fastrpc-compute-cb"; 593 reg = <8>; 594 iommus = <&apps_smmu 0x1408 0x30>; 595 }; 596 }; 597 }; 598 }; 599 600 tcsr_mutex: hwlock { 601 compatible = "qcom,tcsr-mutex"; 602 syscon = <&tcsr_mutex_regs 0 0x1000>; 603 #hwlock-cells = <1>; 604 }; 605 606 smem { 607 compatible = "qcom,smem"; 608 memory-region = <&smem_mem>; 609 hwlocks = <&tcsr_mutex 3>; 610 }; 611 612 smp2p-cdsp { 613 compatible = "qcom,smp2p"; 614 qcom,smem = <94>, <432>; 615 616 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 617 618 mboxes = <&apss_shared 6>; 619 620 qcom,local-pid = <0>; 621 qcom,remote-pid = <5>; 622 623 cdsp_smp2p_out: master-kernel { 624 qcom,entry-name = "master-kernel"; 625 #qcom,smem-state-cells = <1>; 626 }; 627 628 cdsp_smp2p_in: slave-kernel { 629 qcom,entry-name = "slave-kernel"; 630 631 interrupt-controller; 632 #interrupt-cells = <2>; 633 }; 634 }; 635 636 smp2p-lpass { 637 compatible = "qcom,smp2p"; 638 qcom,smem = <443>, <429>; 639 640 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 641 642 mboxes = <&apss_shared 10>; 643 644 qcom,local-pid = <0>; 645 qcom,remote-pid = <2>; 646 647 adsp_smp2p_out: master-kernel { 648 qcom,entry-name = "master-kernel"; 649 #qcom,smem-state-cells = <1>; 650 }; 651 652 adsp_smp2p_in: slave-kernel { 653 qcom,entry-name = "slave-kernel"; 654 655 interrupt-controller; 656 #interrupt-cells = <2>; 657 }; 658 }; 659 660 smp2p-mpss { 661 compatible = "qcom,smp2p"; 662 qcom,smem = <435>, <428>; 663 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 664 mboxes = <&apss_shared 14>; 665 qcom,local-pid = <0>; 666 qcom,remote-pid = <1>; 667 668 modem_smp2p_out: master-kernel { 669 qcom,entry-name = "master-kernel"; 670 #qcom,smem-state-cells = <1>; 671 }; 672 673 modem_smp2p_in: slave-kernel { 674 qcom,entry-name = "slave-kernel"; 675 interrupt-controller; 676 #interrupt-cells = <2>; 677 }; 678 }; 679 680 smp2p-slpi { 681 compatible = "qcom,smp2p"; 682 qcom,smem = <481>, <430>; 683 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 684 mboxes = <&apss_shared 26>; 685 qcom,local-pid = <0>; 686 qcom,remote-pid = <3>; 687 688 slpi_smp2p_out: master-kernel { 689 qcom,entry-name = "master-kernel"; 690 #qcom,smem-state-cells = <1>; 691 }; 692 693 slpi_smp2p_in: slave-kernel { 694 qcom,entry-name = "slave-kernel"; 695 interrupt-controller; 696 #interrupt-cells = <2>; 697 }; 698 }; 699 700 psci { 701 compatible = "arm,psci-1.0"; 702 method = "smc"; 703 }; 704 705 soc: soc@0 { 706 #address-cells = <2>; 707 #size-cells = <2>; 708 ranges = <0 0 0 0 0x10 0>; 709 dma-ranges = <0 0 0 0 0x10 0>; 710 compatible = "simple-bus"; 711 712 gcc: clock-controller@100000 { 713 compatible = "qcom,gcc-sdm845"; 714 reg = <0 0x00100000 0 0x1f0000>; 715 #clock-cells = <1>; 716 #reset-cells = <1>; 717 #power-domain-cells = <1>; 718 power-domains = <&rpmhpd SDM845_CX>; 719 }; 720 721 qfprom@784000 { 722 compatible = "qcom,qfprom"; 723 reg = <0 0x00784000 0 0x8ff>; 724 #address-cells = <1>; 725 #size-cells = <1>; 726 727 qusb2p_hstx_trim: hstx-trim-primary@1eb { 728 reg = <0x1eb 0x1>; 729 bits = <1 4>; 730 }; 731 732 qusb2s_hstx_trim: hstx-trim-secondary@1eb { 733 reg = <0x1eb 0x2>; 734 bits = <6 4>; 735 }; 736 }; 737 738 rng: rng@793000 { 739 compatible = "qcom,prng-ee"; 740 reg = <0 0x00793000 0 0x1000>; 741 clocks = <&gcc GCC_PRNG_AHB_CLK>; 742 clock-names = "core"; 743 }; 744 745 qupv3_id_0: geniqup@8c0000 { 746 compatible = "qcom,geni-se-qup"; 747 reg = <0 0x008c0000 0 0x6000>; 748 clock-names = "m-ahb", "s-ahb"; 749 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 750 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 751 #address-cells = <2>; 752 #size-cells = <2>; 753 ranges; 754 status = "disabled"; 755 756 i2c0: i2c@880000 { 757 compatible = "qcom,geni-i2c"; 758 reg = <0 0x00880000 0 0x4000>; 759 clock-names = "se"; 760 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 761 pinctrl-names = "default"; 762 pinctrl-0 = <&qup_i2c0_default>; 763 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 764 #address-cells = <1>; 765 #size-cells = <0>; 766 status = "disabled"; 767 }; 768 769 spi0: spi@880000 { 770 compatible = "qcom,geni-spi"; 771 reg = <0 0x00880000 0 0x4000>; 772 clock-names = "se"; 773 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 774 pinctrl-names = "default"; 775 pinctrl-0 = <&qup_spi0_default>; 776 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 777 #address-cells = <1>; 778 #size-cells = <0>; 779 status = "disabled"; 780 }; 781 782 uart0: serial@880000 { 783 compatible = "qcom,geni-uart"; 784 reg = <0 0x00880000 0 0x4000>; 785 clock-names = "se"; 786 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 787 pinctrl-names = "default"; 788 pinctrl-0 = <&qup_uart0_default>; 789 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 790 status = "disabled"; 791 }; 792 793 i2c1: i2c@884000 { 794 compatible = "qcom,geni-i2c"; 795 reg = <0 0x00884000 0 0x4000>; 796 clock-names = "se"; 797 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 798 pinctrl-names = "default"; 799 pinctrl-0 = <&qup_i2c1_default>; 800 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 801 #address-cells = <1>; 802 #size-cells = <0>; 803 status = "disabled"; 804 }; 805 806 spi1: spi@884000 { 807 compatible = "qcom,geni-spi"; 808 reg = <0 0x00884000 0 0x4000>; 809 clock-names = "se"; 810 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 811 pinctrl-names = "default"; 812 pinctrl-0 = <&qup_spi1_default>; 813 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 814 #address-cells = <1>; 815 #size-cells = <0>; 816 status = "disabled"; 817 }; 818 819 uart1: serial@884000 { 820 compatible = "qcom,geni-uart"; 821 reg = <0 0x00884000 0 0x4000>; 822 clock-names = "se"; 823 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 824 pinctrl-names = "default"; 825 pinctrl-0 = <&qup_uart1_default>; 826 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 827 status = "disabled"; 828 }; 829 830 i2c2: i2c@888000 { 831 compatible = "qcom,geni-i2c"; 832 reg = <0 0x00888000 0 0x4000>; 833 clock-names = "se"; 834 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 835 pinctrl-names = "default"; 836 pinctrl-0 = <&qup_i2c2_default>; 837 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 838 #address-cells = <1>; 839 #size-cells = <0>; 840 status = "disabled"; 841 }; 842 843 spi2: spi@888000 { 844 compatible = "qcom,geni-spi"; 845 reg = <0 0x00888000 0 0x4000>; 846 clock-names = "se"; 847 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 848 pinctrl-names = "default"; 849 pinctrl-0 = <&qup_spi2_default>; 850 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 851 #address-cells = <1>; 852 #size-cells = <0>; 853 status = "disabled"; 854 }; 855 856 uart2: serial@888000 { 857 compatible = "qcom,geni-uart"; 858 reg = <0 0x00888000 0 0x4000>; 859 clock-names = "se"; 860 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 861 pinctrl-names = "default"; 862 pinctrl-0 = <&qup_uart2_default>; 863 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 864 status = "disabled"; 865 }; 866 867 i2c3: i2c@88c000 { 868 compatible = "qcom,geni-i2c"; 869 reg = <0 0x0088c000 0 0x4000>; 870 clock-names = "se"; 871 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 872 pinctrl-names = "default"; 873 pinctrl-0 = <&qup_i2c3_default>; 874 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 875 #address-cells = <1>; 876 #size-cells = <0>; 877 status = "disabled"; 878 }; 879 880 spi3: spi@88c000 { 881 compatible = "qcom,geni-spi"; 882 reg = <0 0x0088c000 0 0x4000>; 883 clock-names = "se"; 884 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 885 pinctrl-names = "default"; 886 pinctrl-0 = <&qup_spi3_default>; 887 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 888 #address-cells = <1>; 889 #size-cells = <0>; 890 status = "disabled"; 891 }; 892 893 uart3: serial@88c000 { 894 compatible = "qcom,geni-uart"; 895 reg = <0 0x0088c000 0 0x4000>; 896 clock-names = "se"; 897 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 898 pinctrl-names = "default"; 899 pinctrl-0 = <&qup_uart3_default>; 900 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 901 status = "disabled"; 902 }; 903 904 i2c4: i2c@890000 { 905 compatible = "qcom,geni-i2c"; 906 reg = <0 0x00890000 0 0x4000>; 907 clock-names = "se"; 908 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 909 pinctrl-names = "default"; 910 pinctrl-0 = <&qup_i2c4_default>; 911 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 912 #address-cells = <1>; 913 #size-cells = <0>; 914 status = "disabled"; 915 }; 916 917 spi4: spi@890000 { 918 compatible = "qcom,geni-spi"; 919 reg = <0 0x00890000 0 0x4000>; 920 clock-names = "se"; 921 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 922 pinctrl-names = "default"; 923 pinctrl-0 = <&qup_spi4_default>; 924 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 925 #address-cells = <1>; 926 #size-cells = <0>; 927 status = "disabled"; 928 }; 929 930 uart4: serial@890000 { 931 compatible = "qcom,geni-uart"; 932 reg = <0 0x00890000 0 0x4000>; 933 clock-names = "se"; 934 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 935 pinctrl-names = "default"; 936 pinctrl-0 = <&qup_uart4_default>; 937 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 938 status = "disabled"; 939 }; 940 941 i2c5: i2c@894000 { 942 compatible = "qcom,geni-i2c"; 943 reg = <0 0x00894000 0 0x4000>; 944 clock-names = "se"; 945 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 946 pinctrl-names = "default"; 947 pinctrl-0 = <&qup_i2c5_default>; 948 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 949 #address-cells = <1>; 950 #size-cells = <0>; 951 status = "disabled"; 952 }; 953 954 spi5: spi@894000 { 955 compatible = "qcom,geni-spi"; 956 reg = <0 0x00894000 0 0x4000>; 957 clock-names = "se"; 958 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 959 pinctrl-names = "default"; 960 pinctrl-0 = <&qup_spi5_default>; 961 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 962 #address-cells = <1>; 963 #size-cells = <0>; 964 status = "disabled"; 965 }; 966 967 uart5: serial@894000 { 968 compatible = "qcom,geni-uart"; 969 reg = <0 0x00894000 0 0x4000>; 970 clock-names = "se"; 971 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 972 pinctrl-names = "default"; 973 pinctrl-0 = <&qup_uart5_default>; 974 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 975 status = "disabled"; 976 }; 977 978 i2c6: i2c@898000 { 979 compatible = "qcom,geni-i2c"; 980 reg = <0 0x00898000 0 0x4000>; 981 clock-names = "se"; 982 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 983 pinctrl-names = "default"; 984 pinctrl-0 = <&qup_i2c6_default>; 985 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 986 #address-cells = <1>; 987 #size-cells = <0>; 988 status = "disabled"; 989 }; 990 991 spi6: spi@898000 { 992 compatible = "qcom,geni-spi"; 993 reg = <0 0x00898000 0 0x4000>; 994 clock-names = "se"; 995 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 996 pinctrl-names = "default"; 997 pinctrl-0 = <&qup_spi6_default>; 998 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 999 #address-cells = <1>; 1000 #size-cells = <0>; 1001 status = "disabled"; 1002 }; 1003 1004 uart6: serial@898000 { 1005 compatible = "qcom,geni-uart"; 1006 reg = <0 0x00898000 0 0x4000>; 1007 clock-names = "se"; 1008 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1009 pinctrl-names = "default"; 1010 pinctrl-0 = <&qup_uart6_default>; 1011 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1012 status = "disabled"; 1013 }; 1014 1015 i2c7: i2c@89c000 { 1016 compatible = "qcom,geni-i2c"; 1017 reg = <0 0x0089c000 0 0x4000>; 1018 clock-names = "se"; 1019 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1020 pinctrl-names = "default"; 1021 pinctrl-0 = <&qup_i2c7_default>; 1022 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1023 #address-cells = <1>; 1024 #size-cells = <0>; 1025 status = "disabled"; 1026 }; 1027 1028 spi7: spi@89c000 { 1029 compatible = "qcom,geni-spi"; 1030 reg = <0 0x0089c000 0 0x4000>; 1031 clock-names = "se"; 1032 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1033 pinctrl-names = "default"; 1034 pinctrl-0 = <&qup_spi7_default>; 1035 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1036 #address-cells = <1>; 1037 #size-cells = <0>; 1038 status = "disabled"; 1039 }; 1040 1041 uart7: serial@89c000 { 1042 compatible = "qcom,geni-uart"; 1043 reg = <0 0x0089c000 0 0x4000>; 1044 clock-names = "se"; 1045 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1046 pinctrl-names = "default"; 1047 pinctrl-0 = <&qup_uart7_default>; 1048 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1049 status = "disabled"; 1050 }; 1051 }; 1052 1053 qupv3_id_1: geniqup@ac0000 { 1054 compatible = "qcom,geni-se-qup"; 1055 reg = <0 0x00ac0000 0 0x6000>; 1056 clock-names = "m-ahb", "s-ahb"; 1057 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1058 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1059 #address-cells = <2>; 1060 #size-cells = <2>; 1061 ranges; 1062 status = "disabled"; 1063 1064 i2c8: i2c@a80000 { 1065 compatible = "qcom,geni-i2c"; 1066 reg = <0 0x00a80000 0 0x4000>; 1067 clock-names = "se"; 1068 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1069 pinctrl-names = "default"; 1070 pinctrl-0 = <&qup_i2c8_default>; 1071 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1072 #address-cells = <1>; 1073 #size-cells = <0>; 1074 status = "disabled"; 1075 }; 1076 1077 spi8: spi@a80000 { 1078 compatible = "qcom,geni-spi"; 1079 reg = <0 0x00a80000 0 0x4000>; 1080 clock-names = "se"; 1081 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1082 pinctrl-names = "default"; 1083 pinctrl-0 = <&qup_spi8_default>; 1084 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1085 #address-cells = <1>; 1086 #size-cells = <0>; 1087 status = "disabled"; 1088 }; 1089 1090 uart8: serial@a80000 { 1091 compatible = "qcom,geni-uart"; 1092 reg = <0 0x00a80000 0 0x4000>; 1093 clock-names = "se"; 1094 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1095 pinctrl-names = "default"; 1096 pinctrl-0 = <&qup_uart8_default>; 1097 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1098 status = "disabled"; 1099 }; 1100 1101 i2c9: i2c@a84000 { 1102 compatible = "qcom,geni-i2c"; 1103 reg = <0 0x00a84000 0 0x4000>; 1104 clock-names = "se"; 1105 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1106 pinctrl-names = "default"; 1107 pinctrl-0 = <&qup_i2c9_default>; 1108 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1109 #address-cells = <1>; 1110 #size-cells = <0>; 1111 status = "disabled"; 1112 }; 1113 1114 spi9: spi@a84000 { 1115 compatible = "qcom,geni-spi"; 1116 reg = <0 0x00a84000 0 0x4000>; 1117 clock-names = "se"; 1118 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1119 pinctrl-names = "default"; 1120 pinctrl-0 = <&qup_spi9_default>; 1121 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1122 #address-cells = <1>; 1123 #size-cells = <0>; 1124 status = "disabled"; 1125 }; 1126 1127 uart9: serial@a84000 { 1128 compatible = "qcom,geni-debug-uart"; 1129 reg = <0 0x00a84000 0 0x4000>; 1130 clock-names = "se"; 1131 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1132 pinctrl-names = "default"; 1133 pinctrl-0 = <&qup_uart9_default>; 1134 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1135 status = "disabled"; 1136 }; 1137 1138 i2c10: i2c@a88000 { 1139 compatible = "qcom,geni-i2c"; 1140 reg = <0 0x00a88000 0 0x4000>; 1141 clock-names = "se"; 1142 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1143 pinctrl-names = "default"; 1144 pinctrl-0 = <&qup_i2c10_default>; 1145 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1146 #address-cells = <1>; 1147 #size-cells = <0>; 1148 status = "disabled"; 1149 }; 1150 1151 spi10: spi@a88000 { 1152 compatible = "qcom,geni-spi"; 1153 reg = <0 0x00a88000 0 0x4000>; 1154 clock-names = "se"; 1155 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1156 pinctrl-names = "default"; 1157 pinctrl-0 = <&qup_spi10_default>; 1158 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1159 #address-cells = <1>; 1160 #size-cells = <0>; 1161 status = "disabled"; 1162 }; 1163 1164 uart10: serial@a88000 { 1165 compatible = "qcom,geni-uart"; 1166 reg = <0 0x00a88000 0 0x4000>; 1167 clock-names = "se"; 1168 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1169 pinctrl-names = "default"; 1170 pinctrl-0 = <&qup_uart10_default>; 1171 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1172 status = "disabled"; 1173 }; 1174 1175 i2c11: i2c@a8c000 { 1176 compatible = "qcom,geni-i2c"; 1177 reg = <0 0x00a8c000 0 0x4000>; 1178 clock-names = "se"; 1179 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1180 pinctrl-names = "default"; 1181 pinctrl-0 = <&qup_i2c11_default>; 1182 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1183 #address-cells = <1>; 1184 #size-cells = <0>; 1185 status = "disabled"; 1186 }; 1187 1188 spi11: spi@a8c000 { 1189 compatible = "qcom,geni-spi"; 1190 reg = <0 0x00a8c000 0 0x4000>; 1191 clock-names = "se"; 1192 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1193 pinctrl-names = "default"; 1194 pinctrl-0 = <&qup_spi11_default>; 1195 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1196 #address-cells = <1>; 1197 #size-cells = <0>; 1198 status = "disabled"; 1199 }; 1200 1201 uart11: serial@a8c000 { 1202 compatible = "qcom,geni-uart"; 1203 reg = <0 0x00a8c000 0 0x4000>; 1204 clock-names = "se"; 1205 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1206 pinctrl-names = "default"; 1207 pinctrl-0 = <&qup_uart11_default>; 1208 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1209 status = "disabled"; 1210 }; 1211 1212 i2c12: i2c@a90000 { 1213 compatible = "qcom,geni-i2c"; 1214 reg = <0 0x00a90000 0 0x4000>; 1215 clock-names = "se"; 1216 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1217 pinctrl-names = "default"; 1218 pinctrl-0 = <&qup_i2c12_default>; 1219 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1220 #address-cells = <1>; 1221 #size-cells = <0>; 1222 status = "disabled"; 1223 }; 1224 1225 spi12: spi@a90000 { 1226 compatible = "qcom,geni-spi"; 1227 reg = <0 0x00a90000 0 0x4000>; 1228 clock-names = "se"; 1229 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1230 pinctrl-names = "default"; 1231 pinctrl-0 = <&qup_spi12_default>; 1232 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1233 #address-cells = <1>; 1234 #size-cells = <0>; 1235 status = "disabled"; 1236 }; 1237 1238 uart12: serial@a90000 { 1239 compatible = "qcom,geni-uart"; 1240 reg = <0 0x00a90000 0 0x4000>; 1241 clock-names = "se"; 1242 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1243 pinctrl-names = "default"; 1244 pinctrl-0 = <&qup_uart12_default>; 1245 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1246 status = "disabled"; 1247 }; 1248 1249 i2c13: i2c@a94000 { 1250 compatible = "qcom,geni-i2c"; 1251 reg = <0 0x00a94000 0 0x4000>; 1252 clock-names = "se"; 1253 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1254 pinctrl-names = "default"; 1255 pinctrl-0 = <&qup_i2c13_default>; 1256 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1257 #address-cells = <1>; 1258 #size-cells = <0>; 1259 status = "disabled"; 1260 }; 1261 1262 spi13: spi@a94000 { 1263 compatible = "qcom,geni-spi"; 1264 reg = <0 0x00a94000 0 0x4000>; 1265 clock-names = "se"; 1266 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1267 pinctrl-names = "default"; 1268 pinctrl-0 = <&qup_spi13_default>; 1269 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1270 #address-cells = <1>; 1271 #size-cells = <0>; 1272 status = "disabled"; 1273 }; 1274 1275 uart13: serial@a94000 { 1276 compatible = "qcom,geni-uart"; 1277 reg = <0 0x00a94000 0 0x4000>; 1278 clock-names = "se"; 1279 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1280 pinctrl-names = "default"; 1281 pinctrl-0 = <&qup_uart13_default>; 1282 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1283 status = "disabled"; 1284 }; 1285 1286 i2c14: i2c@a98000 { 1287 compatible = "qcom,geni-i2c"; 1288 reg = <0 0x00a98000 0 0x4000>; 1289 clock-names = "se"; 1290 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1291 pinctrl-names = "default"; 1292 pinctrl-0 = <&qup_i2c14_default>; 1293 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1294 #address-cells = <1>; 1295 #size-cells = <0>; 1296 status = "disabled"; 1297 }; 1298 1299 spi14: spi@a98000 { 1300 compatible = "qcom,geni-spi"; 1301 reg = <0 0x00a98000 0 0x4000>; 1302 clock-names = "se"; 1303 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1304 pinctrl-names = "default"; 1305 pinctrl-0 = <&qup_spi14_default>; 1306 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1307 #address-cells = <1>; 1308 #size-cells = <0>; 1309 status = "disabled"; 1310 }; 1311 1312 uart14: serial@a98000 { 1313 compatible = "qcom,geni-uart"; 1314 reg = <0 0x00a98000 0 0x4000>; 1315 clock-names = "se"; 1316 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1317 pinctrl-names = "default"; 1318 pinctrl-0 = <&qup_uart14_default>; 1319 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1320 status = "disabled"; 1321 }; 1322 1323 i2c15: i2c@a9c000 { 1324 compatible = "qcom,geni-i2c"; 1325 reg = <0 0x00a9c000 0 0x4000>; 1326 clock-names = "se"; 1327 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1328 pinctrl-names = "default"; 1329 pinctrl-0 = <&qup_i2c15_default>; 1330 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1331 #address-cells = <1>; 1332 #size-cells = <0>; 1333 status = "disabled"; 1334 }; 1335 1336 spi15: spi@a9c000 { 1337 compatible = "qcom,geni-spi"; 1338 reg = <0 0x00a9c000 0 0x4000>; 1339 clock-names = "se"; 1340 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1341 pinctrl-names = "default"; 1342 pinctrl-0 = <&qup_spi15_default>; 1343 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1344 #address-cells = <1>; 1345 #size-cells = <0>; 1346 status = "disabled"; 1347 }; 1348 1349 uart15: serial@a9c000 { 1350 compatible = "qcom,geni-uart"; 1351 reg = <0 0x00a9c000 0 0x4000>; 1352 clock-names = "se"; 1353 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1354 pinctrl-names = "default"; 1355 pinctrl-0 = <&qup_uart15_default>; 1356 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1357 status = "disabled"; 1358 }; 1359 }; 1360 1361 cache-controller@1100000 { 1362 compatible = "qcom,sdm845-llcc"; 1363 reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>; 1364 reg-names = "llcc_base", "llcc_broadcast_base"; 1365 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 1366 }; 1367 1368 pcie0: pci@1c00000 { 1369 compatible = "qcom,pcie-sdm845", "snps,dw-pcie"; 1370 reg = <0 0x01c00000 0 0x2000>, 1371 <0 0x60000000 0 0xf1d>, 1372 <0 0x60000f20 0 0xa8>, 1373 <0 0x60100000 0 0x100000>; 1374 reg-names = "parf", "dbi", "elbi", "config"; 1375 device_type = "pci"; 1376 linux,pci-domain = <0>; 1377 bus-range = <0x00 0xff>; 1378 num-lanes = <1>; 1379 1380 #address-cells = <3>; 1381 #size-cells = <2>; 1382 1383 ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, 1384 <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0xd00000>; 1385 1386 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 1387 interrupt-names = "msi"; 1388 #interrupt-cells = <1>; 1389 interrupt-map-mask = <0 0 0 0x7>; 1390 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1391 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1392 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1393 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1394 1395 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1396 <&gcc GCC_PCIE_0_AUX_CLK>, 1397 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1398 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1399 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1400 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1401 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1402 clock-names = "pipe", 1403 "aux", 1404 "cfg", 1405 "bus_master", 1406 "bus_slave", 1407 "slave_q2a", 1408 "tbu"; 1409 1410 iommus = <&apps_smmu 0x1c10 0xf>; 1411 iommu-map = <0x0 &apps_smmu 0x1c10 0x1>, 1412 <0x100 &apps_smmu 0x1c11 0x1>, 1413 <0x200 &apps_smmu 0x1c12 0x1>, 1414 <0x300 &apps_smmu 0x1c13 0x1>, 1415 <0x400 &apps_smmu 0x1c14 0x1>, 1416 <0x500 &apps_smmu 0x1c15 0x1>, 1417 <0x600 &apps_smmu 0x1c16 0x1>, 1418 <0x700 &apps_smmu 0x1c17 0x1>, 1419 <0x800 &apps_smmu 0x1c18 0x1>, 1420 <0x900 &apps_smmu 0x1c19 0x1>, 1421 <0xa00 &apps_smmu 0x1c1a 0x1>, 1422 <0xb00 &apps_smmu 0x1c1b 0x1>, 1423 <0xc00 &apps_smmu 0x1c1c 0x1>, 1424 <0xd00 &apps_smmu 0x1c1d 0x1>, 1425 <0xe00 &apps_smmu 0x1c1e 0x1>, 1426 <0xf00 &apps_smmu 0x1c1f 0x1>; 1427 1428 resets = <&gcc GCC_PCIE_0_BCR>; 1429 reset-names = "pci"; 1430 1431 power-domains = <&gcc PCIE_0_GDSC>; 1432 1433 phys = <&pcie0_lane>; 1434 phy-names = "pciephy"; 1435 1436 status = "disabled"; 1437 }; 1438 1439 pcie0_phy: phy@1c06000 { 1440 compatible = "qcom,sdm845-qmp-pcie-phy"; 1441 reg = <0 0x01c06000 0 0x18c>; 1442 #address-cells = <2>; 1443 #size-cells = <2>; 1444 ranges; 1445 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1446 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1447 <&gcc GCC_PCIE_0_CLKREF_CLK>, 1448 <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 1449 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1450 1451 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1452 reset-names = "phy"; 1453 1454 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 1455 assigned-clock-rates = <100000000>; 1456 1457 status = "disabled"; 1458 1459 pcie0_lane: lanes@1c06200 { 1460 reg = <0 0x01c06200 0 0x128>, 1461 <0 0x01c06400 0 0x1fc>, 1462 <0 0x01c06800 0 0x218>, 1463 <0 0x01c06600 0 0x70>; 1464 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 1465 clock-names = "pipe0"; 1466 1467 #phy-cells = <0>; 1468 clock-output-names = "pcie_0_pipe_clk"; 1469 }; 1470 }; 1471 1472 pcie1: pci@1c08000 { 1473 compatible = "qcom,pcie-sdm845", "snps,dw-pcie"; 1474 reg = <0 0x01c08000 0 0x2000>, 1475 <0 0x40000000 0 0xf1d>, 1476 <0 0x40000f20 0 0xa8>, 1477 <0 0x40100000 0 0x100000>; 1478 reg-names = "parf", "dbi", "elbi", "config"; 1479 device_type = "pci"; 1480 linux,pci-domain = <1>; 1481 bus-range = <0x00 0xff>; 1482 num-lanes = <1>; 1483 1484 #address-cells = <3>; 1485 #size-cells = <2>; 1486 1487 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, 1488 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1489 1490 interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>; 1491 interrupt-names = "msi"; 1492 #interrupt-cells = <1>; 1493 interrupt-map-mask = <0 0 0 0x7>; 1494 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1495 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1496 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1497 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1498 1499 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 1500 <&gcc GCC_PCIE_1_AUX_CLK>, 1501 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1502 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1503 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1504 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1505 <&gcc GCC_PCIE_1_CLKREF_CLK>, 1506 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; 1507 clock-names = "pipe", 1508 "aux", 1509 "cfg", 1510 "bus_master", 1511 "bus_slave", 1512 "slave_q2a", 1513 "ref", 1514 "tbu"; 1515 1516 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 1517 assigned-clock-rates = <19200000>; 1518 1519 iommus = <&apps_smmu 0x1c00 0xf>; 1520 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1521 <0x100 &apps_smmu 0x1c01 0x1>, 1522 <0x200 &apps_smmu 0x1c02 0x1>, 1523 <0x300 &apps_smmu 0x1c03 0x1>, 1524 <0x400 &apps_smmu 0x1c04 0x1>, 1525 <0x500 &apps_smmu 0x1c05 0x1>, 1526 <0x600 &apps_smmu 0x1c06 0x1>, 1527 <0x700 &apps_smmu 0x1c07 0x1>, 1528 <0x800 &apps_smmu 0x1c08 0x1>, 1529 <0x900 &apps_smmu 0x1c09 0x1>, 1530 <0xa00 &apps_smmu 0x1c0a 0x1>, 1531 <0xb00 &apps_smmu 0x1c0b 0x1>, 1532 <0xc00 &apps_smmu 0x1c0c 0x1>, 1533 <0xd00 &apps_smmu 0x1c0d 0x1>, 1534 <0xe00 &apps_smmu 0x1c0e 0x1>, 1535 <0xf00 &apps_smmu 0x1c0f 0x1>; 1536 1537 resets = <&gcc GCC_PCIE_1_BCR>; 1538 reset-names = "pci"; 1539 1540 power-domains = <&gcc PCIE_1_GDSC>; 1541 1542 interconnects = <&rsc_hlos MASTER_PCIE_0 &rsc_hlos SLAVE_EBI1>; 1543 interconnect-names = "pcie-mem"; 1544 1545 phys = <&pcie1_lane>; 1546 phy-names = "pciephy"; 1547 1548 status = "disabled"; 1549 }; 1550 1551 pcie1_phy: phy@1c0a000 { 1552 compatible = "qcom,sdm845-qhp-pcie-phy"; 1553 reg = <0 0x01c0a000 0 0x800>; 1554 #address-cells = <2>; 1555 #size-cells = <2>; 1556 ranges; 1557 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1558 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1559 <&gcc GCC_PCIE_1_CLKREF_CLK>, 1560 <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 1561 clock-names = "aux", "cfg_ahb", "ref", "refgen"; 1562 1563 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1564 reset-names = "phy"; 1565 1566 assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>; 1567 assigned-clock-rates = <100000000>; 1568 1569 status = "disabled"; 1570 1571 pcie1_lane: lanes@1c06200 { 1572 reg = <0 0x01c0a800 0 0x800>, 1573 <0 0x01c0a800 0 0x800>, 1574 <0 0x01c0b800 0 0x400>; 1575 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; 1576 clock-names = "pipe0"; 1577 1578 #phy-cells = <0>; 1579 clock-output-names = "pcie_1_pipe_clk"; 1580 }; 1581 }; 1582 1583 ufs_mem_hc: ufshc@1d84000 { 1584 compatible = "qcom,sdm845-ufshc", "qcom,ufshc", 1585 "jedec,ufs-2.0"; 1586 reg = <0 0x01d84000 0 0x2500>; 1587 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1588 phys = <&ufs_mem_phy_lanes>; 1589 phy-names = "ufsphy"; 1590 lanes-per-direction = <2>; 1591 power-domains = <&gcc UFS_PHY_GDSC>; 1592 #reset-cells = <1>; 1593 1594 iommus = <&apps_smmu 0x100 0xf>; 1595 1596 clock-names = 1597 "core_clk", 1598 "bus_aggr_clk", 1599 "iface_clk", 1600 "core_clk_unipro", 1601 "ref_clk", 1602 "tx_lane0_sync_clk", 1603 "rx_lane0_sync_clk", 1604 "rx_lane1_sync_clk"; 1605 clocks = 1606 <&gcc GCC_UFS_PHY_AXI_CLK>, 1607 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1608 <&gcc GCC_UFS_PHY_AHB_CLK>, 1609 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1610 <&rpmhcc RPMH_CXO_CLK>, 1611 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1612 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1613 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 1614 freq-table-hz = 1615 <50000000 200000000>, 1616 <0 0>, 1617 <0 0>, 1618 <37500000 150000000>, 1619 <0 0>, 1620 <0 0>, 1621 <0 0>, 1622 <0 0>; 1623 1624 status = "disabled"; 1625 }; 1626 1627 ufs_mem_phy: phy@1d87000 { 1628 compatible = "qcom,sdm845-qmp-ufs-phy"; 1629 reg = <0 0x01d87000 0 0x18c>; 1630 #address-cells = <2>; 1631 #size-cells = <2>; 1632 ranges; 1633 clock-names = "ref", 1634 "ref_aux"; 1635 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, 1636 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 1637 1638 resets = <&ufs_mem_hc 0>; 1639 reset-names = "ufsphy"; 1640 status = "disabled"; 1641 1642 ufs_mem_phy_lanes: lanes@1d87400 { 1643 reg = <0 0x01d87400 0 0x108>, 1644 <0 0x01d87600 0 0x1e0>, 1645 <0 0x01d87c00 0 0x1dc>, 1646 <0 0x01d87800 0 0x108>, 1647 <0 0x01d87a00 0 0x1e0>; 1648 #phy-cells = <0>; 1649 }; 1650 }; 1651 1652 tcsr_mutex_regs: syscon@1f40000 { 1653 compatible = "syscon"; 1654 reg = <0 0x01f40000 0 0x40000>; 1655 }; 1656 1657 tlmm: pinctrl@3400000 { 1658 compatible = "qcom,sdm845-pinctrl"; 1659 reg = <0 0x03400000 0 0xc00000>; 1660 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1661 gpio-controller; 1662 #gpio-cells = <2>; 1663 interrupt-controller; 1664 #interrupt-cells = <2>; 1665 gpio-ranges = <&tlmm 0 0 150>; 1666 1667 qspi_clk: qspi-clk { 1668 pinmux { 1669 pins = "gpio95"; 1670 function = "qspi_clk"; 1671 }; 1672 }; 1673 1674 qspi_cs0: qspi-cs0 { 1675 pinmux { 1676 pins = "gpio90"; 1677 function = "qspi_cs"; 1678 }; 1679 }; 1680 1681 qspi_cs1: qspi-cs1 { 1682 pinmux { 1683 pins = "gpio89"; 1684 function = "qspi_cs"; 1685 }; 1686 }; 1687 1688 qspi_data01: qspi-data01 { 1689 pinmux-data { 1690 pins = "gpio91", "gpio92"; 1691 function = "qspi_data"; 1692 }; 1693 }; 1694 1695 qspi_data12: qspi-data12 { 1696 pinmux-data { 1697 pins = "gpio93", "gpio94"; 1698 function = "qspi_data"; 1699 }; 1700 }; 1701 1702 qup_i2c0_default: qup-i2c0-default { 1703 pinmux { 1704 pins = "gpio0", "gpio1"; 1705 function = "qup0"; 1706 }; 1707 }; 1708 1709 qup_i2c1_default: qup-i2c1-default { 1710 pinmux { 1711 pins = "gpio17", "gpio18"; 1712 function = "qup1"; 1713 }; 1714 }; 1715 1716 qup_i2c2_default: qup-i2c2-default { 1717 pinmux { 1718 pins = "gpio27", "gpio28"; 1719 function = "qup2"; 1720 }; 1721 }; 1722 1723 qup_i2c3_default: qup-i2c3-default { 1724 pinmux { 1725 pins = "gpio41", "gpio42"; 1726 function = "qup3"; 1727 }; 1728 }; 1729 1730 qup_i2c4_default: qup-i2c4-default { 1731 pinmux { 1732 pins = "gpio89", "gpio90"; 1733 function = "qup4"; 1734 }; 1735 }; 1736 1737 qup_i2c5_default: qup-i2c5-default { 1738 pinmux { 1739 pins = "gpio85", "gpio86"; 1740 function = "qup5"; 1741 }; 1742 }; 1743 1744 qup_i2c6_default: qup-i2c6-default { 1745 pinmux { 1746 pins = "gpio45", "gpio46"; 1747 function = "qup6"; 1748 }; 1749 }; 1750 1751 qup_i2c7_default: qup-i2c7-default { 1752 pinmux { 1753 pins = "gpio93", "gpio94"; 1754 function = "qup7"; 1755 }; 1756 }; 1757 1758 qup_i2c8_default: qup-i2c8-default { 1759 pinmux { 1760 pins = "gpio65", "gpio66"; 1761 function = "qup8"; 1762 }; 1763 }; 1764 1765 qup_i2c9_default: qup-i2c9-default { 1766 pinmux { 1767 pins = "gpio6", "gpio7"; 1768 function = "qup9"; 1769 }; 1770 }; 1771 1772 qup_i2c10_default: qup-i2c10-default { 1773 pinmux { 1774 pins = "gpio55", "gpio56"; 1775 function = "qup10"; 1776 }; 1777 }; 1778 1779 qup_i2c11_default: qup-i2c11-default { 1780 pinmux { 1781 pins = "gpio31", "gpio32"; 1782 function = "qup11"; 1783 }; 1784 }; 1785 1786 qup_i2c12_default: qup-i2c12-default { 1787 pinmux { 1788 pins = "gpio49", "gpio50"; 1789 function = "qup12"; 1790 }; 1791 }; 1792 1793 qup_i2c13_default: qup-i2c13-default { 1794 pinmux { 1795 pins = "gpio105", "gpio106"; 1796 function = "qup13"; 1797 }; 1798 }; 1799 1800 qup_i2c14_default: qup-i2c14-default { 1801 pinmux { 1802 pins = "gpio33", "gpio34"; 1803 function = "qup14"; 1804 }; 1805 }; 1806 1807 qup_i2c15_default: qup-i2c15-default { 1808 pinmux { 1809 pins = "gpio81", "gpio82"; 1810 function = "qup15"; 1811 }; 1812 }; 1813 1814 qup_spi0_default: qup-spi0-default { 1815 pinmux { 1816 pins = "gpio0", "gpio1", 1817 "gpio2", "gpio3"; 1818 function = "qup0"; 1819 }; 1820 }; 1821 1822 qup_spi1_default: qup-spi1-default { 1823 pinmux { 1824 pins = "gpio17", "gpio18", 1825 "gpio19", "gpio20"; 1826 function = "qup1"; 1827 }; 1828 }; 1829 1830 qup_spi2_default: qup-spi2-default { 1831 pinmux { 1832 pins = "gpio27", "gpio28", 1833 "gpio29", "gpio30"; 1834 function = "qup2"; 1835 }; 1836 }; 1837 1838 qup_spi3_default: qup-spi3-default { 1839 pinmux { 1840 pins = "gpio41", "gpio42", 1841 "gpio43", "gpio44"; 1842 function = "qup3"; 1843 }; 1844 }; 1845 1846 qup_spi4_default: qup-spi4-default { 1847 pinmux { 1848 pins = "gpio89", "gpio90", 1849 "gpio91", "gpio92"; 1850 function = "qup4"; 1851 }; 1852 }; 1853 1854 qup_spi5_default: qup-spi5-default { 1855 pinmux { 1856 pins = "gpio85", "gpio86", 1857 "gpio87", "gpio88"; 1858 function = "qup5"; 1859 }; 1860 }; 1861 1862 qup_spi6_default: qup-spi6-default { 1863 pinmux { 1864 pins = "gpio45", "gpio46", 1865 "gpio47", "gpio48"; 1866 function = "qup6"; 1867 }; 1868 }; 1869 1870 qup_spi7_default: qup-spi7-default { 1871 pinmux { 1872 pins = "gpio93", "gpio94", 1873 "gpio95", "gpio96"; 1874 function = "qup7"; 1875 }; 1876 }; 1877 1878 qup_spi8_default: qup-spi8-default { 1879 pinmux { 1880 pins = "gpio65", "gpio66", 1881 "gpio67", "gpio68"; 1882 function = "qup8"; 1883 }; 1884 }; 1885 1886 qup_spi9_default: qup-spi9-default { 1887 pinmux { 1888 pins = "gpio6", "gpio7", 1889 "gpio4", "gpio5"; 1890 function = "qup9"; 1891 }; 1892 }; 1893 1894 qup_spi10_default: qup-spi10-default { 1895 pinmux { 1896 pins = "gpio55", "gpio56", 1897 "gpio53", "gpio54"; 1898 function = "qup10"; 1899 }; 1900 }; 1901 1902 qup_spi11_default: qup-spi11-default { 1903 pinmux { 1904 pins = "gpio31", "gpio32", 1905 "gpio33", "gpio34"; 1906 function = "qup11"; 1907 }; 1908 }; 1909 1910 qup_spi12_default: qup-spi12-default { 1911 pinmux { 1912 pins = "gpio49", "gpio50", 1913 "gpio51", "gpio52"; 1914 function = "qup12"; 1915 }; 1916 }; 1917 1918 qup_spi13_default: qup-spi13-default { 1919 pinmux { 1920 pins = "gpio105", "gpio106", 1921 "gpio107", "gpio108"; 1922 function = "qup13"; 1923 }; 1924 }; 1925 1926 qup_spi14_default: qup-spi14-default { 1927 pinmux { 1928 pins = "gpio33", "gpio34", 1929 "gpio31", "gpio32"; 1930 function = "qup14"; 1931 }; 1932 }; 1933 1934 qup_spi15_default: qup-spi15-default { 1935 pinmux { 1936 pins = "gpio81", "gpio82", 1937 "gpio83", "gpio84"; 1938 function = "qup15"; 1939 }; 1940 }; 1941 1942 qup_uart0_default: qup-uart0-default { 1943 pinmux { 1944 pins = "gpio2", "gpio3"; 1945 function = "qup0"; 1946 }; 1947 }; 1948 1949 qup_uart1_default: qup-uart1-default { 1950 pinmux { 1951 pins = "gpio19", "gpio20"; 1952 function = "qup1"; 1953 }; 1954 }; 1955 1956 qup_uart2_default: qup-uart2-default { 1957 pinmux { 1958 pins = "gpio29", "gpio30"; 1959 function = "qup2"; 1960 }; 1961 }; 1962 1963 qup_uart3_default: qup-uart3-default { 1964 pinmux { 1965 pins = "gpio43", "gpio44"; 1966 function = "qup3"; 1967 }; 1968 }; 1969 1970 qup_uart4_default: qup-uart4-default { 1971 pinmux { 1972 pins = "gpio91", "gpio92"; 1973 function = "qup4"; 1974 }; 1975 }; 1976 1977 qup_uart5_default: qup-uart5-default { 1978 pinmux { 1979 pins = "gpio87", "gpio88"; 1980 function = "qup5"; 1981 }; 1982 }; 1983 1984 qup_uart6_default: qup-uart6-default { 1985 pinmux { 1986 pins = "gpio47", "gpio48"; 1987 function = "qup6"; 1988 }; 1989 }; 1990 1991 qup_uart7_default: qup-uart7-default { 1992 pinmux { 1993 pins = "gpio95", "gpio96"; 1994 function = "qup7"; 1995 }; 1996 }; 1997 1998 qup_uart8_default: qup-uart8-default { 1999 pinmux { 2000 pins = "gpio67", "gpio68"; 2001 function = "qup8"; 2002 }; 2003 }; 2004 2005 qup_uart9_default: qup-uart9-default { 2006 pinmux { 2007 pins = "gpio4", "gpio5"; 2008 function = "qup9"; 2009 }; 2010 }; 2011 2012 qup_uart10_default: qup-uart10-default { 2013 pinmux { 2014 pins = "gpio53", "gpio54"; 2015 function = "qup10"; 2016 }; 2017 }; 2018 2019 qup_uart11_default: qup-uart11-default { 2020 pinmux { 2021 pins = "gpio33", "gpio34"; 2022 function = "qup11"; 2023 }; 2024 }; 2025 2026 qup_uart12_default: qup-uart12-default { 2027 pinmux { 2028 pins = "gpio51", "gpio52"; 2029 function = "qup12"; 2030 }; 2031 }; 2032 2033 qup_uart13_default: qup-uart13-default { 2034 pinmux { 2035 pins = "gpio107", "gpio108"; 2036 function = "qup13"; 2037 }; 2038 }; 2039 2040 qup_uart14_default: qup-uart14-default { 2041 pinmux { 2042 pins = "gpio31", "gpio32"; 2043 function = "qup14"; 2044 }; 2045 }; 2046 2047 qup_uart15_default: qup-uart15-default { 2048 pinmux { 2049 pins = "gpio83", "gpio84"; 2050 function = "qup15"; 2051 }; 2052 }; 2053 }; 2054 2055 mss_pil: remoteproc@4080000 { 2056 compatible = "qcom,sdm845-mss-pil"; 2057 reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>; 2058 reg-names = "qdsp6", "rmb"; 2059 2060 interrupts-extended = 2061 <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 2062 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2063 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2064 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2065 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2066 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2067 interrupt-names = "wdog", "fatal", "ready", 2068 "handover", "stop-ack", 2069 "shutdown-ack"; 2070 2071 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 2072 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, 2073 <&gcc GCC_BOOT_ROM_AHB_CLK>, 2074 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>, 2075 <&gcc GCC_MSS_SNOC_AXI_CLK>, 2076 <&gcc GCC_MSS_MFAB_AXIS_CLK>, 2077 <&gcc GCC_PRNG_AHB_CLK>, 2078 <&rpmhcc RPMH_CXO_CLK>; 2079 clock-names = "iface", "bus", "mem", "gpll0_mss", 2080 "snoc_axi", "mnoc_axi", "prng", "xo"; 2081 2082 qcom,smem-states = <&modem_smp2p_out 0>; 2083 qcom,smem-state-names = "stop"; 2084 2085 resets = <&aoss_reset AOSS_CC_MSS_RESTART>, 2086 <&pdc_reset PDC_MODEM_SYNC_RESET>; 2087 reset-names = "mss_restart", "pdc_reset"; 2088 2089 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; 2090 2091 power-domains = <&aoss_qmp 2>, 2092 <&rpmhpd SDM845_CX>, 2093 <&rpmhpd SDM845_MX>, 2094 <&rpmhpd SDM845_MSS>; 2095 power-domain-names = "load_state", "cx", "mx", "mss"; 2096 2097 mba { 2098 memory-region = <&mba_region>; 2099 }; 2100 2101 mpss { 2102 memory-region = <&mpss_region>; 2103 }; 2104 2105 glink-edge { 2106 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 2107 label = "modem"; 2108 qcom,remote-pid = <1>; 2109 mboxes = <&apss_shared 12>; 2110 }; 2111 }; 2112 2113 gpucc: clock-controller@5090000 { 2114 compatible = "qcom,sdm845-gpucc"; 2115 reg = <0 0x05090000 0 0x9000>; 2116 #clock-cells = <1>; 2117 #reset-cells = <1>; 2118 #power-domain-cells = <1>; 2119 clocks = <&rpmhcc RPMH_CXO_CLK>; 2120 clock-names = "xo"; 2121 }; 2122 2123 stm@6002000 { 2124 compatible = "arm,coresight-stm", "arm,primecell"; 2125 reg = <0 0x06002000 0 0x1000>, 2126 <0 0x16280000 0 0x180000>; 2127 reg-names = "stm-base", "stm-stimulus-base"; 2128 2129 clocks = <&aoss_qmp>; 2130 clock-names = "apb_pclk"; 2131 2132 out-ports { 2133 port { 2134 stm_out: endpoint { 2135 remote-endpoint = 2136 <&funnel0_in7>; 2137 }; 2138 }; 2139 }; 2140 }; 2141 2142 funnel@6041000 { 2143 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2144 reg = <0 0x06041000 0 0x1000>; 2145 2146 clocks = <&aoss_qmp>; 2147 clock-names = "apb_pclk"; 2148 2149 out-ports { 2150 port { 2151 funnel0_out: endpoint { 2152 remote-endpoint = 2153 <&merge_funnel_in0>; 2154 }; 2155 }; 2156 }; 2157 2158 in-ports { 2159 #address-cells = <1>; 2160 #size-cells = <0>; 2161 2162 port@7 { 2163 reg = <7>; 2164 funnel0_in7: endpoint { 2165 remote-endpoint = <&stm_out>; 2166 }; 2167 }; 2168 }; 2169 }; 2170 2171 funnel@6043000 { 2172 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2173 reg = <0 0x06043000 0 0x1000>; 2174 2175 clocks = <&aoss_qmp>; 2176 clock-names = "apb_pclk"; 2177 2178 out-ports { 2179 port { 2180 funnel2_out: endpoint { 2181 remote-endpoint = 2182 <&merge_funnel_in2>; 2183 }; 2184 }; 2185 }; 2186 2187 in-ports { 2188 #address-cells = <1>; 2189 #size-cells = <0>; 2190 2191 port@5 { 2192 reg = <5>; 2193 funnel2_in5: endpoint { 2194 remote-endpoint = 2195 <&apss_merge_funnel_out>; 2196 }; 2197 }; 2198 }; 2199 }; 2200 2201 funnel@6045000 { 2202 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2203 reg = <0 0x06045000 0 0x1000>; 2204 2205 clocks = <&aoss_qmp>; 2206 clock-names = "apb_pclk"; 2207 2208 out-ports { 2209 port { 2210 merge_funnel_out: endpoint { 2211 remote-endpoint = <&etf_in>; 2212 }; 2213 }; 2214 }; 2215 2216 in-ports { 2217 #address-cells = <1>; 2218 #size-cells = <0>; 2219 2220 port@0 { 2221 reg = <0>; 2222 merge_funnel_in0: endpoint { 2223 remote-endpoint = 2224 <&funnel0_out>; 2225 }; 2226 }; 2227 2228 port@2 { 2229 reg = <2>; 2230 merge_funnel_in2: endpoint { 2231 remote-endpoint = 2232 <&funnel2_out>; 2233 }; 2234 }; 2235 }; 2236 }; 2237 2238 replicator@6046000 { 2239 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2240 reg = <0 0x06046000 0 0x1000>; 2241 2242 clocks = <&aoss_qmp>; 2243 clock-names = "apb_pclk"; 2244 2245 out-ports { 2246 port { 2247 replicator_out: endpoint { 2248 remote-endpoint = <&etr_in>; 2249 }; 2250 }; 2251 }; 2252 2253 in-ports { 2254 port { 2255 replicator_in: endpoint { 2256 remote-endpoint = <&etf_out>; 2257 }; 2258 }; 2259 }; 2260 }; 2261 2262 etf@6047000 { 2263 compatible = "arm,coresight-tmc", "arm,primecell"; 2264 reg = <0 0x06047000 0 0x1000>; 2265 2266 clocks = <&aoss_qmp>; 2267 clock-names = "apb_pclk"; 2268 2269 out-ports { 2270 port { 2271 etf_out: endpoint { 2272 remote-endpoint = 2273 <&replicator_in>; 2274 }; 2275 }; 2276 }; 2277 2278 in-ports { 2279 #address-cells = <1>; 2280 #size-cells = <0>; 2281 2282 port@1 { 2283 reg = <1>; 2284 etf_in: endpoint { 2285 remote-endpoint = 2286 <&merge_funnel_out>; 2287 }; 2288 }; 2289 }; 2290 }; 2291 2292 etr@6048000 { 2293 compatible = "arm,coresight-tmc", "arm,primecell"; 2294 reg = <0 0x06048000 0 0x1000>; 2295 2296 clocks = <&aoss_qmp>; 2297 clock-names = "apb_pclk"; 2298 arm,scatter-gather; 2299 2300 in-ports { 2301 port { 2302 etr_in: endpoint { 2303 remote-endpoint = 2304 <&replicator_out>; 2305 }; 2306 }; 2307 }; 2308 }; 2309 2310 etm@7040000 { 2311 compatible = "arm,coresight-etm4x", "arm,primecell"; 2312 reg = <0 0x07040000 0 0x1000>; 2313 2314 cpu = <&CPU0>; 2315 2316 clocks = <&aoss_qmp>; 2317 clock-names = "apb_pclk"; 2318 2319 out-ports { 2320 port { 2321 etm0_out: endpoint { 2322 remote-endpoint = 2323 <&apss_funnel_in0>; 2324 }; 2325 }; 2326 }; 2327 }; 2328 2329 etm@7140000 { 2330 compatible = "arm,coresight-etm4x", "arm,primecell"; 2331 reg = <0 0x07140000 0 0x1000>; 2332 2333 cpu = <&CPU1>; 2334 2335 clocks = <&aoss_qmp>; 2336 clock-names = "apb_pclk"; 2337 2338 out-ports { 2339 port { 2340 etm1_out: endpoint { 2341 remote-endpoint = 2342 <&apss_funnel_in1>; 2343 }; 2344 }; 2345 }; 2346 }; 2347 2348 etm@7240000 { 2349 compatible = "arm,coresight-etm4x", "arm,primecell"; 2350 reg = <0 0x07240000 0 0x1000>; 2351 2352 cpu = <&CPU2>; 2353 2354 clocks = <&aoss_qmp>; 2355 clock-names = "apb_pclk"; 2356 2357 out-ports { 2358 port { 2359 etm2_out: endpoint { 2360 remote-endpoint = 2361 <&apss_funnel_in2>; 2362 }; 2363 }; 2364 }; 2365 }; 2366 2367 etm@7340000 { 2368 compatible = "arm,coresight-etm4x", "arm,primecell"; 2369 reg = <0 0x07340000 0 0x1000>; 2370 2371 cpu = <&CPU3>; 2372 2373 clocks = <&aoss_qmp>; 2374 clock-names = "apb_pclk"; 2375 2376 out-ports { 2377 port { 2378 etm3_out: endpoint { 2379 remote-endpoint = 2380 <&apss_funnel_in3>; 2381 }; 2382 }; 2383 }; 2384 }; 2385 2386 etm@7440000 { 2387 compatible = "arm,coresight-etm4x", "arm,primecell"; 2388 reg = <0 0x07440000 0 0x1000>; 2389 2390 cpu = <&CPU4>; 2391 2392 clocks = <&aoss_qmp>; 2393 clock-names = "apb_pclk"; 2394 2395 out-ports { 2396 port { 2397 etm4_out: endpoint { 2398 remote-endpoint = 2399 <&apss_funnel_in4>; 2400 }; 2401 }; 2402 }; 2403 }; 2404 2405 etm@7540000 { 2406 compatible = "arm,coresight-etm4x", "arm,primecell"; 2407 reg = <0 0x07540000 0 0x1000>; 2408 2409 cpu = <&CPU5>; 2410 2411 clocks = <&aoss_qmp>; 2412 clock-names = "apb_pclk"; 2413 2414 out-ports { 2415 port { 2416 etm5_out: endpoint { 2417 remote-endpoint = 2418 <&apss_funnel_in5>; 2419 }; 2420 }; 2421 }; 2422 }; 2423 2424 etm@7640000 { 2425 compatible = "arm,coresight-etm4x", "arm,primecell"; 2426 reg = <0 0x07640000 0 0x1000>; 2427 2428 cpu = <&CPU6>; 2429 2430 clocks = <&aoss_qmp>; 2431 clock-names = "apb_pclk"; 2432 2433 out-ports { 2434 port { 2435 etm6_out: endpoint { 2436 remote-endpoint = 2437 <&apss_funnel_in6>; 2438 }; 2439 }; 2440 }; 2441 }; 2442 2443 etm@7740000 { 2444 compatible = "arm,coresight-etm4x", "arm,primecell"; 2445 reg = <0 0x07740000 0 0x1000>; 2446 2447 cpu = <&CPU7>; 2448 2449 clocks = <&aoss_qmp>; 2450 clock-names = "apb_pclk"; 2451 2452 out-ports { 2453 port { 2454 etm7_out: endpoint { 2455 remote-endpoint = 2456 <&apss_funnel_in7>; 2457 }; 2458 }; 2459 }; 2460 }; 2461 2462 funnel@7800000 { /* APSS Funnel */ 2463 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2464 reg = <0 0x07800000 0 0x1000>; 2465 2466 clocks = <&aoss_qmp>; 2467 clock-names = "apb_pclk"; 2468 2469 out-ports { 2470 port { 2471 apss_funnel_out: endpoint { 2472 remote-endpoint = 2473 <&apss_merge_funnel_in>; 2474 }; 2475 }; 2476 }; 2477 2478 in-ports { 2479 #address-cells = <1>; 2480 #size-cells = <0>; 2481 2482 port@0 { 2483 reg = <0>; 2484 apss_funnel_in0: endpoint { 2485 remote-endpoint = 2486 <&etm0_out>; 2487 }; 2488 }; 2489 2490 port@1 { 2491 reg = <1>; 2492 apss_funnel_in1: endpoint { 2493 remote-endpoint = 2494 <&etm1_out>; 2495 }; 2496 }; 2497 2498 port@2 { 2499 reg = <2>; 2500 apss_funnel_in2: endpoint { 2501 remote-endpoint = 2502 <&etm2_out>; 2503 }; 2504 }; 2505 2506 port@3 { 2507 reg = <3>; 2508 apss_funnel_in3: endpoint { 2509 remote-endpoint = 2510 <&etm3_out>; 2511 }; 2512 }; 2513 2514 port@4 { 2515 reg = <4>; 2516 apss_funnel_in4: endpoint { 2517 remote-endpoint = 2518 <&etm4_out>; 2519 }; 2520 }; 2521 2522 port@5 { 2523 reg = <5>; 2524 apss_funnel_in5: endpoint { 2525 remote-endpoint = 2526 <&etm5_out>; 2527 }; 2528 }; 2529 2530 port@6 { 2531 reg = <6>; 2532 apss_funnel_in6: endpoint { 2533 remote-endpoint = 2534 <&etm6_out>; 2535 }; 2536 }; 2537 2538 port@7 { 2539 reg = <7>; 2540 apss_funnel_in7: endpoint { 2541 remote-endpoint = 2542 <&etm7_out>; 2543 }; 2544 }; 2545 }; 2546 }; 2547 2548 funnel@7810000 { 2549 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2550 reg = <0 0x07810000 0 0x1000>; 2551 2552 clocks = <&aoss_qmp>; 2553 clock-names = "apb_pclk"; 2554 2555 out-ports { 2556 port { 2557 apss_merge_funnel_out: endpoint { 2558 remote-endpoint = 2559 <&funnel2_in5>; 2560 }; 2561 }; 2562 }; 2563 2564 in-ports { 2565 port { 2566 apss_merge_funnel_in: endpoint { 2567 remote-endpoint = 2568 <&apss_funnel_out>; 2569 }; 2570 }; 2571 }; 2572 }; 2573 2574 sdhc_2: sdhci@8804000 { 2575 compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5"; 2576 reg = <0 0x08804000 0 0x1000>; 2577 2578 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 2579 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 2580 interrupt-names = "hc_irq", "pwr_irq"; 2581 2582 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2583 <&gcc GCC_SDCC2_APPS_CLK>; 2584 clock-names = "iface", "core"; 2585 iommus = <&apps_smmu 0xa0 0xf>; 2586 2587 status = "disabled"; 2588 }; 2589 2590 qspi: spi@88df000 { 2591 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1"; 2592 reg = <0 0x088df000 0 0x600>; 2593 #address-cells = <1>; 2594 #size-cells = <0>; 2595 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 2596 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 2597 <&gcc GCC_QSPI_CORE_CLK>; 2598 clock-names = "iface", "core"; 2599 status = "disabled"; 2600 }; 2601 2602 usb_1_hsphy: phy@88e2000 { 2603 compatible = "qcom,sdm845-qusb2-phy"; 2604 reg = <0 0x088e2000 0 0x400>; 2605 status = "disabled"; 2606 #phy-cells = <0>; 2607 2608 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2609 <&rpmhcc RPMH_CXO_CLK>; 2610 clock-names = "cfg_ahb", "ref"; 2611 2612 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2613 2614 nvmem-cells = <&qusb2p_hstx_trim>; 2615 }; 2616 2617 usb_2_hsphy: phy@88e3000 { 2618 compatible = "qcom,sdm845-qusb2-phy"; 2619 reg = <0 0x088e3000 0 0x400>; 2620 status = "disabled"; 2621 #phy-cells = <0>; 2622 2623 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2624 <&rpmhcc RPMH_CXO_CLK>; 2625 clock-names = "cfg_ahb", "ref"; 2626 2627 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2628 2629 nvmem-cells = <&qusb2s_hstx_trim>; 2630 }; 2631 2632 usb_1_qmpphy: phy@88e9000 { 2633 compatible = "qcom,sdm845-qmp-usb3-phy"; 2634 reg = <0 0x088e9000 0 0x18c>, 2635 <0 0x088e8000 0 0x10>; 2636 reg-names = "reg-base", "dp_com"; 2637 status = "disabled"; 2638 #clock-cells = <1>; 2639 #address-cells = <2>; 2640 #size-cells = <2>; 2641 ranges; 2642 2643 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2644 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2645 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 2646 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2647 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 2648 2649 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2650 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2651 reset-names = "phy", "common"; 2652 2653 usb_1_ssphy: lanes@88e9200 { 2654 reg = <0 0x088e9200 0 0x128>, 2655 <0 0x088e9400 0 0x200>, 2656 <0 0x088e9c00 0 0x218>, 2657 <0 0x088e9600 0 0x128>, 2658 <0 0x088e9800 0 0x200>, 2659 <0 0x088e9a00 0 0x100>; 2660 #phy-cells = <0>; 2661 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2662 clock-names = "pipe0"; 2663 clock-output-names = "usb3_phy_pipe_clk_src"; 2664 }; 2665 }; 2666 2667 usb_2_qmpphy: phy@88eb000 { 2668 compatible = "qcom,sdm845-qmp-usb3-uni-phy"; 2669 reg = <0 0x088eb000 0 0x18c>; 2670 status = "disabled"; 2671 #clock-cells = <1>; 2672 #address-cells = <2>; 2673 #size-cells = <2>; 2674 ranges; 2675 2676 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2677 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2678 <&gcc GCC_USB3_SEC_CLKREF_CLK>, 2679 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 2680 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 2681 2682 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 2683 <&gcc GCC_USB3_PHY_SEC_BCR>; 2684 reset-names = "phy", "common"; 2685 2686 usb_2_ssphy: lane@88eb200 { 2687 reg = <0 0x088eb200 0 0x128>, 2688 <0 0x088eb400 0 0x1fc>, 2689 <0 0x088eb800 0 0x218>, 2690 <0 0x088eb600 0 0x70>; 2691 #phy-cells = <0>; 2692 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2693 clock-names = "pipe0"; 2694 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 2695 }; 2696 }; 2697 2698 usb_1: usb@a6f8800 { 2699 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 2700 reg = <0 0x0a6f8800 0 0x400>; 2701 status = "disabled"; 2702 #address-cells = <2>; 2703 #size-cells = <2>; 2704 ranges; 2705 dma-ranges; 2706 2707 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2708 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2709 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2710 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2711 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 2712 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 2713 "sleep"; 2714 2715 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2716 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2717 assigned-clock-rates = <19200000>, <150000000>; 2718 2719 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2720 <&intc GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 2721 <&pdc_intc 8 IRQ_TYPE_EDGE_BOTH>, 2722 <&pdc_intc 9 IRQ_TYPE_EDGE_BOTH>; 2723 interrupt-names = "hs_phy_irq", "ss_phy_irq", 2724 "dm_hs_phy_irq", "dp_hs_phy_irq"; 2725 2726 power-domains = <&gcc USB30_PRIM_GDSC>; 2727 2728 resets = <&gcc GCC_USB30_PRIM_BCR>; 2729 2730 usb_1_dwc3: dwc3@a600000 { 2731 compatible = "snps,dwc3"; 2732 reg = <0 0x0a600000 0 0xcd00>; 2733 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2734 iommus = <&apps_smmu 0x740 0>; 2735 snps,dis_u2_susphy_quirk; 2736 snps,dis_enblslpm_quirk; 2737 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 2738 phy-names = "usb2-phy", "usb3-phy"; 2739 }; 2740 }; 2741 2742 usb_2: usb@a8f8800 { 2743 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 2744 reg = <0 0x0a8f8800 0 0x400>; 2745 status = "disabled"; 2746 #address-cells = <2>; 2747 #size-cells = <2>; 2748 ranges; 2749 dma-ranges; 2750 2751 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2752 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2753 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2754 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2755 <&gcc GCC_USB30_SEC_SLEEP_CLK>; 2756 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 2757 "sleep"; 2758 2759 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2760 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2761 assigned-clock-rates = <19200000>, <150000000>; 2762 2763 interrupts-extended = <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2764 <&intc GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>, 2765 <&pdc_intc 10 IRQ_TYPE_EDGE_BOTH>, 2766 <&pdc_intc 11 IRQ_TYPE_EDGE_BOTH>; 2767 interrupt-names = "hs_phy_irq", "ss_phy_irq", 2768 "dm_hs_phy_irq", "dp_hs_phy_irq"; 2769 2770 power-domains = <&gcc USB30_SEC_GDSC>; 2771 2772 resets = <&gcc GCC_USB30_SEC_BCR>; 2773 2774 usb_2_dwc3: dwc3@a800000 { 2775 compatible = "snps,dwc3"; 2776 reg = <0 0x0a800000 0 0xcd00>; 2777 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 2778 iommus = <&apps_smmu 0x760 0>; 2779 snps,dis_u2_susphy_quirk; 2780 snps,dis_enblslpm_quirk; 2781 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 2782 phy-names = "usb2-phy", "usb3-phy"; 2783 }; 2784 }; 2785 2786 video-codec@aa00000 { 2787 compatible = "qcom,sdm845-venus"; 2788 reg = <0 0x0aa00000 0 0xff000>; 2789 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 2790 power-domains = <&videocc VENUS_GDSC>; 2791 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, 2792 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 2793 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>; 2794 clock-names = "core", "iface", "bus"; 2795 iommus = <&apps_smmu 0x10a0 0x8>, 2796 <&apps_smmu 0x10b0 0x0>; 2797 memory-region = <&venus_mem>; 2798 2799 video-core0 { 2800 compatible = "venus-decoder"; 2801 clocks = <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, 2802 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>; 2803 clock-names = "core", "bus"; 2804 power-domains = <&videocc VCODEC0_GDSC>; 2805 }; 2806 2807 video-core1 { 2808 compatible = "venus-encoder"; 2809 clocks = <&videocc VIDEO_CC_VCODEC1_CORE_CLK>, 2810 <&videocc VIDEO_CC_VCODEC1_AXI_CLK>; 2811 clock-names = "core", "bus"; 2812 power-domains = <&videocc VCODEC1_GDSC>; 2813 }; 2814 }; 2815 2816 videocc: clock-controller@ab00000 { 2817 compatible = "qcom,sdm845-videocc"; 2818 reg = <0 0x0ab00000 0 0x10000>; 2819 #clock-cells = <1>; 2820 #power-domain-cells = <1>; 2821 #reset-cells = <1>; 2822 }; 2823 2824 mdss: mdss@ae00000 { 2825 compatible = "qcom,sdm845-mdss"; 2826 reg = <0 0x0ae00000 0 0x1000>; 2827 reg-names = "mdss"; 2828 2829 power-domains = <&dispcc MDSS_GDSC>; 2830 2831 clocks = <&gcc GCC_DISP_AHB_CLK>, 2832 <&gcc GCC_DISP_AXI_CLK>, 2833 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2834 clock-names = "iface", "bus", "core"; 2835 2836 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; 2837 assigned-clock-rates = <300000000>; 2838 2839 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2840 interrupt-controller; 2841 #interrupt-cells = <1>; 2842 2843 iommus = <&apps_smmu 0x880 0x8>, 2844 <&apps_smmu 0xc80 0x8>; 2845 2846 status = "disabled"; 2847 2848 #address-cells = <2>; 2849 #size-cells = <2>; 2850 ranges; 2851 2852 mdss_mdp: mdp@ae01000 { 2853 compatible = "qcom,sdm845-dpu"; 2854 reg = <0 0x0ae01000 0 0x8f000>, 2855 <0 0x0aeb0000 0 0x2008>; 2856 reg-names = "mdp", "vbif"; 2857 2858 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2859 <&dispcc DISP_CC_MDSS_AXI_CLK>, 2860 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2861 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2862 clock-names = "iface", "bus", "core", "vsync"; 2863 2864 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, 2865 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2866 assigned-clock-rates = <300000000>, 2867 <19200000>; 2868 2869 interrupt-parent = <&mdss>; 2870 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; 2871 2872 status = "disabled"; 2873 2874 ports { 2875 #address-cells = <1>; 2876 #size-cells = <0>; 2877 2878 port@0 { 2879 reg = <0>; 2880 dpu_intf1_out: endpoint { 2881 remote-endpoint = <&dsi0_in>; 2882 }; 2883 }; 2884 2885 port@1 { 2886 reg = <1>; 2887 dpu_intf2_out: endpoint { 2888 remote-endpoint = <&dsi1_in>; 2889 }; 2890 }; 2891 }; 2892 }; 2893 2894 dsi0: dsi@ae94000 { 2895 compatible = "qcom,mdss-dsi-ctrl"; 2896 reg = <0 0x0ae94000 0 0x400>; 2897 reg-names = "dsi_ctrl"; 2898 2899 interrupt-parent = <&mdss>; 2900 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; 2901 2902 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2903 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2904 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2905 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2906 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2907 <&dispcc DISP_CC_MDSS_AXI_CLK>; 2908 clock-names = "byte", 2909 "byte_intf", 2910 "pixel", 2911 "core", 2912 "iface", 2913 "bus"; 2914 2915 phys = <&dsi0_phy>; 2916 phy-names = "dsi"; 2917 2918 status = "disabled"; 2919 2920 ports { 2921 #address-cells = <1>; 2922 #size-cells = <0>; 2923 2924 port@0 { 2925 reg = <0>; 2926 dsi0_in: endpoint { 2927 remote-endpoint = <&dpu_intf1_out>; 2928 }; 2929 }; 2930 2931 port@1 { 2932 reg = <1>; 2933 dsi0_out: endpoint { 2934 }; 2935 }; 2936 }; 2937 }; 2938 2939 dsi0_phy: dsi-phy@ae94400 { 2940 compatible = "qcom,dsi-phy-10nm"; 2941 reg = <0 0x0ae94400 0 0x200>, 2942 <0 0x0ae94600 0 0x280>, 2943 <0 0x0ae94a00 0 0x1e0>; 2944 reg-names = "dsi_phy", 2945 "dsi_phy_lane", 2946 "dsi_pll"; 2947 2948 #clock-cells = <1>; 2949 #phy-cells = <0>; 2950 2951 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2952 <&rpmhcc RPMH_CXO_CLK>; 2953 clock-names = "iface", "ref"; 2954 2955 status = "disabled"; 2956 }; 2957 2958 dsi1: dsi@ae96000 { 2959 compatible = "qcom,mdss-dsi-ctrl"; 2960 reg = <0 0x0ae96000 0 0x400>; 2961 reg-names = "dsi_ctrl"; 2962 2963 interrupt-parent = <&mdss>; 2964 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; 2965 2966 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 2967 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 2968 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 2969 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 2970 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2971 <&dispcc DISP_CC_MDSS_AXI_CLK>; 2972 clock-names = "byte", 2973 "byte_intf", 2974 "pixel", 2975 "core", 2976 "iface", 2977 "bus"; 2978 2979 phys = <&dsi1_phy>; 2980 phy-names = "dsi"; 2981 2982 status = "disabled"; 2983 2984 ports { 2985 #address-cells = <1>; 2986 #size-cells = <0>; 2987 2988 port@0 { 2989 reg = <0>; 2990 dsi1_in: endpoint { 2991 remote-endpoint = <&dpu_intf2_out>; 2992 }; 2993 }; 2994 2995 port@1 { 2996 reg = <1>; 2997 dsi1_out: endpoint { 2998 }; 2999 }; 3000 }; 3001 }; 3002 3003 dsi1_phy: dsi-phy@ae96400 { 3004 compatible = "qcom,dsi-phy-10nm"; 3005 reg = <0 0x0ae96400 0 0x200>, 3006 <0 0x0ae96600 0 0x280>, 3007 <0 0x0ae96a00 0 0x10e>; 3008 reg-names = "dsi_phy", 3009 "dsi_phy_lane", 3010 "dsi_pll"; 3011 3012 #clock-cells = <1>; 3013 #phy-cells = <0>; 3014 3015 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3016 <&rpmhcc RPMH_CXO_CLK>; 3017 clock-names = "iface", "ref"; 3018 3019 status = "disabled"; 3020 }; 3021 }; 3022 3023 gpu@5000000 { 3024 compatible = "qcom,adreno-630.2", "qcom,adreno"; 3025 #stream-id-cells = <16>; 3026 3027 reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x10>; 3028 reg-names = "kgsl_3d0_reg_memory", "cx_mem"; 3029 3030 /* 3031 * Look ma, no clocks! The GPU clocks and power are 3032 * controlled entirely by the GMU 3033 */ 3034 3035 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 3036 3037 iommus = <&adreno_smmu 0>; 3038 3039 operating-points-v2 = <&gpu_opp_table>; 3040 3041 qcom,gmu = <&gmu>; 3042 3043 zap_shader: zap-shader { 3044 memory-region = <&gpu_mem>; 3045 }; 3046 3047 gpu_opp_table: opp-table { 3048 compatible = "operating-points-v2"; 3049 3050 opp-710000000 { 3051 opp-hz = /bits/ 64 <710000000>; 3052 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3053 }; 3054 3055 opp-675000000 { 3056 opp-hz = /bits/ 64 <675000000>; 3057 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3058 }; 3059 3060 opp-596000000 { 3061 opp-hz = /bits/ 64 <596000000>; 3062 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3063 }; 3064 3065 opp-520000000 { 3066 opp-hz = /bits/ 64 <520000000>; 3067 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3068 }; 3069 3070 opp-414000000 { 3071 opp-hz = /bits/ 64 <414000000>; 3072 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3073 }; 3074 3075 opp-342000000 { 3076 opp-hz = /bits/ 64 <342000000>; 3077 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3078 }; 3079 3080 opp-257000000 { 3081 opp-hz = /bits/ 64 <257000000>; 3082 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3083 }; 3084 }; 3085 }; 3086 3087 adreno_smmu: iommu@5040000 { 3088 compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2"; 3089 reg = <0 0x5040000 0 0x10000>; 3090 #iommu-cells = <1>; 3091 #global-interrupts = <2>; 3092 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 3093 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 3094 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 3095 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 3096 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 3097 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 3098 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 3099 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, 3100 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, 3101 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; 3102 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 3103 <&gcc GCC_GPU_CFG_AHB_CLK>; 3104 clock-names = "bus", "iface"; 3105 3106 power-domains = <&gpucc GPU_CX_GDSC>; 3107 }; 3108 3109 gmu: gmu@506a000 { 3110 compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu"; 3111 3112 reg = <0 0x506a000 0 0x30000>, 3113 <0 0xb280000 0 0x10000>, 3114 <0 0xb480000 0 0x10000>; 3115 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 3116 3117 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 3118 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 3119 interrupt-names = "hfi", "gmu"; 3120 3121 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 3122 <&gpucc GPU_CC_CXO_CLK>, 3123 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 3124 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 3125 clock-names = "gmu", "cxo", "axi", "memnoc"; 3126 3127 power-domains = <&gpucc GPU_CX_GDSC>, 3128 <&gpucc GPU_GX_GDSC>; 3129 power-domain-names = "cx", "gx"; 3130 3131 dma-ranges = <0 0x60000000 0 0x60000000 0 0x20000000>; 3132 3133 iommus = <&adreno_smmu 5>; 3134 3135 operating-points-v2 = <&gmu_opp_table>; 3136 3137 gmu_opp_table: opp-table { 3138 compatible = "operating-points-v2"; 3139 3140 opp-400000000 { 3141 opp-hz = /bits/ 64 <400000000>; 3142 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3143 }; 3144 3145 opp-200000000 { 3146 opp-hz = /bits/ 64 <200000000>; 3147 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3148 }; 3149 }; 3150 }; 3151 3152 dispcc: clock-controller@af00000 { 3153 compatible = "qcom,sdm845-dispcc"; 3154 reg = <0 0x0af00000 0 0x10000>; 3155 clocks = <&gcc GCC_DISP_GPLL0_CLK_SRC>; 3156 #clock-cells = <1>; 3157 #reset-cells = <1>; 3158 #power-domain-cells = <1>; 3159 }; 3160 3161 pdc_intc: interrupt-controller@b220000 { 3162 compatible = "qcom,sdm845-pdc", "qcom,pdc"; 3163 reg = <0 0x0b220000 0 0x30000>; 3164 qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>; 3165 #interrupt-cells = <2>; 3166 interrupt-parent = <&intc>; 3167 interrupt-controller; 3168 }; 3169 3170 pdc_reset: reset-controller@b2e0000 { 3171 compatible = "qcom,sdm845-pdc-global"; 3172 reg = <0 0x0b2e0000 0 0x20000>; 3173 #reset-cells = <1>; 3174 }; 3175 3176 tsens0: thermal-sensor@c263000 { 3177 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 3178 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3179 <0 0x0c222000 0 0x1ff>; /* SROT */ 3180 #qcom,sensors = <13>; 3181 #thermal-sensor-cells = <1>; 3182 }; 3183 3184 tsens1: thermal-sensor@c265000 { 3185 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 3186 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3187 <0 0x0c223000 0 0x1ff>; /* SROT */ 3188 #qcom,sensors = <8>; 3189 #thermal-sensor-cells = <1>; 3190 }; 3191 3192 aoss_reset: reset-controller@c2a0000 { 3193 compatible = "qcom,sdm845-aoss-cc"; 3194 reg = <0 0x0c2a0000 0 0x31000>; 3195 #reset-cells = <1>; 3196 }; 3197 3198 aoss_qmp: qmp@c300000 { 3199 compatible = "qcom,sdm845-aoss-qmp"; 3200 reg = <0 0x0c300000 0 0x100000>; 3201 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 3202 mboxes = <&apss_shared 0>; 3203 3204 #clock-cells = <0>; 3205 #power-domain-cells = <1>; 3206 3207 cx_cdev: cx { 3208 #cooling-cells = <2>; 3209 }; 3210 3211 ebi_cdev: ebi { 3212 #cooling-cells = <2>; 3213 }; 3214 }; 3215 3216 spmi_bus: spmi@c440000 { 3217 compatible = "qcom,spmi-pmic-arb"; 3218 reg = <0 0x0c440000 0 0x1100>, 3219 <0 0x0c600000 0 0x2000000>, 3220 <0 0x0e600000 0 0x100000>, 3221 <0 0x0e700000 0 0xa0000>, 3222 <0 0x0c40a000 0 0x26000>; 3223 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3224 interrupt-names = "periph_irq"; 3225 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 3226 qcom,ee = <0>; 3227 qcom,channel = <0>; 3228 #address-cells = <2>; 3229 #size-cells = <0>; 3230 interrupt-controller; 3231 #interrupt-cells = <4>; 3232 cell-index = <0>; 3233 }; 3234 3235 apps_smmu: iommu@15000000 { 3236 compatible = "qcom,sdm845-smmu-500", "arm,mmu-500"; 3237 reg = <0 0x15000000 0 0x80000>; 3238 #iommu-cells = <2>; 3239 qcom,smmu-500-fw-impl-safe-errata; 3240 #global-interrupts = <1>; 3241 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3242 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 3243 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3244 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3245 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3246 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3247 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3248 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3249 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3250 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3251 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3252 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3253 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3254 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3255 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3256 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3257 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3258 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3259 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3260 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3261 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3262 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3263 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3264 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3265 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3266 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3267 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3268 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3269 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3270 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3271 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3272 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3273 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3274 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3275 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3276 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3277 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3278 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3279 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3280 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3281 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3282 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3283 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3284 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3285 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3286 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3287 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3288 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3289 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3290 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3291 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3292 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3293 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3294 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3295 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3296 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3297 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3298 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3299 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3300 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3301 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3302 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3303 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3304 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3305 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; 3306 }; 3307 3308 lpasscc: clock-controller@17014000 { 3309 compatible = "qcom,sdm845-lpasscc"; 3310 reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>; 3311 reg-names = "cc", "qdsp6ss"; 3312 #clock-cells = <1>; 3313 status = "disabled"; 3314 }; 3315 3316 watchdog@17980000 { 3317 compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt"; 3318 reg = <0 0x17980000 0 0x1000>; 3319 clocks = <&sleep_clk>; 3320 }; 3321 3322 apss_shared: mailbox@17990000 { 3323 compatible = "qcom,sdm845-apss-shared"; 3324 reg = <0 0x17990000 0 0x1000>; 3325 #mbox-cells = <1>; 3326 }; 3327 3328 apps_rsc: rsc@179c0000 { 3329 label = "apps_rsc"; 3330 compatible = "qcom,rpmh-rsc"; 3331 reg = <0 0x179c0000 0 0x10000>, 3332 <0 0x179d0000 0 0x10000>, 3333 <0 0x179e0000 0 0x10000>; 3334 reg-names = "drv-0", "drv-1", "drv-2"; 3335 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3336 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3337 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3338 qcom,tcs-offset = <0xd00>; 3339 qcom,drv-id = <2>; 3340 qcom,tcs-config = <ACTIVE_TCS 2>, 3341 <SLEEP_TCS 3>, 3342 <WAKE_TCS 3>, 3343 <CONTROL_TCS 1>; 3344 3345 rpmhcc: clock-controller { 3346 compatible = "qcom,sdm845-rpmh-clk"; 3347 #clock-cells = <1>; 3348 clock-names = "xo"; 3349 clocks = <&xo_board>; 3350 }; 3351 3352 rpmhpd: power-controller { 3353 compatible = "qcom,sdm845-rpmhpd"; 3354 #power-domain-cells = <1>; 3355 operating-points-v2 = <&rpmhpd_opp_table>; 3356 3357 rpmhpd_opp_table: opp-table { 3358 compatible = "operating-points-v2"; 3359 3360 rpmhpd_opp_ret: opp1 { 3361 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3362 }; 3363 3364 rpmhpd_opp_min_svs: opp2 { 3365 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3366 }; 3367 3368 rpmhpd_opp_low_svs: opp3 { 3369 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3370 }; 3371 3372 rpmhpd_opp_svs: opp4 { 3373 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3374 }; 3375 3376 rpmhpd_opp_svs_l1: opp5 { 3377 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3378 }; 3379 3380 rpmhpd_opp_nom: opp6 { 3381 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3382 }; 3383 3384 rpmhpd_opp_nom_l1: opp7 { 3385 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3386 }; 3387 3388 rpmhpd_opp_nom_l2: opp8 { 3389 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3390 }; 3391 3392 rpmhpd_opp_turbo: opp9 { 3393 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3394 }; 3395 3396 rpmhpd_opp_turbo_l1: opp10 { 3397 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3398 }; 3399 }; 3400 }; 3401 3402 rsc_hlos: interconnect { 3403 compatible = "qcom,sdm845-rsc-hlos"; 3404 #interconnect-cells = <1>; 3405 }; 3406 }; 3407 3408 intc: interrupt-controller@17a00000 { 3409 compatible = "arm,gic-v3"; 3410 #address-cells = <2>; 3411 #size-cells = <2>; 3412 ranges; 3413 #interrupt-cells = <3>; 3414 interrupt-controller; 3415 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 3416 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 3417 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3418 3419 gic-its@17a40000 { 3420 compatible = "arm,gic-v3-its"; 3421 msi-controller; 3422 #msi-cells = <1>; 3423 reg = <0 0x17a40000 0 0x20000>; 3424 status = "disabled"; 3425 }; 3426 }; 3427 3428 timer@17c90000 { 3429 #address-cells = <2>; 3430 #size-cells = <2>; 3431 ranges; 3432 compatible = "arm,armv7-timer-mem"; 3433 reg = <0 0x17c90000 0 0x1000>; 3434 3435 frame@17ca0000 { 3436 frame-number = <0>; 3437 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 3438 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3439 reg = <0 0x17ca0000 0 0x1000>, 3440 <0 0x17cb0000 0 0x1000>; 3441 }; 3442 3443 frame@17cc0000 { 3444 frame-number = <1>; 3445 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 3446 reg = <0 0x17cc0000 0 0x1000>; 3447 status = "disabled"; 3448 }; 3449 3450 frame@17cd0000 { 3451 frame-number = <2>; 3452 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3453 reg = <0 0x17cd0000 0 0x1000>; 3454 status = "disabled"; 3455 }; 3456 3457 frame@17ce0000 { 3458 frame-number = <3>; 3459 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3460 reg = <0 0x17ce0000 0 0x1000>; 3461 status = "disabled"; 3462 }; 3463 3464 frame@17cf0000 { 3465 frame-number = <4>; 3466 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3467 reg = <0 0x17cf0000 0 0x1000>; 3468 status = "disabled"; 3469 }; 3470 3471 frame@17d00000 { 3472 frame-number = <5>; 3473 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3474 reg = <0 0x17d00000 0 0x1000>; 3475 status = "disabled"; 3476 }; 3477 3478 frame@17d10000 { 3479 frame-number = <6>; 3480 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3481 reg = <0 0x17d10000 0 0x1000>; 3482 status = "disabled"; 3483 }; 3484 }; 3485 3486 cpufreq_hw: cpufreq@17d43000 { 3487 compatible = "qcom,cpufreq-hw"; 3488 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>; 3489 reg-names = "freq-domain0", "freq-domain1"; 3490 3491 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3492 clock-names = "xo", "alternate"; 3493 3494 #freq-domain-cells = <1>; 3495 }; 3496 3497 wifi: wifi@18800000 { 3498 compatible = "qcom,wcn3990-wifi"; 3499 status = "disabled"; 3500 reg = <0 0x18800000 0 0x800000>; 3501 reg-names = "membase"; 3502 memory-region = <&wlan_msa_mem>; 3503 clock-names = "cxo_ref_clk_pin"; 3504 clocks = <&rpmhcc RPMH_RF_CLK2>; 3505 interrupts = 3506 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 3507 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 3508 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 3509 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 3510 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3511 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3512 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 3513 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3514 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 3515 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3516 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3517 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 3518 iommus = <&apps_smmu 0x0040 0x1>; 3519 }; 3520 }; 3521 3522 thermal-zones { 3523 cpu0-thermal { 3524 polling-delay-passive = <250>; 3525 polling-delay = <1000>; 3526 3527 thermal-sensors = <&tsens0 1>; 3528 3529 trips { 3530 cpu0_alert0: trip-point0 { 3531 temperature = <90000>; 3532 hysteresis = <2000>; 3533 type = "passive"; 3534 }; 3535 3536 cpu0_alert1: trip-point1 { 3537 temperature = <95000>; 3538 hysteresis = <2000>; 3539 type = "passive"; 3540 }; 3541 3542 cpu0_crit: cpu_crit { 3543 temperature = <110000>; 3544 hysteresis = <1000>; 3545 type = "critical"; 3546 }; 3547 }; 3548 3549 cooling-maps { 3550 map0 { 3551 trip = <&cpu0_alert0>; 3552 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3553 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3554 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3555 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3556 }; 3557 map1 { 3558 trip = <&cpu0_alert1>; 3559 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3560 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3561 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3562 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3563 }; 3564 }; 3565 }; 3566 3567 cpu1-thermal { 3568 polling-delay-passive = <250>; 3569 polling-delay = <1000>; 3570 3571 thermal-sensors = <&tsens0 2>; 3572 3573 trips { 3574 cpu1_alert0: trip-point0 { 3575 temperature = <90000>; 3576 hysteresis = <2000>; 3577 type = "passive"; 3578 }; 3579 3580 cpu1_alert1: trip-point1 { 3581 temperature = <95000>; 3582 hysteresis = <2000>; 3583 type = "passive"; 3584 }; 3585 3586 cpu1_crit: cpu_crit { 3587 temperature = <110000>; 3588 hysteresis = <1000>; 3589 type = "critical"; 3590 }; 3591 }; 3592 3593 cooling-maps { 3594 map0 { 3595 trip = <&cpu1_alert0>; 3596 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3597 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3598 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3599 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3600 }; 3601 map1 { 3602 trip = <&cpu1_alert1>; 3603 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3604 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3605 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3606 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3607 }; 3608 }; 3609 }; 3610 3611 cpu2-thermal { 3612 polling-delay-passive = <250>; 3613 polling-delay = <1000>; 3614 3615 thermal-sensors = <&tsens0 3>; 3616 3617 trips { 3618 cpu2_alert0: trip-point0 { 3619 temperature = <90000>; 3620 hysteresis = <2000>; 3621 type = "passive"; 3622 }; 3623 3624 cpu2_alert1: trip-point1 { 3625 temperature = <95000>; 3626 hysteresis = <2000>; 3627 type = "passive"; 3628 }; 3629 3630 cpu2_crit: cpu_crit { 3631 temperature = <110000>; 3632 hysteresis = <1000>; 3633 type = "critical"; 3634 }; 3635 }; 3636 3637 cooling-maps { 3638 map0 { 3639 trip = <&cpu2_alert0>; 3640 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3641 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3642 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3643 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3644 }; 3645 map1 { 3646 trip = <&cpu2_alert1>; 3647 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3648 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3649 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3650 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3651 }; 3652 }; 3653 }; 3654 3655 cpu3-thermal { 3656 polling-delay-passive = <250>; 3657 polling-delay = <1000>; 3658 3659 thermal-sensors = <&tsens0 4>; 3660 3661 trips { 3662 cpu3_alert0: trip-point0 { 3663 temperature = <90000>; 3664 hysteresis = <2000>; 3665 type = "passive"; 3666 }; 3667 3668 cpu3_alert1: trip-point1 { 3669 temperature = <95000>; 3670 hysteresis = <2000>; 3671 type = "passive"; 3672 }; 3673 3674 cpu3_crit: cpu_crit { 3675 temperature = <110000>; 3676 hysteresis = <1000>; 3677 type = "critical"; 3678 }; 3679 }; 3680 3681 cooling-maps { 3682 map0 { 3683 trip = <&cpu3_alert0>; 3684 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3685 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3686 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3687 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3688 }; 3689 map1 { 3690 trip = <&cpu3_alert1>; 3691 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3692 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3693 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3694 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3695 }; 3696 }; 3697 }; 3698 3699 cpu4-thermal { 3700 polling-delay-passive = <250>; 3701 polling-delay = <1000>; 3702 3703 thermal-sensors = <&tsens0 7>; 3704 3705 trips { 3706 cpu4_alert0: trip-point0 { 3707 temperature = <90000>; 3708 hysteresis = <2000>; 3709 type = "passive"; 3710 }; 3711 3712 cpu4_alert1: trip-point1 { 3713 temperature = <95000>; 3714 hysteresis = <2000>; 3715 type = "passive"; 3716 }; 3717 3718 cpu4_crit: cpu_crit { 3719 temperature = <110000>; 3720 hysteresis = <1000>; 3721 type = "critical"; 3722 }; 3723 }; 3724 3725 cooling-maps { 3726 map0 { 3727 trip = <&cpu4_alert0>; 3728 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3729 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3730 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3731 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3732 }; 3733 map1 { 3734 trip = <&cpu4_alert1>; 3735 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3736 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3737 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3738 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3739 }; 3740 }; 3741 }; 3742 3743 cpu5-thermal { 3744 polling-delay-passive = <250>; 3745 polling-delay = <1000>; 3746 3747 thermal-sensors = <&tsens0 8>; 3748 3749 trips { 3750 cpu5_alert0: trip-point0 { 3751 temperature = <90000>; 3752 hysteresis = <2000>; 3753 type = "passive"; 3754 }; 3755 3756 cpu5_alert1: trip-point1 { 3757 temperature = <95000>; 3758 hysteresis = <2000>; 3759 type = "passive"; 3760 }; 3761 3762 cpu5_crit: cpu_crit { 3763 temperature = <110000>; 3764 hysteresis = <1000>; 3765 type = "critical"; 3766 }; 3767 }; 3768 3769 cooling-maps { 3770 map0 { 3771 trip = <&cpu5_alert0>; 3772 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3773 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3774 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3775 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3776 }; 3777 map1 { 3778 trip = <&cpu5_alert1>; 3779 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3780 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3781 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3782 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3783 }; 3784 }; 3785 }; 3786 3787 cpu6-thermal { 3788 polling-delay-passive = <250>; 3789 polling-delay = <1000>; 3790 3791 thermal-sensors = <&tsens0 9>; 3792 3793 trips { 3794 cpu6_alert0: trip-point0 { 3795 temperature = <90000>; 3796 hysteresis = <2000>; 3797 type = "passive"; 3798 }; 3799 3800 cpu6_alert1: trip-point1 { 3801 temperature = <95000>; 3802 hysteresis = <2000>; 3803 type = "passive"; 3804 }; 3805 3806 cpu6_crit: cpu_crit { 3807 temperature = <110000>; 3808 hysteresis = <1000>; 3809 type = "critical"; 3810 }; 3811 }; 3812 3813 cooling-maps { 3814 map0 { 3815 trip = <&cpu6_alert0>; 3816 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3817 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3818 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3819 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3820 }; 3821 map1 { 3822 trip = <&cpu6_alert1>; 3823 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3824 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3825 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3826 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3827 }; 3828 }; 3829 }; 3830 3831 cpu7-thermal { 3832 polling-delay-passive = <250>; 3833 polling-delay = <1000>; 3834 3835 thermal-sensors = <&tsens0 10>; 3836 3837 trips { 3838 cpu7_alert0: trip-point0 { 3839 temperature = <90000>; 3840 hysteresis = <2000>; 3841 type = "passive"; 3842 }; 3843 3844 cpu7_alert1: trip-point1 { 3845 temperature = <95000>; 3846 hysteresis = <2000>; 3847 type = "passive"; 3848 }; 3849 3850 cpu7_crit: cpu_crit { 3851 temperature = <110000>; 3852 hysteresis = <1000>; 3853 type = "critical"; 3854 }; 3855 }; 3856 3857 cooling-maps { 3858 map0 { 3859 trip = <&cpu7_alert0>; 3860 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3861 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3862 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3863 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3864 }; 3865 map1 { 3866 trip = <&cpu7_alert1>; 3867 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3868 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3869 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3870 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3871 }; 3872 }; 3873 }; 3874 3875 aoss0-thermal { 3876 polling-delay-passive = <250>; 3877 polling-delay = <1000>; 3878 3879 thermal-sensors = <&tsens0 0>; 3880 3881 trips { 3882 aoss0_alert0: trip-point0 { 3883 temperature = <90000>; 3884 hysteresis = <2000>; 3885 type = "hot"; 3886 }; 3887 }; 3888 }; 3889 3890 cluster0-thermal { 3891 polling-delay-passive = <250>; 3892 polling-delay = <1000>; 3893 3894 thermal-sensors = <&tsens0 5>; 3895 3896 trips { 3897 cluster0_alert0: trip-point0 { 3898 temperature = <90000>; 3899 hysteresis = <2000>; 3900 type = "hot"; 3901 }; 3902 cluster0_crit: cluster0_crit { 3903 temperature = <110000>; 3904 hysteresis = <2000>; 3905 type = "critical"; 3906 }; 3907 }; 3908 }; 3909 3910 cluster1-thermal { 3911 polling-delay-passive = <250>; 3912 polling-delay = <1000>; 3913 3914 thermal-sensors = <&tsens0 6>; 3915 3916 trips { 3917 cluster1_alert0: trip-point0 { 3918 temperature = <90000>; 3919 hysteresis = <2000>; 3920 type = "hot"; 3921 }; 3922 cluster1_crit: cluster1_crit { 3923 temperature = <110000>; 3924 hysteresis = <2000>; 3925 type = "critical"; 3926 }; 3927 }; 3928 }; 3929 3930 gpu-thermal-top { 3931 polling-delay-passive = <250>; 3932 polling-delay = <1000>; 3933 3934 thermal-sensors = <&tsens0 11>; 3935 3936 trips { 3937 gpu1_alert0: trip-point0 { 3938 temperature = <90000>; 3939 hysteresis = <2000>; 3940 type = "hot"; 3941 }; 3942 }; 3943 }; 3944 3945 gpu-thermal-bottom { 3946 polling-delay-passive = <250>; 3947 polling-delay = <1000>; 3948 3949 thermal-sensors = <&tsens0 12>; 3950 3951 trips { 3952 gpu2_alert0: trip-point0 { 3953 temperature = <90000>; 3954 hysteresis = <2000>; 3955 type = "hot"; 3956 }; 3957 }; 3958 }; 3959 3960 aoss1-thermal { 3961 polling-delay-passive = <250>; 3962 polling-delay = <1000>; 3963 3964 thermal-sensors = <&tsens1 0>; 3965 3966 trips { 3967 aoss1_alert0: trip-point0 { 3968 temperature = <90000>; 3969 hysteresis = <2000>; 3970 type = "hot"; 3971 }; 3972 }; 3973 }; 3974 3975 q6-modem-thermal { 3976 polling-delay-passive = <250>; 3977 polling-delay = <1000>; 3978 3979 thermal-sensors = <&tsens1 1>; 3980 3981 trips { 3982 q6_modem_alert0: trip-point0 { 3983 temperature = <90000>; 3984 hysteresis = <2000>; 3985 type = "hot"; 3986 }; 3987 }; 3988 }; 3989 3990 mem-thermal { 3991 polling-delay-passive = <250>; 3992 polling-delay = <1000>; 3993 3994 thermal-sensors = <&tsens1 2>; 3995 3996 trips { 3997 mem_alert0: trip-point0 { 3998 temperature = <90000>; 3999 hysteresis = <2000>; 4000 type = "hot"; 4001 }; 4002 }; 4003 }; 4004 4005 wlan-thermal { 4006 polling-delay-passive = <250>; 4007 polling-delay = <1000>; 4008 4009 thermal-sensors = <&tsens1 3>; 4010 4011 trips { 4012 wlan_alert0: trip-point0 { 4013 temperature = <90000>; 4014 hysteresis = <2000>; 4015 type = "hot"; 4016 }; 4017 }; 4018 }; 4019 4020 q6-hvx-thermal { 4021 polling-delay-passive = <250>; 4022 polling-delay = <1000>; 4023 4024 thermal-sensors = <&tsens1 4>; 4025 4026 trips { 4027 q6_hvx_alert0: trip-point0 { 4028 temperature = <90000>; 4029 hysteresis = <2000>; 4030 type = "hot"; 4031 }; 4032 }; 4033 }; 4034 4035 camera-thermal { 4036 polling-delay-passive = <250>; 4037 polling-delay = <1000>; 4038 4039 thermal-sensors = <&tsens1 5>; 4040 4041 trips { 4042 camera_alert0: trip-point0 { 4043 temperature = <90000>; 4044 hysteresis = <2000>; 4045 type = "hot"; 4046 }; 4047 }; 4048 }; 4049 4050 video-thermal { 4051 polling-delay-passive = <250>; 4052 polling-delay = <1000>; 4053 4054 thermal-sensors = <&tsens1 6>; 4055 4056 trips { 4057 video_alert0: trip-point0 { 4058 temperature = <90000>; 4059 hysteresis = <2000>; 4060 type = "hot"; 4061 }; 4062 }; 4063 }; 4064 4065 modem-thermal { 4066 polling-delay-passive = <250>; 4067 polling-delay = <1000>; 4068 4069 thermal-sensors = <&tsens1 7>; 4070 4071 trips { 4072 modem_alert0: trip-point0 { 4073 temperature = <90000>; 4074 hysteresis = <2000>; 4075 type = "hot"; 4076 }; 4077 }; 4078 }; 4079 }; 4080}; 4081