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Searched refs:val (Results 1 – 25 of 60) sorted by relevance

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/Documentation/usb/
Dgadget_hid.rst144 unsigned char val;
148 {.opt = "--left-ctrl", .val = 0x01},
149 {.opt = "--right-ctrl", .val = 0x10},
150 {.opt = "--left-shift", .val = 0x02},
151 {.opt = "--right-shift", .val = 0x20},
152 {.opt = "--left-alt", .val = 0x04},
153 {.opt = "--right-alt", .val = 0x40},
154 {.opt = "--left-meta", .val = 0x08},
155 {.opt = "--right-meta", .val = 0x80},
160 {.opt = "--return", .val = 0x28},
[all …]
/Documentation/devicetree/bindings/leds/
Dleds-netxbig.txt16 - mode-val: Mode to value mapping. Each entry is represented by two integers:
38 mode-val = <NETXBIG_LED_OFF 0
48 mode-val = <NETXBIG_LED_OFF 0
57 mode-val = <NETXBIG_LED_OFF 0
67 mode-val = <NETXBIG_LED_OFF 0
76 mode-val = <NETXBIG_LED_OFF 0
86 mode-val = <NETXBIG_LED_OFF 0
Dleds-aat1290.txt69 samsung,pin-val = <0>;
75 samsung,pin-val = <1>;
/Documentation/devicetree/bindings/leds/backlight/
Dlp855x.txt14 - rom-val: Register value to be updated (u8)
31 rom-val = /bits/ 8 <0xcf>;
37 rom-val = /bits/ 8 <0xc7>;
43 rom-val = /bits/ 8 <0x0f>;
70 rom-val = /bits/ 8 <0xcf>;
/Documentation/ioctl/
Dhdio.rst147 long val;
149 ioctl(fd, HDIO_GET_UNMASKINTR, &val);
169 unsigned long val;
171 ioctl(fd, HDIO_SET_UNMASKINTR, val);
198 long val;
200 ioctl(fd, HDIO_GET_MULTCOUNT, &val);
220 int val;
222 ioctl(fd, HDIO_SET_MULTCOUNT, val);
317 long val;
319 ioctl(fd, HDIO_GET_KEEPSETTINGS, &val);
[all …]
/Documentation/translations/zh_CN/
Dio_ordering.txt36 CPU A: val = readl(my_status);
42 CPU B: val = readl(my_status);
53 CPU A: val = readl(my_status);
60 CPU B: val = readl(my_status);
/Documentation/
Dconf.py81 key, val = [x.strip() for x in line.split('=', 2)] variable
83 makefile_version = val
85 makefile_patchlevel = val
Dio_ordering.txt19 CPU A: val = readl(my_status);
25 CPU B: val = readl(my_status);
36 CPU A: val = readl(my_status);
43 CPU B: val = readl(my_status);
Dthis_cpu_ops.txt49 this_cpu_write(pcp, val)
50 this_cpu_add(pcp, val)
51 this_cpu_and(pcp, val)
52 this_cpu_or(pcp, val)
53 this_cpu_add_return(pcp, val)
57 this_cpu_sub(pcp, val)
60 this_cpu_sub_return(pcp, val)
238 __this_cpu_write(pcp, val)
239 __this_cpu_add(pcp, val)
240 __this_cpu_and(pcp, val)
[all …]
/Documentation/i2c/
Dslave-interface.rst60 ret = i2c_slave_event(client, event, &val)
63 types described hereafter. 'val' holds an u8 value for the data byte to be
64 read/written and is thus bidirectional. The pointer to val must always be
65 provided even if val is not used for an event, i.e. don't use NULL here. 'ret'
73 'val': unused
84 'val': backend returns first byte to be sent
94 'val': bus driver delivers received byte
98 Another I2C master has sent a byte to us which needs to be set in 'val'. If 'ret'
104 'val': backend returns next byte to be sent
109 'val'. Important: This does not mean that the previous byte has been acked, it
[all …]
/Documentation/translations/zh_CN/arm/
Dkernel_user_helpers.txt166 int atomic_add(volatile int *ptr, int val)
172 new = old + val;
264 int64_t atomic_add64(volatile int64_t *ptr, int64_t val)
270 new = old + val;
/Documentation/devicetree/bindings/watchdog/
Dof-xilinx-wdt.txt15 - xlnx,wdt-interval : Watchdog timeout interval in 2^<val> clock cycles,
16 <val> is integer from 8 to 31.
/Documentation/trace/
Devents-msr.rst18 - val: Value written
27 - val: Value written
/Documentation/devicetree/bindings/regulator/
Danatop-regulator.txt9 - anatop-min-bit-val: Minimum value of this register
37 anatop-min-bit-val = <1>;
/Documentation/media/kapi/
Dv4l2-controls.rst261 write_reg(0x123, ctrl->val);
264 write_reg(0x456, ctrl->val);
320 s32 val;
322 s32 val;
333 &ctrl->val == ctrl->p_new.p_s32
334 &ctrl->cur.val == ctrl->p_cur.p_s32
336 For all other types use ctrl->p_cur.p<something>. Basically the val
337 and cur.val fields can be considered an alias since these are used so often.
339 Within the control ops you can freely use these. The val and cur.val speak for
361 ctrl->val = read_reg(0x123);
[all …]
/Documentation/media/uapi/v4l/
Dvidioc-dbg-g-register.rst64 ``val`` field the value to be written into the register.
69 the driver stores the register value in the ``val`` field and the size
139 - ``val``
/Documentation/arm/
Dkernel_user_helpers.rst153 int atomic_add(volatile int *ptr, int val)
159 new = old + val;
249 int64_t atomic_add64(volatile int64_t *ptr, int64_t val)
255 new = old + val;
/Documentation/arm64/
Delf_hwcaps.rst51 Functionality implied by idreg.field == val.
54 defines as being present when idreg.field has value val, but do not
55 indicate that idreg.field is precisely equal to val, nor do they
/Documentation/input/devices/
Diforce-protocol.rst313 OP= 40 <idx> <val> [<val>]
328 OP= 42 <val>
340 OP= 43 <val>
/Documentation/devicetree/bindings/dma/
Dfsl-imx-sdma.txt67 <reg shift val>.
70 val is the value of the bit (0 or 1).
/Documentation/driver-api/
Dconnector.rst35 __u32 val;
38 idx and val are unique identifiers which must be registered in the
40 callback function which will be called when a message with above idx.val
/Documentation/driver-api/iio/
Dhw-consumer.rst31 struct iio_chan_spec const *chan, int *val,
/Documentation/driver-api/dmaengine/
Ddmatest.rst119 …"dmatest: result <channel>: <test id>: '<error msg>' with src_off=<val> dst_off=<val> len=<val> (<…
/Documentation/devicetree/bindings/input/touchscreen/
Dad7879.txt35 1-255: 515us + val * 35us (up to 9.440ms)
/Documentation/hwmon/
Dhwmon-kernel-api.rst291 u32 attr, int channel, long *val)
305 val:
314 u32 attr, int channel, long val)
328 val:

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