Searched refs:BIT (Results 1 – 25 of 281) sorted by relevance
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171 #define QCA956X_MAC_CFG1_SOFT_RST BIT(31)172 #define QCA956X_MAC_CFG1_RX_RST BIT(19)173 #define QCA956X_MAC_CFG1_TX_RST BIT(18)174 #define QCA956X_MAC_CFG1_LOOPBACK BIT(8)175 #define QCA956X_MAC_CFG1_RX_EN BIT(2)176 #define QCA956X_MAC_CFG1_TX_EN BIT(0)179 #define QCA956X_MAC_CFG2_IF_1000 BIT(9)180 #define QCA956X_MAC_CFG2_IF_10_100 BIT(8)181 #define QCA956X_MAC_CFG2_HUGE_FRAME_EN BIT(5)182 #define QCA956X_MAC_CFG2_LEN_CHECK BIT(4)[all …]
21 #define AR933X_UART_DATA_RX_CSR BIT(8)22 #define AR933X_UART_DATA_TX_CSR BIT(9)36 #define AR933X_UART_CS_DMA_EN BIT(6)37 #define AR933X_UART_CS_TX_READY_ORIDE BIT(7)38 #define AR933X_UART_CS_RX_READY_ORIDE BIT(8)39 #define AR933X_UART_CS_TX_READY BIT(9)40 #define AR933X_UART_CS_RX_BREAK BIT(10)41 #define AR933X_UART_CS_TX_BREAK BIT(11)42 #define AR933X_UART_CS_HOST_INT BIT(12)43 #define AR933X_UART_CS_HOST_INT_EN BIT(13)[all …]
19 #define UART0_USE_PWM23 BIT(28)20 #define UART0_USE_PWM01 BIT(27)21 #define UART1_USE_LCD0_5_6_11 BIT(26)22 #define I2C2_USE_CAN1 BIT(25)23 #define I2C1_USE_CAN0 BIT(24)24 #define NAND3_USE_UART5 BIT(23)25 #define NAND3_USE_UART4 BIT(22)26 #define NAND3_USE_UART1_DAT BIT(21)27 #define NAND3_USE_UART1_CTS BIT(20)28 #define NAND3_USE_PWM23 BIT(19)[all …]
19 #define DIV_DC_EN BIT(31)20 #define DIV_DC_RST BIT(30)21 #define DIV_CPU_EN BIT(25)22 #define DIV_CPU_RST BIT(24)23 #define DIV_DDR_EN BIT(19)24 #define DIV_DDR_RST BIT(18)25 #define RST_DC_EN BIT(5)26 #define RST_DC BIT(4)27 #define RST_DDR_EN BIT(3)28 #define RST_DDR BIT(2)[all …]
18 #define CNT_RST BIT(7)19 #define INT_SR BIT(6)20 #define INT_EN BIT(5)21 #define PWM_SINGLE BIT(4)22 #define PWM_OE BIT(3)23 #define CNT_EN BIT(0)
26 #define MACEPCI_ERROR_MASTER_ABORT BIT(31)27 #define MACEPCI_ERROR_TARGET_ABORT BIT(30)28 #define MACEPCI_ERROR_DATA_PARITY_ERR BIT(29)29 #define MACEPCI_ERROR_RETRY_ERR BIT(28)30 #define MACEPCI_ERROR_ILLEGAL_CMD BIT(27)31 #define MACEPCI_ERROR_SYSTEM_ERR BIT(26)32 #define MACEPCI_ERROR_INTERRUPT_TEST BIT(25)33 #define MACEPCI_ERROR_PARITY_ERR BIT(24)34 #define MACEPCI_ERROR_OVERRUN BIT(23)35 #define MACEPCI_ERROR_RSVD BIT(22)[all …]
50 #define MACE_VID_IN1_INT BIT(0)51 #define MACE_VID_IN2_INT BIT(1)52 #define MACE_VID_OUT_INT BIT(2)53 #define MACE_ETHERNET_INT BIT(3)54 #define MACE_SUPERIO_INT BIT(4)55 #define MACE_MISC_INT BIT(5)56 #define MACE_AUDIO_INT BIT(6)57 #define MACE_PCI_BRIDGE_INT BIT(7)58 #define MACEPCI_SCSI0_INT BIT(8)59 #define MACEPCI_SCSI1_INT BIT(9)[all …]
93 #define RT3883_SYSCFG0_DRAM_TYPE_DDR2 BIT(17)101 #define RT3883_SYSCFG1_USB0_HOST_MODE BIT(10)102 #define RT3883_SYSCFG1_PCIE_RC_MODE BIT(8)103 #define RT3883_SYSCFG1_PCI_HOST_MODE BIT(7)104 #define RT3883_SYSCFG1_PCI_66M_MODE BIT(6)105 #define RT3883_SYSCFG1_GPIO2_AS_WDT_OUT BIT(2)107 #define RT3883_CLKCFG1_PCIE_CLK_EN BIT(21)108 #define RT3883_CLKCFG1_UPHY1_CLK_EN BIT(20)109 #define RT3883_CLKCFG1_PCI_CLK_EN BIT(19)110 #define RT3883_CLKCFG1_UPHY0_CLK_EN BIT(18)[all …]
36 #define RT2880_GPIO_MODE_I2C BIT(0)37 #define RT2880_GPIO_MODE_UART0 BIT(1)38 #define RT2880_GPIO_MODE_SPI BIT(2)39 #define RT2880_GPIO_MODE_UART1 BIT(3)40 #define RT2880_GPIO_MODE_JTAG BIT(4)41 #define RT2880_GPIO_MODE_MDIO BIT(5)42 #define RT2880_GPIO_MODE_SDRAM BIT(6)43 #define RT2880_GPIO_MODE_PCI BIT(7)45 #define CLKCFG_SRAM_CS_N_WDT BIT(9)
78 #define L2X0_EVENT_CNT_CTRL_ENABLE BIT(0)91 #define L2C_AUX_CTRL_EVTMON_ENABLE BIT(20)92 #define L2C_AUX_CTRL_PARITY_ENABLE BIT(21)93 #define L2C_AUX_CTRL_SHARED_OVERRIDE BIT(22)106 #define L210_AUX_CTRL_WRAP_DISABLE BIT(12)107 #define L210_AUX_CTRL_WA_OVERRIDE BIT(23)108 #define L210_AUX_CTRL_EXCLUSIVE_ABORT BIT(24)110 #define L220_AUX_CTRL_EXCLUSIVE_CACHE BIT(12)113 #define L220_AUX_CTRL_NS_LOCKDOWN BIT(26)114 #define L220_AUX_CTRL_NS_INT_CTRL BIT(27)[all …]
20 #define NMISR_MAN_NMI BIT(0)21 #define NMISR_AUX_NMI BIT(1)25 #define NMIMR_MAN_NMIM BIT(0) /* Manual NMI mask */26 #define NMIMR_AUX_NMIM BIT(1) /* Auxiliary NMI mask */42 #define PCIECR_PCIEMUX1 BIT(15)43 #define PCIECR_PCIEMUX0 BIT(14)44 #define PCIECR_PRST4 BIT(12) /* slot 4 card present */45 #define PCIECR_PRST3 BIT(11) /* slot 3 card present */46 #define PCIECR_PRST2 BIT(10) /* slot 2 card present */47 #define PCIECR_PRST1 BIT(9) /* slot 1 card present */[all …]
18 #define IMR_ESRAM_FLUSH BIT(31)19 #define IMR_CPU_SNOOP BIT(30) /* Applicable only to write */20 #define IMR_RMU BIT(29)21 #define IMR_VC1_SAI_ID3 BIT(15)22 #define IMR_VC1_SAI_ID2 BIT(14)23 #define IMR_VC1_SAI_ID1 BIT(13)24 #define IMR_VC1_SAI_ID0 BIT(12)25 #define IMR_VC0_SAI_ID3 BIT(11)26 #define IMR_VC0_SAI_ID2 BIT(10)27 #define IMR_VC0_SAI_ID1 BIT(9)[all …]
22 #define HV_HYP_PAGE_SIZE BIT(HV_HYP_PAGE_SHIFT)48 #define HV_X64_MSR_VP_RUNTIME_AVAILABLE BIT(0)50 #define HV_MSR_TIME_REF_COUNT_AVAILABLE BIT(1)55 #define HV_X64_MSR_SYNIC_AVAILABLE BIT(2)60 #define HV_MSR_SYNTIMER_AVAILABLE BIT(3)65 #define HV_X64_MSR_APIC_ACCESS_AVAILABLE BIT(4)67 #define HV_X64_MSR_HYPERCALL_AVAILABLE BIT(5)69 #define HV_X64_MSR_VP_INDEX_AVAILABLE BIT(6)71 #define HV_X64_MSR_RESET_AVAILABLE BIT(7)77 #define HV_X64_MSR_STAT_PAGES_AVAILABLE BIT(8)[all …]
47 #define SPEC_CTRL_IBRS BIT(0) /* Indirect Branch Restricted Speculation */49 #define SPEC_CTRL_STIBP BIT(SPEC_CTRL_STIBP_SHIFT) /* STIBP mask */51 #define SPEC_CTRL_SSBD BIT(SPEC_CTRL_SSBD_SHIFT) /* Speculative Store Bypass Disable */53 #define SPEC_CTRL_RRSBA_DIS_S BIT(SPEC_CTRL_RRSBA_DIS_S_SHIFT)60 #define PRED_CMD_IBPB BIT(0) /* Indirect Branch Prediction Barrier */73 #define MSR_IA32_UMWAIT_CONTROL_C02_DISABLE BIT(0)74 #define MSR_IA32_UMWAIT_CONTROL_RESERVED BIT(1)91 #define ARCH_CAP_RDCL_NO BIT(0) /* Not susceptible to Meltdown */92 #define ARCH_CAP_IBRS_ALL BIT(1) /* Enhanced IBRS support */93 #define ARCH_CAP_RSBA BIT(2) /* RET may use alternative branch predictors */[all …]
13 #define CR0_CLOCK_COMPARATOR_SIGN BIT(63 - 10)14 #define CR0_EMERGENCY_SIGNAL_SUBMASK BIT(63 - 49)15 #define CR0_EXTERNAL_CALL_SUBMASK BIT(63 - 50)16 #define CR0_CLOCK_COMPARATOR_SUBMASK BIT(63 - 52)17 #define CR0_CPU_TIMER_SUBMASK BIT(63 - 53)18 #define CR0_SERVICE_SIGNAL_SUBMASK BIT(63 - 54)19 #define CR0_UNUSED_56 BIT(63 - 56)20 #define CR0_INTERRUPT_KEY_SUBMASK BIT(63 - 57)21 #define CR0_MEASUREMENT_ALERT_SUBMASK BIT(63 - 58)23 #define CR2_GUARDED_STORAGE BIT(63 - 59)[all …]
85 #define _TIF_NOTIFY_RESUME BIT(TIF_NOTIFY_RESUME)86 #define _TIF_SIGPENDING BIT(TIF_SIGPENDING)87 #define _TIF_NEED_RESCHED BIT(TIF_NEED_RESCHED)88 #define _TIF_UPROBE BIT(TIF_UPROBE)89 #define _TIF_GUARDED_STORAGE BIT(TIF_GUARDED_STORAGE)90 #define _TIF_PATCH_PENDING BIT(TIF_PATCH_PENDING)91 #define _TIF_ISOLATE_BP BIT(TIF_ISOLATE_BP)92 #define _TIF_ISOLATE_BP_GUEST BIT(TIF_ISOLATE_BP_GUEST)94 #define _TIF_31BIT BIT(TIF_31BIT)95 #define _TIF_SINGLE_STEP BIT(TIF_SINGLE_STEP)[all …]
25 #define MACHINE_FLAG_VM BIT(0)26 #define MACHINE_FLAG_KVM BIT(1)27 #define MACHINE_FLAG_LPAR BIT(2)28 #define MACHINE_FLAG_DIAG9C BIT(3)29 #define MACHINE_FLAG_ESOP BIT(4)30 #define MACHINE_FLAG_IDTE BIT(5)31 #define MACHINE_FLAG_DIAG44 BIT(6)32 #define MACHINE_FLAG_EDAT1 BIT(7)33 #define MACHINE_FLAG_EDAT2 BIT(8)34 #define MACHINE_FLAG_TOPOLOGY BIT(10)[all …]
55 #define PLLPREDIV_EN BIT(15)59 #define PLLCTL_PLLEN BIT(0)60 #define PLLCTL_PLLPWRDN BIT(1)61 #define PLLCTL_PLLRST BIT(3)62 #define PLLCTL_PLLDIS BIT(4)63 #define PLLCTL_PLLENSRC BIT(5)64 #define PLLCTL_CLKMODE BIT(8)67 #define PLLCMD_GOSTAT BIT(0)70 #define PLLSTAT_GOSTAT BIT(0)73 #define PLLDIV_EN BIT(15)[all …]
89 #define SATA_RST_N BIT(0) /* Active low reset sata_core phy */90 #define SataCtlReserve0 BIT(1)91 #define M_CSYSREQ BIT(2) /* AXI master low power, not used */92 #define S_CSYSREQ BIT(3) /* AXI slave low power, not used */93 #define P0_CP_DET BIT(8) /* Reserved, bring in from pad */94 #define P0_MP_SW BIT(9) /* Mech Switch */95 #define P0_DISABLE BIT(10) /* disable p0 */96 #define P0_ACT_LED_EN BIT(11) /* Active LED enable */97 #define P0_IRST_HARD_SYNTH BIT(12) /* PHY hard synth reset */98 #define P0_IRST_HARD_TXRX BIT(13) /* PHY lane hard reset */[all …]
65 #define GRF_SIDDQ BIT(13)117 mode_set = BIT(PMU_GLOBAL_INT_DISABLE) | BIT(PMU_L2FLUSH_EN) | in rk3288_slp_mode_set()118 BIT(PMU_SREF0_ENTER_EN) | BIT(PMU_SREF1_ENTER_EN) | in rk3288_slp_mode_set()119 BIT(PMU_DDR0_GATING_EN) | BIT(PMU_DDR1_GATING_EN) | in rk3288_slp_mode_set()120 BIT(PMU_PWR_MODE_EN) | BIT(PMU_CHIP_PD_EN) | in rk3288_slp_mode_set()121 BIT(PMU_SCU_EN); in rk3288_slp_mode_set()123 mode_set1 = BIT(PMU_CLR_CORE) | BIT(PMU_CLR_CPUP); in rk3288_slp_mode_set()127 mode_set |= BIT(PMU_BUS_PD_EN) | BIT(PMU_PMU_USE_LF) | in rk3288_slp_mode_set()128 BIT(PMU_DDR1IO_RET_EN) | BIT(PMU_DDR0IO_RET_EN) | in rk3288_slp_mode_set()129 BIT(PMU_ALIVE_USE_LF) | BIT(PMU_PLL_PD_EN); in rk3288_slp_mode_set()[all …]
45 #define SGRF_PCLK_WDT_GATE BIT(6)46 #define SGRF_PCLK_WDT_GATE_WRITE BIT(22)47 #define SGRF_FAST_BOOT_EN BIT(8)48 #define SGRF_FAST_BOOT_EN_WRITE BIT(24)51 #define SGRF_DAPDEVICEEN BIT(0)52 #define SGRF_DAPDEVICEEN_WRITE BIT(16)55 #define PMU_ARMINT_WAKEUP_EN BIT(0)56 #define PMU_GPIOINT_WAKEUP_EN BIT(3)
505 .core_events = BIT(PERF_CSTATE_CORE_C3_RES) |506 BIT(PERF_CSTATE_CORE_C6_RES),508 .pkg_events = BIT(PERF_CSTATE_PKG_C3_RES) |509 BIT(PERF_CSTATE_PKG_C6_RES) |510 BIT(PERF_CSTATE_PKG_C7_RES),514 .core_events = BIT(PERF_CSTATE_CORE_C3_RES) |515 BIT(PERF_CSTATE_CORE_C6_RES) |516 BIT(PERF_CSTATE_CORE_C7_RES),518 .pkg_events = BIT(PERF_CSTATE_PKG_C2_RES) |519 BIT(PERF_CSTATE_PKG_C3_RES) |[all …]
88 #define PMU_USB0_P BIT(0)89 #define PMU_ASE_SDIO BIT(2) /* ASE special */90 #define PMU_PCI BIT(4)91 #define PMU_DMA BIT(5)92 #define PMU_USB0 BIT(6)93 #define PMU_ASC0 BIT(7)94 #define PMU_EPHY BIT(7) /* ase */95 #define PMU_USIF BIT(7) /* from vr9 until grx390 */96 #define PMU_SPI BIT(8)97 #define PMU_DFE BIT(9)[all …]
28 #define JZ_TIMER_IRQ_HALF(x) BIT((x) + 0x10)29 #define JZ_TIMER_IRQ_FULL(x) BIT(x)31 #define JZ_TIMER_CTRL_PWM_ABBRUPT_SHUTDOWN BIT(9)32 #define JZ_TIMER_CTRL_PWM_ACTIVE_LOW BIT(8)33 #define JZ_TIMER_CTRL_PWM_ENABLE BIT(7)45 #define JZ_TIMER_CTRL_SRC_EXT BIT(2)46 #define JZ_TIMER_CTRL_SRC_RTC BIT(1)47 #define JZ_TIMER_CTRL_SRC_PCLK BIT(0)57 writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_SET); in jz4740_timer_stop()62 writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR); in jz4740_timer_start()[all …]
14 #define PLLCTL_PLLEN BIT(0)15 #define PLLCTL_PLLPWRDN BIT(1)16 #define PLLCTL_PLLRST BIT(3)17 #define PLLCTL_PLLDIS BIT(4)18 #define PLLCTL_PLLENSRC BIT(5)19 #define PLLCTL_CLKMODE BIT(8)43 #define PLLDIV_EN BIT(15)