Searched refs:CLK_RESET_PLLC_BASE (Results 1 – 2 of 2) sorted by relevance
| /arch/arm/mach-tegra/ |
| D | sleep-tegra20.S | 34 #define CLK_RESET_PLLC_BASE 0x80 macro
352 pll_enable r1, r0, CLK_RESET_PLLC_BASE
450 ldr r0, [r5, #CLK_RESET_PLLC_BASE]
452 str r0, [r5, #CLK_RESET_PLLC_BASE]
|
| D | sleep-tegra30.S | 48 #define CLK_RESET_PLLC_BASE 0x80 macro
347 pll_enable r1, r0, CLK_RESET_PLLC_BASE, 0
360 pll_enable r1, r0, CLK_RESET_PLLC_BASE, CLK_RESET_PLLC_MISC
370 pll_locked r1, r0, CLK_RESET_PLLC_BASE
650 ldr r0, [r5, #CLK_RESET_PLLC_BASE]
652 str r0, [r5, #CLK_RESET_PLLC_BASE]
|