| /arch/arm/kvm/ |
| D | coproc.h | 12 unsigned long CRm; member
24 unsigned long CRm; member
54 p->CRn, p->CRm, p->Op1, p->Op2, in print_cp_instr()
108 if (i1->CRm != i2->CRm) in cmp_reg()
109 return i1->CRm - i2->CRm; in cmp_reg()
119 #define CRm(_x) .CRm = _x macro
120 #define CRm64(_x) .CRn = _x, .CRm = 0
|
| D | coproc.c | 381 { CRn( 0), CRm( 0), Op1( 0), Op2( 5), is32,
385 { CRn( 0), CRm( 0), Op1( 2), Op2( 0), is32,
389 { CRn( 1), CRm( 0), Op1( 0), Op2( 1), is32,
393 { CRn( 1), CRm( 0), Op1( 0), Op2( 2), is32,
398 { CRn(2), CRm( 0), Op1( 0), Op2( 0), is32,
400 { CRn(2), CRm( 0), Op1( 0), Op2( 1), is32,
402 { CRn( 2), CRm( 0), Op1( 0), Op2( 2), is32,
408 { CRn( 3), CRm( 0), Op1( 0), Op2( 0), is32,
412 { CRn( 5), CRm( 0), Op1( 0), Op2( 0), is32,
414 { CRn( 5), CRm( 0), Op1( 0), Op2( 1), is32,
[all …]
|
| D | trace.h | 13 unsigned long CRm, unsigned long Op2, bool is_write),
14 TP_ARGS(Op1, Rt1, CRn, CRm, Op2, is_write),
20 __field( unsigned int, CRm )
30 __entry->CRm = CRm;
37 __entry->CRm, __entry->Op2)
|
| D | coproc_a7.c | 27 { CRn( 1), CRm( 0), Op1( 0), Op2( 0), is32,
|
| D | coproc_a15.c | 24 { CRn( 1), CRm( 0), Op1( 0), Op2( 0), is32,
|
| /arch/arm64/kvm/ |
| D | sys_regs.h | 18 u8 CRm; member
34 u8 CRm; member
69 p->Op0, p->Op1, p->CRn, p->CRm, p->Op2, p->is_write ? "write" : "read"); in print_sys_reg_instr()
133 if (i1->CRm != i2->CRm) in cmp_sys_reg()
134 return i1->CRm - i2->CRm; in cmp_sys_reg()
146 #define CRm(_x) .CRm = _x macro
152 CRn(sys_reg_CRn(reg)), CRm(sys_reg_CRm(reg)), \
|
| D | sys_regs.c | 318 (u32)r->CRn, (u32)r->CRm, (u32)r->Op2); in trap_loregion()
435 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm]; in trap_bvr()
442 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg); in trap_bvr()
450 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm]; in set_bvr()
460 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm]; in get_bvr()
470 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = rd->val; in reset_bvr()
477 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm]; in trap_bcr()
484 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg); in trap_bcr()
492 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm]; in set_bcr()
503 __u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm]; in get_bcr()
[all …]
|
| D | trace.h | 167 __field(u8, CRm)
179 __entry->CRm = reg->CRm;
186 __entry->CRm, __entry->Op2,
|
| D | sys_regs_generic_v8.c | 49 { Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b001),
|
| /arch/arm/include/asm/vdso/ |
| D | cp15.h | 14 #define __ACCESS_CP15(CRn, Op1, CRm, Op2) \ argument
15 "mrc", "mcr", __stringify(p15, Op1, %0, CRn, CRm, Op2), u32
16 #define __ACCESS_CP15_64(Op1, CRm) \ argument
17 "mrrc", "mcrr", __stringify(p15, Op1, %Q0, %R0, CRm), u64
|
| /arch/arm64/include/asm/ |
| D | sysreg.h | 99 #define __SYS_BARRIER_INSN(CRm, op2, Rt) \ argument
100 __emit_inst(0xd5000000 | sys_insn(0, 3, 3, (CRm), (op2)) | ((Rt) & 0x1f))
|