1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __ASM_SH_RENESAS_SDK7780_H 3 #define __ASM_SH_RENESAS_SDK7780_H 4 5 /* 6 * linux/include/asm-sh/sdk7780.h 7 * 8 * Renesas Solutions SH7780 SDK Support 9 * Copyright (C) 2008 Nicholas Beck <nbeck@mpc-data.co.uk> 10 */ 11 #include <linux/sh_intc.h> 12 #include <asm/addrspace.h> 13 14 /* Box specific addresses. */ 15 #define SE_AREA0_WIDTH 4 /* Area0: 32bit */ 16 #define PA_ROM 0xa0000000 /* EPROM */ 17 #define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */ 18 #define PA_FROM 0xa0800000 /* Flash-ROM */ 19 #define PA_FROM_SIZE 0x00400000 /* Flash-ROM size 4M byte */ 20 #define PA_EXT1 0xa4000000 21 #define PA_EXT1_SIZE 0x04000000 22 #define PA_SDRAM 0xa8000000 /* DDR-SDRAM(Area2/3) 128MB */ 23 #define PA_SDRAM_SIZE 0x08000000 24 25 #define PA_EXT4 0xb0000000 26 #define PA_EXT4_SIZE 0x04000000 27 #define PA_EXT_USER PA_EXT4 /* User Expansion Space */ 28 29 #define PA_PERIPHERAL PA_AREA5_IO 30 31 /* SRAM/Reserved */ 32 #define PA_RESERVED (PA_PERIPHERAL + 0) 33 /* FPGA base address */ 34 #define PA_FPGA (PA_PERIPHERAL + 0x01000000) 35 /* SMC LAN91C111 */ 36 #define PA_LAN (PA_PERIPHERAL + 0x01800000) 37 38 39 #define FPGA_SRSTR (PA_FPGA + 0x000) /* System reset */ 40 #define FPGA_IRQ0SR (PA_FPGA + 0x010) /* IRQ0 status */ 41 #define FPGA_IRQ0MR (PA_FPGA + 0x020) /* IRQ0 mask */ 42 #define FPGA_BDMR (PA_FPGA + 0x030) /* Board operating mode */ 43 #define FPGA_INTT0PRTR (PA_FPGA + 0x040) /* Interrupt test mode0 port */ 44 #define FPGA_INTT0SELR (PA_FPGA + 0x050) /* Int. test mode0 select */ 45 #define FPGA_INTT1POLR (PA_FPGA + 0x060) /* Int. test mode0 polarity */ 46 #define FPGA_NMIR (PA_FPGA + 0x070) /* NMI source */ 47 #define FPGA_NMIMR (PA_FPGA + 0x080) /* NMI mask */ 48 #define FPGA_IRQR (PA_FPGA + 0x090) /* IRQX source */ 49 #define FPGA_IRQMR (PA_FPGA + 0x0A0) /* IRQX mask */ 50 #define FPGA_SLEDR (PA_FPGA + 0x0B0) /* LED control */ 51 #define PA_LED FPGA_SLEDR 52 #define FPGA_MAPSWR (PA_FPGA + 0x0C0) /* Map switch */ 53 #define FPGA_FPVERR (PA_FPGA + 0x0D0) /* FPGA version */ 54 #define FPGA_FPDATER (PA_FPGA + 0x0E0) /* FPGA date */ 55 #define FPGA_RSE (PA_FPGA + 0x100) /* Reset source */ 56 #define FPGA_EASR (PA_FPGA + 0x110) /* External area select */ 57 #define FPGA_SPER (PA_FPGA + 0x120) /* Serial port enable */ 58 #define FPGA_IMSR (PA_FPGA + 0x130) /* Interrupt mode select */ 59 #define FPGA_PCIMR (PA_FPGA + 0x140) /* PCI Mode */ 60 #define FPGA_DIPSWMR (PA_FPGA + 0x150) /* DIPSW monitor */ 61 #define FPGA_FPODR (PA_FPGA + 0x160) /* Output port data */ 62 #define FPGA_ATAESR (PA_FPGA + 0x170) /* ATA extended bus status */ 63 #define FPGA_IRQPOLR (PA_FPGA + 0x180) /* IRQx polarity */ 64 65 66 #define SDK7780_NR_IRL 15 67 /* IDE/ATA interrupt */ 68 #define IRQ_CFCARD evt2irq(0x3c0) 69 /* SMC interrupt */ 70 #define IRQ_ETHERNET evt2irq(0x2c0) 71 72 73 /* arch/sh/boards/renesas/sdk7780/irq.c */ 74 void init_sdk7780_IRQ(void); 75 76 #define __IO_PREFIX sdk7780 77 #include <asm/io_generic.h> 78 79 #endif /* __ASM_SH_RENESAS_SDK7780_H */ 80