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/arch/arm64/boot/dts/cavium/
Dthunder2-99xx.dts19 reg = <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */
20 <0x00000008 0x80000000 0x0 0x80000000>; /* 2G @ 34G */
/arch/arc/plat-eznps/
Dentry.S30 ; 0G-2G: We disable CONFIG_ARC_CACHE_PAGES.
31 ; 2G-3G: We disable D$ by setting this bit.
32 ; 3G-4G: D$ is disabled by architecture.
33 ; FMT are huge pages for user application reside at 0-2G.
/arch/arm64/boot/dts/broadcom/stingray/
Dstingray-board-base.dtsi23 reg = <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */
24 <0x00000008 0x80000000 0x1 0x80000000>; /* 6G @ 34G */
/arch/arm/boot/dts/
Dstm32mp157-pinctrl.dtsi213 pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
214 <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
215 <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
216 <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
239 pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
240 <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
241 <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
242 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
271 <STM32_PINMUX('G', 9, AF12)>; /* FMC_NE2_FMC_NCE */
297 <STM32_PINMUX('G', 9, ANALOG)>; /* FMC_NE2_FMC_NCE */
[all …]
Domap3-igep0030-rev-g.dts3 * Device Tree Source for IGEP COM MODULE Rev. G (TI OMAP AM/DM37x)
12 model = "IGEP COM MODULE Rev. G (TI OMAP AM/DM37x)";
Drda8810pl-orangepi-2g-iot.dts13 model = "Orange Pi 2G-IoT";
Ds5pv210-fascinate4g.dts9 model = "Samsung Galaxy S Fascinate 4G (SGH-T959P) based on S5PV210";
Daspeed-bmc-opp-palmetto.dts303 gpios = <ASPEED_GPIO(G, 3) GPIO_ACTIVE_HIGH>;
310 gpios = <ASPEED_GPIO(G, 4) GPIO_ACTIVE_HIGH>;
317 gpios = <ASPEED_GPIO(G, 5) GPIO_ACTIVE_HIGH>;
Dstm32f7-pinctrl.dtsi259 pinmux = <STM32_PINMUX('G', 9, AF11)>, /* SDMMC2 D0 */
260 <STM32_PINMUX('G', 10, AF11)>, /* SDMMC2 D1 */
272 pinmux = <STM32_PINMUX('G', 9, AF11)>, /* SDMMC2 D0 */
273 <STM32_PINMUX('G', 10, AF11)>, /* SDMMC2 D1 */
Dat91-vinco.dts13 model = "L+G VInCo platform";
175 /* 4G Modem */
Dsun4i-a10-jesurun-q5.dts2 * Copyright 2015 Gábor Nyers
4 * Gábor Nyers <gabor.nyers@gmail.com>
Dstm32h743-pinctrl.dtsi178 pinmux = <STM32_PINMUX('G', 11, AF11)>,
179 <STM32_PINMUX('G', 13, AF11)>,
180 <STM32_PINMUX('G', 12, AF11)>,
/arch/arm64/crypto/
Dsha512-armv8.pl103 @V=($A,$B,$C,$D,$E,$F,$G,$H)=map("$reg_t$_",(20..27));
239 ldp $G,$H,[$ctx,#6*$SZ]
272 add $G,$G,@X[6]
276 stp $G,$H,[$ctx,#6*$SZ]
458 my @V = ($A,$B,$C,$D,$E,$F,$G,$H) = map("w$_",(3..10));
678 ldp $G,$H,[$ctx,#24]
724 add $G,$G,$t2
730 stp $G,$H,[$ctx,#24]
/arch/x86/kernel/
Didt.c24 #define G(_vector, _addr, _ist, _type, _dpl, _segment) \ macro
37 G(_vector, _addr, DEFAULT_STACK, GATE_INTERRUPT, DPL0, __KERNEL_CS)
41 G(_vector, _addr, DEFAULT_STACK, GATE_INTERRUPT, DPL3, __KERNEL_CS)
48 G(_vector, _addr, _ist + 1, GATE_INTERRUPT, DPL0, __KERNEL_CS)
52 G(_vector, NULL, DEFAULT_STACK, GATE_TASK, DPL0, _gdt << 3)
/arch/nds32/
DKconfig.cpu201 bool "3G/1G user/kernel split"
203 bool "3G/1G user/kernel split (for full 1G low memory)"
205 bool "2G/2G user/kernel split"
207 bool "1G/3G user/kernel split"
/arch/arm/crypto/
Dsha256-armv4.pl60 $G="r10";
62 @V=($A,$B,$C,$D,$E,$F,$G,$H);
230 ldmia $ctx,{$A,$B,$C,$D,$E,$F,$G,$H}
269 add $G,$G,$t0
271 stmia $t3,{$A,$B,$C,$D,$E,$F,$G,$H}
562 add $G,$G,$t3
/arch/arm64/boot/dts/ti/
Dk3-j721e-som-p0.dtsi13 /* 4G RAM */
/arch/x86/crypto/
Dtwofish-avx-x86_64-asm_64.S109 #define G(gi1, gi2, x, t0, t1, t2, t3) \ macro
124 G(RGI1, RGI2, x1, s0, s1, s2, s3); \
130 G(RGI3, RGI4, y1, s1, s2, s3, s0); \
136 G(RGI1, RGI2, x2, s0, s1, s2, s3); \
140 G(RGI3, RGI4, y2, s1, s2, s3, s0); \
Dcrct10dif-pcl-asm_64.S228 # Load 'x^48 * (x^48 mod G(x))' and 'x^48 * (x^80 mod G(x))'.
/arch/mips/alchemy/
DKconfig16 bool "4G Systems MTX-1 board"
DPlatform16 # 4G-Systems MTX-1 "MeshCube" wireless router
/arch/x86/um/
DKconfig39 Three-level pagetables will let UML have more than 4G of physical
/arch/arc/
DKconfig432 -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU
433 -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel
453 With ARC 2G:2G address split, only upper 2G is directly addressable by
454 kernel. Enable this to potentially allow access to rest of 2G and PAE
463 Enable access to physical memory beyond 4G, only supported on
/arch/m68k/fpsp040/
Dround.S540 bfextu FP_SCR2+LOCAL_LO(%a6){%d0:#32},%d0 |d0 = new G,R,S
550 andil #0xe0000000,%d2 |clear all but G,R,S
551 tstl %d2 |test if original G,R,S are clear
555 andil #0xe0000000,%d0 |clear all but G,R,S
569 bfextu LOCAL_HI(%a0){%d0:#32},%d1 |d1 = new G,R,S
585 andil #0xe0000000,%d2 |clear all but G,R,S
586 tstl %d2 |test if original G,R,S are clear
590 andil #0xe0000000,%d0 |get rid of all but G,R,S
/arch/arm64/boot/dts/amd/
Damd-seattle-soc.dtsi228 /* 32-bit MMIO (size=2G) */
230 /* 64-bit MMIO (size= 124G) */

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