| /arch/mips/pci/ |
| D | fixup-sni.c | 26 #define INTC PCIMT_IRQ_INTC macro
50 { 0, INTB, INTC, INTD, INTA }, /* Slot 2 */
51 { 0, INTC, INTD, INTA, INTB }, /* Slot 3 */
52 { 0, INTD, INTA, INTB, INTC }, /* Slot 4 */
64 { 0, INTC, INTD, INTA, INTB }, /* Slot 1 */
67 { 0, INTB, INTC, INTD, INTA }, /* Slot 2 */
68 { 0, INTC, INTD, INTA, INTB }, /* Slot 3 */
69 { 0, INTD, INTA, INTB, INTC }, /* Slot 4 */
76 { 0, INTC, INTD, INTA, INTB }, /* Bridge/i960 */
77 { 0, INTD, INTA, INTB, INTC }, /* Slot 1 */
[all …]
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| D | fixup-ip32.c | 23 #define INTC MACEPCI_SHARED1_IRQ macro
30 {0, INTA0, INTB, INTC, INTD},
31 {0, INTA1, INTC, INTD, INTB},
32 {0, INTA2, INTD, INTB, INTC},
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| D | fixup-capcella.c | 19 #define INTC PC104PLUS_INTC_IRQ macro
25 [14] = { -1, INTA, INTB, INTC, INTD }
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| /arch/arm/mach-iop32x/ |
| D | em7210.c | 76 #define INTC IRQ_IOP32X_XINT2 macro
90 {INTC, INTC, INTC, INTC}, /* GD31244 */ in em7210_pci_map_irq()
92 {INTD, INTC, INTA, INTA}, /* NEC USB */ in em7210_pci_map_irq()
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| D | glantank.c | 71 #define INTC IRQ_IOP32X_XINT2 macro
85 {INTC, INTC, INTC, INTC}, /* USB (NEC) */ in glantank_pci_map_irq()
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| /arch/arm/mach-ixp4xx/ |
| D | nslu2-pci.c | 28 #define INTC 9 macro
35 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); in nslu2_pci_preinit()
44 IXP4XX_GPIO_IRQ(INTC), in nslu2_map_irq()
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| D | miccpt-pci.c | 32 #define INTC 3 macro
40 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); in miccpt_pci_preinit()
50 IXP4XX_GPIO_IRQ(INTC), in miccpt_map_irq()
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| D | avila-pci.c | 35 #define INTC 9 macro
42 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); in avila_pci_preinit()
52 IXP4XX_GPIO_IRQ(INTC), in avila_map_irq()
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| D | ixdp425-pci.c | 31 #define INTC 9 macro
39 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); in ixdp425_pci_preinit()
49 IXP4XX_GPIO_IRQ(INTC), in ixdp425_map_irq()
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| D | fsg-pci.c | 29 #define INTC 5 macro
35 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); in fsg_pci_preinit()
42 IXP4XX_GPIO_IRQ(INTC), in fsg_map_irq()
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| D | nas100d-pci.c | 28 #define INTC 9 macro
36 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); in nas100d_pci_preinit()
47 { IXP4XX_GPIO_IRQ(INTC), IXP4XX_GPIO_IRQ(INTD), in nas100d_map_irq()
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| D | dsmg600-pci.c | 29 #define INTC 9 macro
38 irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); in dsmg600_pci_preinit()
50 { IXP4XX_GPIO_IRQ(INTB), IXP4XX_GPIO_IRQ(INTC), in dsmg600_map_irq()
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| /arch/arc/boot/dts/ |
| D | axc001.dtsi | 77 * This INTC is actually connected to DW APB GPIO
78 * which acts as a wire between MB INTC and CPU INTC.
79 * GPIO INTC is configured in platform init code
80 * and here we mimic direct connection from MB INTC to
81 * CPU INTC, thus we set "interrupts = <7>" instead of
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| D | axc003_idu.dtsi | 127 * This INTC is actually connected to DW APB GPIO
128 * which acts as a wire between MB INTC and CPU INTC.
129 * GPIO INTC is configured in platform init code
130 * and here we mimic direct connection from MB INTC to
131 * CPU INTC, thus we set "interrupts = <0 1>" instead of
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| /arch/powerpc/boot/dts/ |
| D | holly.dts | 157 | The INTA, INTB, INTC, INTD are shared.
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| D | katmai.dts | 309 * INTC: J2: 1-2
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| /arch/arm64/boot/dts/socionext/ |
| D | uniphier-pxs3.dtsi | 764 <0 0 0 3 &pcie_intc 2>, /* INTC */
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| D | uniphier-ld20.dtsi | 906 <0 0 0 3 &pcie_intc 2>, /* INTC */
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