Searched refs:LL (Results 1 – 25 of 38) sorted by relevance
12
| /arch/parisc/include/asm/ |
| D | processor.h | 266 regs->fr[ 0] = 0LL; \
267 regs->fr[ 1] = 0LL; \
268 regs->fr[ 2] = 0LL; \
269 regs->fr[ 3] = 0LL; \
|
| /arch/mips/include/asm/octeon/ |
| D | cvmx-address.h | 40 CVMX_MIPS_SPACE_XUSEG = 0LL
45 CVMX_MIPS_XKSEG_SPACE_KSEG0 = 0LL,
|
| D | cvmx.h | 39 CVMX_MIPS_SPACE_XUSEG = 0LL
|
| D | cvmx-ipd.h | 42 CVMX_IPD_OPC_MODE_STT = 0LL, /* All blocks DRAM, not cached in L2 */
|
| /arch/arm/kernel/ |
| D | perf_event_v7.c | 187 [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L2_CACHE_ACCESS,
188 [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_A8_PERFCTR_L2_CACHE_REFILL,
189 [C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L2_CACHE_ACCESS,
190 [C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_A8_PERFCTR_L2_CACHE_REFILL,
326 [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_READ,
327 [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L2_CACHE_REFILL_READ,
328 [C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_WRITE,
329 [C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L2_CACHE_REFILL_WRITE,
375 [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L2_CACHE_ACCESS,
376 [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACHE_REFILL,
[all …]
|
| /arch/arm/nwfpe/ |
| D | ARM-gcc.h | 62 #define LIT64( a ) a##LL
|
| /arch/powerpc/perf/ |
| D | e6500-pmu.c | 53 [C(LL)] = {
|
| D | e500-pmu.c | 55 [C(LL)] = { /* RESULT_ACCESS RESULT_MISS */
|
| D | generic-compat-pmu.c | 133 [ C(LL) ] = {
|
| D | mpc7450-pmu.c | 368 [C(LL)] = { /* RESULT_ACCESS RESULT_MISS */
|
| D | power8-pmu.c | 285 [ C(LL) ] = {
|
| D | ppc970-pmu.c | 446 [C(LL)] = { /* RESULT_ACCESS RESULT_MISS */
|
| D | power7-pmu.c | 346 [C(LL)] = { /* RESULT_ACCESS RESULT_MISS */
|
| D | power6-pmu.c | 495 [C(LL)] = { /* RESULT_ACCESS RESULT_MISS */
|
| /arch/mips/include/asm/ |
| D | addrspace.h | 30 #define _CONST64_(x) x ## LL
|
| /arch/x86/events/intel/ |
| D | core.c | 455 [ C(LL ) ] = {
532 [ C(LL ) ] = {
620 [ C(LL ) ] = {
683 [ C(LL ) ] = {
839 [ C(LL ) ] = {
916 [ C(LL ) ] = {
991 [ C(LL ) ] = {
1111 [ C(LL ) ] = {
1174 [ C(LL ) ] = {
1289 [ C(LL ) ] = {
[all …]
|
| D | p6.c | 56 [ C(LL ) ] = {
|
| D | knc.c | 59 [ C(LL ) ] = {
|
| /arch/mips/kvm/ |
| D | 00README.txt | 25 LL/TLBP/SC. Since the TLBP instruction causes a trap the reservation gets cleared
|
| /arch/arc/include/asm/ |
| D | perf_event.h | 155 [C(LL)] = {
|
| /arch/sh/kernel/cpu/sh4a/ |
| D | perf_event.c | 146 [ C(LL) ] = {
|
| /arch/sh/kernel/cpu/sh4/ |
| D | perf_event.c | 121 [ C(LL) ] = {
|
| /arch/x86/events/amd/ |
| D | core.c | 50 [ C(LL ) ] = {
154 [C(LL)] = {
|
| /arch/mips/kernel/ |
| D | perf_event_mipsxx.c | 908 [C(LL)] = {
989 [C(LL)] = {
1160 [C(LL)] = {
1242 [C(LL)] = {
|
| /arch/nds32/include/asm/ |
| D | pmu.h | 284 [C(LL)] = {
|
12