1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * arch/arm/include/asm/pgtable-3level.h
4 *
5 * Copyright (C) 2011 ARM Ltd.
6 * Author: Catalin Marinas <catalin.marinas@arm.com>
7 */
8 #ifndef _ASM_PGTABLE_3LEVEL_H
9 #define _ASM_PGTABLE_3LEVEL_H
10
11 /*
12 * With LPAE, there are 3 levels of page tables. Each level has 512 entries of
13 * 8 bytes each, occupying a 4K page. The first level table covers a range of
14 * 512GB, each entry representing 1GB. Since we are limited to 4GB input
15 * address range, only 4 entries in the PGD are used.
16 *
17 * There are enough spare bits in a page table entry for the kernel specific
18 * state.
19 */
20 #define PTRS_PER_PTE 512
21 #define PTRS_PER_PMD 512
22 #define PTRS_PER_PGD 4
23
24 #define PTE_HWTABLE_PTRS (0)
25 #define PTE_HWTABLE_OFF (0)
26 #define PTE_HWTABLE_SIZE (PTRS_PER_PTE * sizeof(u64))
27
28 #define MAX_POSSIBLE_PHYSMEM_BITS 40
29
30 /*
31 * PGDIR_SHIFT determines the size a top-level page table entry can map.
32 */
33 #define PGDIR_SHIFT 30
34
35 /*
36 * PMD_SHIFT determines the size a middle-level page table entry can map.
37 */
38 #define PMD_SHIFT 21
39
40 #define PMD_SIZE (1UL << PMD_SHIFT)
41 #define PMD_MASK (~((1 << PMD_SHIFT) - 1))
42 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
43 #define PGDIR_MASK (~((1 << PGDIR_SHIFT) - 1))
44
45 /*
46 * section address mask and size definitions.
47 */
48 #define SECTION_SHIFT 21
49 #define SECTION_SIZE (1UL << SECTION_SHIFT)
50 #define SECTION_MASK (~((1 << SECTION_SHIFT) - 1))
51
52 #define USER_PTRS_PER_PGD (PAGE_OFFSET / PGDIR_SIZE)
53
54 /*
55 * Hugetlb definitions.
56 */
57 #define HPAGE_SHIFT PMD_SHIFT
58 #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT)
59 #define HPAGE_MASK (~(HPAGE_SIZE - 1))
60 #define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
61
62 /*
63 * "Linux" PTE definitions for LPAE.
64 *
65 * These bits overlap with the hardware bits but the naming is preserved for
66 * consistency with the classic page table format.
67 */
68 #define L_PTE_VALID (_AT(pteval_t, 1) << 0) /* Valid */
69 #define L_PTE_PRESENT (_AT(pteval_t, 3) << 0) /* Present */
70 #define L_PTE_USER (_AT(pteval_t, 1) << 6) /* AP[1] */
71 #define L_PTE_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */
72 #define L_PTE_YOUNG (_AT(pteval_t, 1) << 10) /* AF */
73 #define L_PTE_XN (_AT(pteval_t, 1) << 54) /* XN */
74 #define L_PTE_DIRTY (_AT(pteval_t, 1) << 55)
75 #define L_PTE_SPECIAL (_AT(pteval_t, 1) << 56)
76 #define L_PTE_NONE (_AT(pteval_t, 1) << 57) /* PROT_NONE */
77 #define L_PTE_RDONLY (_AT(pteval_t, 1) << 58) /* READ ONLY */
78
79 #define L_PMD_SECT_VALID (_AT(pmdval_t, 1) << 0)
80 #define L_PMD_SECT_DIRTY (_AT(pmdval_t, 1) << 55)
81 #define L_PMD_SECT_NONE (_AT(pmdval_t, 1) << 57)
82 #define L_PMD_SECT_RDONLY (_AT(pteval_t, 1) << 58)
83
84 /*
85 * To be used in assembly code with the upper page attributes.
86 */
87 #define L_PTE_XN_HIGH (1 << (54 - 32))
88 #define L_PTE_DIRTY_HIGH (1 << (55 - 32))
89
90 /*
91 * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
92 */
93 #define L_PTE_MT_UNCACHED (_AT(pteval_t, 0) << 2) /* strongly ordered */
94 #define L_PTE_MT_BUFFERABLE (_AT(pteval_t, 1) << 2) /* normal non-cacheable */
95 #define L_PTE_MT_WRITETHROUGH (_AT(pteval_t, 2) << 2) /* normal inner write-through */
96 #define L_PTE_MT_WRITEBACK (_AT(pteval_t, 3) << 2) /* normal inner write-back */
97 #define L_PTE_MT_WRITEALLOC (_AT(pteval_t, 7) << 2) /* normal inner write-alloc */
98 #define L_PTE_MT_DEV_SHARED (_AT(pteval_t, 4) << 2) /* device */
99 #define L_PTE_MT_DEV_NONSHARED (_AT(pteval_t, 4) << 2) /* device */
100 #define L_PTE_MT_DEV_WC (_AT(pteval_t, 1) << 2) /* normal non-cacheable */
101 #define L_PTE_MT_DEV_CACHED (_AT(pteval_t, 3) << 2) /* normal inner write-back */
102 #define L_PTE_MT_MASK (_AT(pteval_t, 7) << 2)
103
104 /*
105 * Software PGD flags.
106 */
107 #define L_PGD_SWAPPER (_AT(pgdval_t, 1) << 55) /* swapper_pg_dir entry */
108
109 /*
110 * 2nd stage PTE definitions for LPAE.
111 */
112 #define L_PTE_S2_MT_UNCACHED (_AT(pteval_t, 0x0) << 2) /* strongly ordered */
113 #define L_PTE_S2_MT_WRITETHROUGH (_AT(pteval_t, 0xa) << 2) /* normal inner write-through */
114 #define L_PTE_S2_MT_WRITEBACK (_AT(pteval_t, 0xf) << 2) /* normal inner write-back */
115 #define L_PTE_S2_MT_DEV_SHARED (_AT(pteval_t, 0x1) << 2) /* device */
116 #define L_PTE_S2_MT_MASK (_AT(pteval_t, 0xf) << 2)
117
118 #define L_PTE_S2_RDONLY (_AT(pteval_t, 1) << 6) /* HAP[1] */
119 #define L_PTE_S2_RDWR (_AT(pteval_t, 3) << 6) /* HAP[2:1] */
120
121 #define L_PMD_S2_RDONLY (_AT(pmdval_t, 1) << 6) /* HAP[1] */
122 #define L_PMD_S2_RDWR (_AT(pmdval_t, 3) << 6) /* HAP[2:1] */
123
124 /*
125 * Hyp-mode PL2 PTE definitions for LPAE.
126 */
127 #define L_PTE_HYP L_PTE_USER
128
129 #ifndef __ASSEMBLY__
130
131 #define pud_none(pud) (!pud_val(pud))
132 #define pud_bad(pud) (!(pud_val(pud) & 2))
133 #define pud_present(pud) (pud_val(pud))
134 #define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
135 PMD_TYPE_TABLE)
136 #define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
137 PMD_TYPE_SECT)
138 #define pmd_large(pmd) pmd_sect(pmd)
139
140 #define pud_clear(pudp) \
141 do { \
142 *pudp = __pud(0); \
143 clean_pmd_entry(pudp); \
144 } while (0)
145
146 #define set_pud(pudp, pud) \
147 do { \
148 *pudp = pud; \
149 flush_pmd_entry(pudp); \
150 } while (0)
151
pud_page_vaddr(pud_t pud)152 static inline pmd_t *pud_page_vaddr(pud_t pud)
153 {
154 return __va(pud_val(pud) & PHYS_MASK & (s32)PAGE_MASK);
155 }
156
157 /* Find an entry in the second-level page table.. */
158 #define pmd_index(addr) (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1))
pmd_offset(pud_t * pud,unsigned long addr)159 static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr)
160 {
161 return (pmd_t *)pud_page_vaddr(*pud) + pmd_index(addr);
162 }
163
164 #define pmd_bad(pmd) (!(pmd_val(pmd) & 2))
165
166 #define copy_pmd(pmdpd,pmdps) \
167 do { \
168 *pmdpd = *pmdps; \
169 flush_pmd_entry(pmdpd); \
170 } while (0)
171
172 #define pmd_clear(pmdp) \
173 do { \
174 *pmdp = __pmd(0); \
175 clean_pmd_entry(pmdp); \
176 } while (0)
177
178 /*
179 * For 3 levels of paging the PTE_EXT_NG bit will be set for user address ptes
180 * that are written to a page table but not for ptes created with mk_pte.
181 *
182 * In hugetlb_no_page, a new huge pte (new_pte) is generated and passed to
183 * hugetlb_cow, where it is compared with an entry in a page table.
184 * This comparison test fails erroneously leading ultimately to a memory leak.
185 *
186 * To correct this behaviour, we mask off PTE_EXT_NG for any pte that is
187 * present before running the comparison.
188 */
189 #define __HAVE_ARCH_PTE_SAME
190 #define pte_same(pte_a,pte_b) ((pte_present(pte_a) ? pte_val(pte_a) & ~PTE_EXT_NG \
191 : pte_val(pte_a)) \
192 == (pte_present(pte_b) ? pte_val(pte_b) & ~PTE_EXT_NG \
193 : pte_val(pte_b)))
194
195 #define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,__pte(pte_val(pte)|(ext)))
196
197 #define pte_huge(pte) (pte_val(pte) && !(pte_val(pte) & PTE_TABLE_BIT))
198 #define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT))
199
200 #define pmd_isset(pmd, val) ((u32)(val) == (val) ? pmd_val(pmd) & (val) \
201 : !!(pmd_val(pmd) & (val)))
202 #define pmd_isclear(pmd, val) (!(pmd_val(pmd) & (val)))
203
204 #define pmd_present(pmd) (pmd_isset((pmd), L_PMD_SECT_VALID))
205 #define pmd_young(pmd) (pmd_isset((pmd), PMD_SECT_AF))
206 #define pte_special(pte) (pte_isset((pte), L_PTE_SPECIAL))
pte_mkspecial(pte_t pte)207 static inline pte_t pte_mkspecial(pte_t pte)
208 {
209 pte_val(pte) |= L_PTE_SPECIAL;
210 return pte;
211 }
212
213 #define pmd_write(pmd) (pmd_isclear((pmd), L_PMD_SECT_RDONLY))
214 #define pmd_dirty(pmd) (pmd_isset((pmd), L_PMD_SECT_DIRTY))
215 #define pud_page(pud) pmd_page(__pmd(pud_val(pud)))
216 #define pud_write(pud) pmd_write(__pmd(pud_val(pud)))
217
218 #define pmd_hugewillfault(pmd) (!pmd_young(pmd) || !pmd_write(pmd))
219 #define pmd_thp_or_huge(pmd) (pmd_huge(pmd) || pmd_trans_huge(pmd))
220
221 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
222 #define pmd_trans_huge(pmd) (pmd_val(pmd) && !pmd_table(pmd))
223 #endif
224
225 #define PMD_BIT_FUNC(fn,op) \
226 static inline pmd_t pmd_##fn(pmd_t pmd) { pmd_val(pmd) op; return pmd; }
227
228 PMD_BIT_FUNC(wrprotect, |= L_PMD_SECT_RDONLY);
229 PMD_BIT_FUNC(mkold, &= ~PMD_SECT_AF);
230 PMD_BIT_FUNC(mkwrite, &= ~L_PMD_SECT_RDONLY);
231 PMD_BIT_FUNC(mkdirty, |= L_PMD_SECT_DIRTY);
232 PMD_BIT_FUNC(mkclean, &= ~L_PMD_SECT_DIRTY);
233 PMD_BIT_FUNC(mkyoung, |= PMD_SECT_AF);
234
235 #define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT))
236
237 #define pmd_pfn(pmd) (((pmd_val(pmd) & PMD_MASK) & PHYS_MASK) >> PAGE_SHIFT)
238 #define pfn_pmd(pfn,prot) (__pmd(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)))
239 #define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot)
240
241 /* No hardware dirty/accessed bits -- generic_pmdp_establish() fits */
242 #define pmdp_establish generic_pmdp_establish
243
244 /* represent a notpresent pmd by faulting entry, this is used by pmdp_invalidate */
pmd_mknotpresent(pmd_t pmd)245 static inline pmd_t pmd_mknotpresent(pmd_t pmd)
246 {
247 return __pmd(pmd_val(pmd) & ~L_PMD_SECT_VALID);
248 }
249
pmd_modify(pmd_t pmd,pgprot_t newprot)250 static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
251 {
252 const pmdval_t mask = PMD_SECT_USER | PMD_SECT_XN | L_PMD_SECT_RDONLY |
253 L_PMD_SECT_VALID | L_PMD_SECT_NONE;
254 pmd_val(pmd) = (pmd_val(pmd) & ~mask) | (pgprot_val(newprot) & mask);
255 return pmd;
256 }
257
set_pmd_at(struct mm_struct * mm,unsigned long addr,pmd_t * pmdp,pmd_t pmd)258 static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
259 pmd_t *pmdp, pmd_t pmd)
260 {
261 BUG_ON(addr >= TASK_SIZE);
262
263 /* create a faulting entry if PROT_NONE protected */
264 if (pmd_val(pmd) & L_PMD_SECT_NONE)
265 pmd_val(pmd) &= ~L_PMD_SECT_VALID;
266
267 if (pmd_write(pmd) && pmd_dirty(pmd))
268 pmd_val(pmd) &= ~PMD_SECT_AP2;
269 else
270 pmd_val(pmd) |= PMD_SECT_AP2;
271
272 *pmdp = __pmd(pmd_val(pmd) | PMD_SECT_nG);
273 flush_pmd_entry(pmdp);
274 }
275
276 #endif /* __ASSEMBLY__ */
277
278 #endif /* _ASM_PGTABLE_3LEVEL_H */
279