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Searched refs:MCF_CLK (Results 1 – 25 of 29) sorted by relevance

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/arch/m68k/coldfire/
Dm5441x.c20 DEFINE_CLK(0, "flexbus", 2, MCF_CLK);
21 DEFINE_CLK(0, "mcfcan.0", 8, MCF_CLK);
22 DEFINE_CLK(0, "mcfcan.1", 9, MCF_CLK);
23 DEFINE_CLK(0, "imx1-i2c.1", 14, MCF_CLK);
24 DEFINE_CLK(0, "mcfdspi.1", 15, MCF_CLK);
25 DEFINE_CLK(0, "edma", 17, MCF_CLK);
26 DEFINE_CLK(0, "intc.0", 18, MCF_CLK);
27 DEFINE_CLK(0, "intc.1", 19, MCF_CLK);
28 DEFINE_CLK(0, "intc.2", 20, MCF_CLK);
29 DEFINE_CLK(0, "imx1-i2c.0", 22, MCF_CLK);
[all …]
Dm520x.c27 DEFINE_CLK(0, "flexbus", 2, MCF_CLK);
28 DEFINE_CLK(0, "fec.0", 12, MCF_CLK);
29 DEFINE_CLK(0, "edma", 17, MCF_CLK);
30 DEFINE_CLK(0, "intc.0", 18, MCF_CLK);
31 DEFINE_CLK(0, "iack.0", 21, MCF_CLK);
32 DEFINE_CLK(0, "imx1-i2c.0", 22, MCF_CLK);
33 DEFINE_CLK(0, "mcfqspi.0", 23, MCF_CLK);
37 DEFINE_CLK(0, "mcftmr.0", 28, MCF_CLK);
38 DEFINE_CLK(0, "mcftmr.1", 29, MCF_CLK);
39 DEFINE_CLK(0, "mcftmr.2", 30, MCF_CLK);
[all …]
Dm53xx.c30 DEFINE_CLK(0, "flexbus", 2, MCF_CLK);
31 DEFINE_CLK(0, "mcfcan.0", 8, MCF_CLK);
32 DEFINE_CLK(0, "fec.0", 12, MCF_CLK);
33 DEFINE_CLK(0, "edma", 17, MCF_CLK);
34 DEFINE_CLK(0, "intc.0", 18, MCF_CLK);
35 DEFINE_CLK(0, "intc.1", 19, MCF_CLK);
36 DEFINE_CLK(0, "iack.0", 21, MCF_CLK);
37 DEFINE_CLK(0, "imx1-i2c.0", 22, MCF_CLK);
38 DEFINE_CLK(0, "mcfqspi.0", 23, MCF_CLK);
42 DEFINE_CLK(0, "mcftmr.0", 28, MCF_CLK);
[all …]
Dm523x.c27 DEFINE_CLK(pll, "pll.0", MCF_CLK);
29 DEFINE_CLK(mcfpit0, "mcfpit.0", MCF_CLK);
30 DEFINE_CLK(mcfpit1, "mcfpit.1", MCF_CLK);
31 DEFINE_CLK(mcfpit2, "mcfpit.2", MCF_CLK);
32 DEFINE_CLK(mcfpit3, "mcfpit.3", MCF_CLK);
Dm528x.c29 DEFINE_CLK(pll, "pll.0", MCF_CLK);
31 DEFINE_CLK(mcfpit0, "mcfpit.0", MCF_CLK);
32 DEFINE_CLK(mcfpit1, "mcfpit.1", MCF_CLK);
33 DEFINE_CLK(mcfpit2, "mcfpit.2", MCF_CLK);
34 DEFINE_CLK(mcfpit3, "mcfpit.3", MCF_CLK);
Dm527x.c28 DEFINE_CLK(pll, "pll.0", MCF_CLK);
30 DEFINE_CLK(mcfpit0, "mcfpit.0", MCF_CLK);
31 DEFINE_CLK(mcfpit1, "mcfpit.1", MCF_CLK);
32 DEFINE_CLK(mcfpit2, "mcfpit.2", MCF_CLK);
33 DEFINE_CLK(mcfpit3, "mcfpit.3", MCF_CLK);
Dm5407.c24 DEFINE_CLK(pll, "pll.0", MCF_CLK);
Dm5206.c24 DEFINE_CLK(pll, "pll.0", MCF_CLK);
Dm5307.c33 DEFINE_CLK(pll, "pll.0", MCF_CLK);
Ddma_timer.c30 #define DMA_FREQ ((MCF_CLK / 2) / 16)
Dm54xx.c33 DEFINE_CLK(pll, "pll.0", MCF_CLK);
Dm525x.c24 DEFINE_CLK(pll, "pll.0", MCF_CLK);
Dm5272.c35 DEFINE_CLK(pll, "pll.0", MCF_CLK);
Dm5249.c24 DEFINE_CLK(pll, "pll.0", MCF_CLK);
Dpit.c34 #define FREQ ((MCF_CLK / 2) / 64)
/arch/m68k/include/asm/
Dcoldfire.h24 #define MCF_CLK CONFIG_CLOCK_FREQ macro
Dtimex.h16 #define CLOCK_TICK_RATE MCF_CLK
Dm54xxsim.h11 #define MCF_BUSCLK (MCF_CLK / 2)
Dm5407sim.h20 #define MCF_BUSCLK (MCF_CLK / 2)
Dm5272sim.h18 #define MCF_BUSCLK MCF_CLK
Dm520xsim.h17 #define MCF_BUSCLK (MCF_CLK / 2)
Dm5206sim.h18 #define MCF_BUSCLK MCF_CLK
Dm5307sim.h20 #define MCF_BUSCLK (MCF_CLK / 2)
Dm523xsim.h17 #define MCF_BUSCLK (MCF_CLK / 2)
Dm5441xsim.h13 #define MCF_BUSCLK (MCF_CLK / 2)

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