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Searched refs:MSR_K7_EVNTSEL0 (Results 1 – 7 of 7) sorted by relevance

/arch/x86/xen/
Dpmu.c89 amd_ctrls_base = MSR_K7_EVNTSEL0; in xen_pmu_arch_init()
97 amd_ctrls_base = MSR_K7_EVNTSEL0; in xen_pmu_arch_init()
120 case MSR_K7_EVNTSEL0: in get_fam15h_addr()
124 return MSR_F15H_PERF_CTL + (addr - MSR_K7_EVNTSEL0); in get_fam15h_addr()
136 (msr >= MSR_K7_EVNTSEL0 && in is_amd_pmu_msr()
265 ((msr >= MSR_K7_EVNTSEL0) && (msr <= MSR_K7_PERFCTR3))) in xen_amd_pmu_emulate()
/arch/x86/kvm/
Dpmu_amd.c76 return MSR_K7_EVNTSEL0; in get_msr_base()
85 case MSR_K7_EVNTSEL0: in msr_to_index()
124 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: in get_gp_pmc_amd()
Dx86.c1246 MSR_K7_EVNTSEL0, MSR_K7_EVNTSEL1, MSR_K7_EVNTSEL2, MSR_K7_EVNTSEL3,
2894 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: in kvm_set_msr_common()
3038 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3: in kvm_get_msr_common()
/arch/x86/kernel/cpu/
Dperfctr-watchdog.c82 return msr - MSR_K7_EVNTSEL0; in nmi_evntsel_msr_to_bit()
/arch/x86/oprofile/
Dop_model_amd.c298 release_evntsel_nmi(MSR_K7_EVNTSEL0 + i); in op_amd_shutdown()
309 if (!reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i)) { in op_amd_fill_in_addresses()
318 msrs->controls[i].addr = MSR_K7_EVNTSEL0 + i; in op_amd_fill_in_addresses()
/arch/x86/include/asm/
Dmsr-index.h571 #define MSR_K7_EVNTSEL0 0xc0010000 macro
/arch/x86/events/amd/
Dcore.c910 .eventsel = MSR_K7_EVNTSEL0,