Searched refs:MSR_TM (Results 1 – 12 of 12) sorted by relevance
67 (newmsr & MSR_TM))); in kvmhv_p9_tm_emulation()114 (newmsr & MSR_TM))); in kvmhv_p9_tm_emulation()135 if (!(msr & MSR_TM)) { in kvmhv_p9_tm_emulation()165 if (!(msr & MSR_TM)) { in kvmhv_p9_tm_emulation()203 if (!(msr & MSR_TM)) { in kvmhv_p9_tm_emulation()
42 if (!(MSR_TM_TRANSACTIONAL(newmsr) && (newmsr & MSR_TM))) in kvmhv_p9_tm_emulation_early()79 if (!(MSR_TM_TRANSACTIONAL(newmsr) && (newmsr & MSR_TM))) in kvmhv_p9_tm_emulation_early()95 if (!(vcpu->arch.hfscr & HFSCR_TM) || !(msr & MSR_TM)) in kvmhv_p9_tm_emulation_early()
279 if (((cur_msr & MSR_TM) == 0) && in kvmppc_core_emulate_op_pr()280 ((srr1 & MSR_TM) == 0) && in kvmppc_core_emulate_op_pr()495 if (!(kvmppc_get_msr(vcpu) & MSR_TM)) { in kvmppc_core_emulate_op_pr()533 if (!(kvmppc_get_msr(vcpu) & MSR_TM)) { in kvmppc_core_emulate_op_pr()559 if (!(kvmppc_get_msr(vcpu) & MSR_TM)) { in kvmppc_core_emulate_op_pr()593 if (!(kvmppc_get_msr(vcpu) & MSR_TM)) { in kvmppc_core_emulate_op_pr()789 if (!(kvmppc_get_msr(vcpu) & MSR_TM)) { in kvmppc_core_emulate_mtspr_pr()967 if (!(kvmppc_get_msr(vcpu) & MSR_TM)) { in kvmppc_core_emulate_mfspr_pr()
196 MSR_TM | MSR_TS_MASK; in kvmppc_recalc_shadow_msr()215 smsr &= ~MSR_TM; in kvmppc_recalc_shadow_msr()359 if (kvmppc_get_msr(vcpu) & MSR_TM) { in kvmppc_restore_tm_pr()371 if (kvmppc_get_msr(vcpu) & MSR_TM) { in kvmppc_restore_tm_pr()531 if (kvmppc_get_msr(vcpu) & MSR_TM) in kvmppc_set_msr_pr()983 guest_fac_enabled = kvmppc_get_msr(vcpu) & MSR_TM; in kvmppc_handle_fac()
235 li r6, MSR_TM >> 32
4263 (current->thread.regs->msr & MSR_TM)) { in kvmppc_vcpu_run_hv()4270 mtmsr(mfmsr() | MSR_TM); in kvmppc_vcpu_run_hv()4274 current->thread.regs->msr &= ~MSR_TM; in kvmppc_vcpu_run_hv()
53 li r3, MSR_TM >> 3264 li r3, MSR_TM >> 32
826 return tsk && tsk->thread.regs && (tsk->thread.regs->msr & MSR_TM); in tm_enabled()927 if (!(thread->regs->msr & MSR_TM)) in tm_recheckpoint()996 prev->thread.regs->msr &= ~MSR_TM; in __switch_to_tm()1349 {MSR_TM, "E"},1362 if (val & (MSR_TM | MSR_TS_S | MSR_TS_T)) { in print_tm_bits()
577 regs->msr |= MSR_TM; in restore_tm_sigcontexts()
1695 regs->msr |= MSR_TM; in tm_unavailable()
119 #define MSR_TM __MASK(MSR_TM_LG) /* Transactional Mem Available */ macro
1906 if (msr & MSR_TM) { in dump_207_sprs()