| /arch/arm/kvm/ |
| D | coproc.c | 252 switch (p->Op1) { in access_gic_sgi()
381 { CRn( 0), CRm( 0), Op1( 0), Op2( 5), is32,
385 { CRn( 0), CRm( 0), Op1( 2), Op2( 0), is32,
389 { CRn( 1), CRm( 0), Op1( 0), Op2( 1), is32,
393 { CRn( 1), CRm( 0), Op1( 0), Op2( 2), is32,
397 { CRm64( 2), Op1( 0), is64, access_vm_reg, reset_unknown64, c2_TTBR0 },
398 { CRn(2), CRm( 0), Op1( 0), Op2( 0), is32,
400 { CRn(2), CRm( 0), Op1( 0), Op2( 1), is32,
402 { CRn( 2), CRm( 0), Op1( 0), Op2( 2), is32,
404 { CRm64( 2), Op1( 1), is64, access_vm_reg, reset_unknown64, c2_TTBR1 },
[all …]
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| D | coproc.h | 13 unsigned long Op1; member
25 unsigned long Op1; member
50 p->CRn, p->Op1, p->is_write ? "write" : "read"); in print_cp_instr()
54 p->CRn, p->CRm, p->Op1, p->Op2, in print_cp_instr()
110 if (i1->Op1 != i2->Op1) in cmp_reg()
111 return i1->Op1 - i2->Op1; in cmp_reg()
121 #define Op1(_x) .Op1 = _x macro
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| D | trace.h | 12 TP_PROTO(unsigned long Op1, unsigned long Rt1, unsigned long CRn,
14 TP_ARGS(Op1, Rt1, CRn, CRm, Op2, is_write),
17 __field( unsigned int, Op1 )
27 __entry->Op1 = Op1;
36 __entry->Op1, __entry->Rt1, __entry->CRn,
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| D | coproc_a7.c | 27 { CRn( 1), CRm( 0), Op1( 0), Op2( 0), is32,
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| D | coproc_a15.c | 24 { CRn( 1), CRm( 0), Op1( 0), Op2( 0), is32,
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| /arch/arm64/kvm/ |
| D | sys_regs.h | 16 u8 Op1; member
32 u8 Op1; member
69 p->Op0, p->Op1, p->CRn, p->CRm, p->Op2, p->is_write ? "write" : "read"); in print_sys_reg_instr()
129 if (i1->Op1 != i2->Op1) in cmp_sys_reg()
130 return i1->Op1 - i2->Op1; in cmp_sys_reg()
144 #define Op1(_x) .Op1 = _x macro
151 Op0(sys_reg_Op0(reg)), Op1(sys_reg_Op1(reg)), \
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| D | sys_regs.c | 257 switch (p->Op1) { in access_gic_sgi()
317 u32 sr = sys_reg((u32)r->Op0, (u32)r->Op1, in trap_loregion()
986 sys_reg((u32)(x)->Op0, (u32)(x)->Op1, \
1095 u32 id = sys_reg((u32)r->Op0, (u32)r->Op1, in read_id_reg()
1352 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \
1809 { Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \
1811 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n }, \
1813 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n }, \
1815 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n }
1818 { Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_xvr, NULL, n }
[all …]
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| D | trace.h | 165 __field(u8, Op1)
177 __entry->Op1 = reg->Op1;
185 __entry->Op0, __entry->Op1, __entry->CRn,
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| D | sys_regs_generic_v8.c | 49 { Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b001),
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| /arch/arm/include/asm/vdso/ |
| D | cp15.h | 14 #define __ACCESS_CP15(CRn, Op1, CRm, Op2) \ argument
15 "mrc", "mcr", __stringify(p15, Op1, %0, CRn, CRm, Op2), u32
16 #define __ACCESS_CP15_64(Op1, CRm) \ argument
17 "mrrc", "mcrr", __stringify(p15, Op1, %Q0, %R0, CRm), u64
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