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Searched refs:PT_CPUID_REGS_NUM (Results 1 – 5 of 5) sorted by relevance

/arch/x86/include/asm/
Dintel_pt.h6 #define PT_CPUID_REGS_NUM 4 /* number of regsters (eax, ebx, ecx, edx) */ macro
/arch/x86/events/intel/
Dpt.h45 u32 caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES];
Dpt.c74 u32 c = caps[cd->leaf * PT_CPUID_REGS_NUM + cd->reg]; in intel_pt_validate_cap()
233 &pt_pmu.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM], in pt_pmu_hw_init()
234 &pt_pmu.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM], in pt_pmu_hw_init()
235 &pt_pmu.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM], in pt_pmu_hw_init()
236 &pt_pmu.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM]); in pt_pmu_hw_init()
/arch/x86/kvm/vmx/
Dvmx.h84 u32 caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES];
Dvmx.c7100 vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax; in update_intel_pt_cfg()
7101 vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx; in update_intel_pt_cfg()
7102 vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx; in update_intel_pt_cfg()
7103 vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx; in update_intel_pt_cfg()