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Searched refs:RC (Results 1 – 14 of 14) sorted by relevance

/arch/x86/crypto/
Dserpent-sse2-i586-asm_32.S29 #define RC %xmm2 macro
513 read_blocks(%eax, RA, RB, RC, RD, RT0, RT1, RE);
515 K(RA, RB, RC, RD, RE, 0);
516 S0(RA, RB, RC, RD, RE); LK(RC, RB, RD, RA, RE, 1);
517 S1(RC, RB, RD, RA, RE); LK(RE, RD, RA, RC, RB, 2);
518 S2(RE, RD, RA, RC, RB); LK(RB, RD, RE, RC, RA, 3);
519 S3(RB, RD, RE, RC, RA); LK(RC, RA, RD, RB, RE, 4);
520 S4(RC, RA, RD, RB, RE); LK(RA, RD, RB, RE, RC, 5);
521 S5(RA, RD, RB, RE, RC); LK(RC, RA, RD, RE, RB, 6);
522 S6(RC, RA, RD, RE, RB); LK(RD, RB, RA, RE, RC, 7);
[all …]
Dserpent-sse2-x86_64-asm_64.S636 K2(RA, RB, RC, RD, RE, 0);
637 S(S0, RA, RB, RC, RD, RE); LK2(RC, RB, RD, RA, RE, 1);
638 S(S1, RC, RB, RD, RA, RE); LK2(RE, RD, RA, RC, RB, 2);
639 S(S2, RE, RD, RA, RC, RB); LK2(RB, RD, RE, RC, RA, 3);
640 S(S3, RB, RD, RE, RC, RA); LK2(RC, RA, RD, RB, RE, 4);
641 S(S4, RC, RA, RD, RB, RE); LK2(RA, RD, RB, RE, RC, 5);
642 S(S5, RA, RD, RB, RE, RC); LK2(RC, RA, RD, RE, RB, 6);
643 S(S6, RC, RA, RD, RE, RB); LK2(RD, RB, RA, RE, RC, 7);
644 S(S7, RD, RB, RA, RE, RC); LK2(RC, RA, RE, RD, RB, 8);
645 S(S0, RC, RA, RE, RD, RB); LK2(RE, RA, RD, RC, RB, 9);
[all …]
Dserpent-avx-x86_64-asm_64.S571 K2(RA, RB, RC, RD, RE, 0);
572 S(S0, RA, RB, RC, RD, RE); LK2(RC, RB, RD, RA, RE, 1);
573 S(S1, RC, RB, RD, RA, RE); LK2(RE, RD, RA, RC, RB, 2);
574 S(S2, RE, RD, RA, RC, RB); LK2(RB, RD, RE, RC, RA, 3);
575 S(S3, RB, RD, RE, RC, RA); LK2(RC, RA, RD, RB, RE, 4);
576 S(S4, RC, RA, RD, RB, RE); LK2(RA, RD, RB, RE, RC, 5);
577 S(S5, RA, RD, RB, RE, RC); LK2(RC, RA, RD, RE, RB, 6);
578 S(S6, RC, RA, RD, RE, RB); LK2(RD, RB, RA, RE, RC, 7);
579 S(S7, RD, RB, RA, RE, RC); LK2(RC, RA, RE, RD, RB, 8);
580 S(S0, RC, RA, RE, RD, RB); LK2(RE, RA, RD, RC, RB, 9);
[all …]
Dserpent-avx2-asm_64.S577 K2(RA, RB, RC, RD, RE, 0);
578 S(S0, RA, RB, RC, RD, RE); LK2(RC, RB, RD, RA, RE, 1);
579 S(S1, RC, RB, RD, RA, RE); LK2(RE, RD, RA, RC, RB, 2);
580 S(S2, RE, RD, RA, RC, RB); LK2(RB, RD, RE, RC, RA, 3);
581 S(S3, RB, RD, RE, RC, RA); LK2(RC, RA, RD, RB, RE, 4);
582 S(S4, RC, RA, RD, RB, RE); LK2(RA, RD, RB, RE, RC, 5);
583 S(S5, RA, RD, RB, RE, RC); LK2(RC, RA, RD, RE, RB, 6);
584 S(S6, RC, RA, RD, RE, RB); LK2(RD, RB, RA, RE, RC, 7);
585 S(S7, RD, RB, RA, RE, RC); LK2(RC, RA, RE, RD, RB, 8);
586 S(S0, RC, RA, RE, RD, RB); LK2(RE, RA, RD, RC, RB, 9);
[all …]
Dtwofish-avx-x86_64-asm_64.S194 encrypt_round((2*n), RA, RB, RC, RD, preload_rgi, rotate_1l); \
195 encrypt_round(((2*n) + 1), RC, RD, RA, RB, preload_rgi, rotate_1l);
198 encrypt_round((2*n), RA, RB, RC, RD, preload_rgi, rotate_1l); \
199 encrypt_round(((2*n) + 1), RC, RD, RA, RB, dummy, dummy);
202 decrypt_round(((2*n) + 1), RC, RD, RA, RB, preload_rgi, rotate_1l); \
203 decrypt_round((2*n), RA, RB, RC, RD, preload_rgi, rotate_1l);
206 decrypt_round(((2*n) + 1), RC, RD, RA, RB, preload_rgi, rotate_1l); \
207 decrypt_round((2*n), RA, RB, RC, RD, dummy, dummy);
Dcast6-avx-x86_64-asm_64.S153 qop(RD, RC, 1); \
156 qop(RC, RB, 2); \
172 qop(RC, RB, 2); \
175 qop(RD, RC, 1);
Dsha1_avx2_x86_64_asm.S110 .set RC, REG_RC define
333 .set RD, RC
334 .set RC, RB define
/arch/powerpc/crypto/
Dsha1-powerpc-asm.S29 #define RC(t) ((((t)+2)%6)+7) macro
41 and r6,RB(t),RC(t); \
52 and r6,RB(t),RC(t); \
67 xor r6,RB(t),RC(t); \
77 xor r6,RB(t),RC(t); \
91 and r6,RB(t),RC(t); \
96 and r0,RC(t),RD(t); \
134 lwz RC(0),8(r3) /* C */
177 add RC(0),RC(80),r18
183 stw RC(0),8(r3)
/arch/m68k/include/asm/
Dtraps.h109 #define RC (0x2000) macro
/arch/arm64/boot/dts/arm/
Djuno-base.dtsi528 iommu-map-mask = <0x0>; /* RC has no means to output PCI RID */
/arch/m68k/kernel/
Dtraps.c992 if (ssw & RC) in bad_super_trap()
/arch/arm/boot/dts/
Dsun8i-a83t.dtsi176 * It is an internal RC-based oscillator.
Dsun9i-a80.dtsi162 * the clock switched to an internal 16M RC oscillator. Under
/arch/powerpc/xmon/
Dppc-opc.c559 #define RC RBOPT + 1 macro
565 #define RS RC + 1
3142 {"maddhd", VXA(4, 48), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
3144 {"maddhdu", VXA(4, 49), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},
3147 {"maddld", VXA(4, 51), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}},