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Searched refs:SPRN_L1CSR1 (Results 1 – 5 of 5) sorted by relevance

/arch/powerpc/kernel/
Dcpu_setup_fsl_booke.S20 mfspr r0, SPRN_L1CSR1
25 mtspr SPRN_L1CSR1, r0 /* Enable I-Cache */
Dmisc_32.S303 mfspr r3,SPRN_L1CSR1
305 mtspr SPRN_L1CSR1,r3
Dtraps.c635 mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI); in machine_check_e500mc()
636 while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI) in machine_check_e500mc()
/arch/powerpc/kvm/
De500_emulate.c253 case SPRN_L1CSR1: in kvmppc_core_emulate_mtspr_e500()
382 case SPRN_L1CSR1: in kvmppc_core_emulate_mfspr_e500()
/arch/powerpc/include/asm/
Dreg_booke.h174 #define SPRN_L1CSR1 0x3F3 /* L1 Cache Control and Status Register 1 */ macro