Searched refs:SPRN_L2CR (Results 1 – 5 of 5) sorted by relevance
| /arch/powerpc/platforms/powermac/ |
| D | cache.S | 99 mfspr r5,SPRN_L2CR
105 1: mtspr SPRN_L2CR,r3
139 1: mtspr SPRN_L2CR,r5
151 mtspr SPRN_L2CR,r4
156 1: mfspr r3,SPRN_L2CR
163 mtspr SPRN_L2CR,r4
270 mfspr r3,SPRN_L2CR
277 1: mtspr SPRN_L2CR,r0 /* lock the L2 cache */
289 mtspr SPRN_L2CR,r0 /* set the hardware flush bit */
290 3: mfspr r0,SPRN_L2CR /* wait for it to go to 0 */
[all …]
|
| /arch/powerpc/kernel/ |
| D | l2cr_6xx.S | 123 mfspr r4,SPRN_L2CR
197 mtspr SPRN_L2CR,r3
210 mtspr SPRN_L2CR,r3
217 10: mfspr r3,SPRN_L2CR
224 3: mfspr r3,SPRN_L2CR
230 mtspr SPRN_L2CR,r3
239 mtspr SPRN_L2CR,r3
270 mfspr r3,SPRN_L2CR
|
| D | cpu_setup_6xx.S | 263 mfspr r3,SPRN_L2CR
|
| /arch/powerpc/kvm/ |
| D | book3s_emulate.c | 825 case SPRN_L2CR: in kvmppc_core_emulate_mtspr_pr()
989 case SPRN_L2CR: in kvmppc_core_emulate_mfspr_pr()
|
| /arch/powerpc/include/asm/ |
| D | reg.h | 660 #define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Register */ macro
|