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Searched refs:SRCC0 (Results 1 – 2 of 2) sorted by relevance

/arch/sh/kernel/cpu/sh2a/
Dsetup-sh7264.c42 SRCC0, SRCC1, DCOMU, OFFI, IFEI, enumerator
165 INTC_IRQ(SRCC0, 299), INTC_IRQ(SRCC0, 300),
166 INTC_IRQ(SRCC0, 301), INTC_IRQ(SRCC0, 302),
167 INTC_IRQ(SRCC0, 303),
213 { 0xfffe0c20, 0, 16, 4, /* IPR22 */ { SRCC0, SRCC1, 0, DCOMU } },
Dsetup-sh7269.c46 SRCC0, SRCC1, SRCC2, enumerator
182 INTC_IRQ(SRCC0, 341), INTC_IRQ(SRCC0, 342),
183 INTC_IRQ(SRCC0, 343), INTC_IRQ(SRCC0, 344),
184 INTC_IRQ(SRCC0, 345),
235 { 0xfffe0c28, 0, 16, 4, /* IPR26 */ { SRCC0, SRCC1, SRCC2, 0 } },