1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Macros for accessing system registers with older binutils. 4 * 5 * Copyright (C) 2014 ARM Ltd. 6 * Author: Catalin Marinas <catalin.marinas@arm.com> 7 */ 8 9 #ifndef __ASM_SYSREG_H 10 #define __ASM_SYSREG_H 11 12 #include <linux/bits.h> 13 #include <linux/stringify.h> 14 15 /* 16 * ARMv8 ARM reserves the following encoding for system registers: 17 * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview", 18 * C5.2, version:ARM DDI 0487A.f) 19 * [20-19] : Op0 20 * [18-16] : Op1 21 * [15-12] : CRn 22 * [11-8] : CRm 23 * [7-5] : Op2 24 */ 25 #define Op0_shift 19 26 #define Op0_mask 0x3 27 #define Op1_shift 16 28 #define Op1_mask 0x7 29 #define CRn_shift 12 30 #define CRn_mask 0xf 31 #define CRm_shift 8 32 #define CRm_mask 0xf 33 #define Op2_shift 5 34 #define Op2_mask 0x7 35 36 #define sys_reg(op0, op1, crn, crm, op2) \ 37 (((op0) << Op0_shift) | ((op1) << Op1_shift) | \ 38 ((crn) << CRn_shift) | ((crm) << CRm_shift) | \ 39 ((op2) << Op2_shift)) 40 41 #define sys_insn sys_reg 42 43 #define sys_reg_Op0(id) (((id) >> Op0_shift) & Op0_mask) 44 #define sys_reg_Op1(id) (((id) >> Op1_shift) & Op1_mask) 45 #define sys_reg_CRn(id) (((id) >> CRn_shift) & CRn_mask) 46 #define sys_reg_CRm(id) (((id) >> CRm_shift) & CRm_mask) 47 #define sys_reg_Op2(id) (((id) >> Op2_shift) & Op2_mask) 48 49 #ifndef CONFIG_BROKEN_GAS_INST 50 51 #ifdef __ASSEMBLY__ 52 // The space separator is omitted so that __emit_inst(x) can be parsed as 53 // either an assembler directive or an assembler macro argument. 54 #define __emit_inst(x) .inst(x) 55 #else 56 #define __emit_inst(x) ".inst " __stringify((x)) "\n\t" 57 #endif 58 59 #else /* CONFIG_BROKEN_GAS_INST */ 60 61 #ifndef CONFIG_CPU_BIG_ENDIAN 62 #define __INSTR_BSWAP(x) (x) 63 #else /* CONFIG_CPU_BIG_ENDIAN */ 64 #define __INSTR_BSWAP(x) ((((x) << 24) & 0xff000000) | \ 65 (((x) << 8) & 0x00ff0000) | \ 66 (((x) >> 8) & 0x0000ff00) | \ 67 (((x) >> 24) & 0x000000ff)) 68 #endif /* CONFIG_CPU_BIG_ENDIAN */ 69 70 #ifdef __ASSEMBLY__ 71 #define __emit_inst(x) .long __INSTR_BSWAP(x) 72 #else /* __ASSEMBLY__ */ 73 #define __emit_inst(x) ".long " __stringify(__INSTR_BSWAP(x)) "\n\t" 74 #endif /* __ASSEMBLY__ */ 75 76 #endif /* CONFIG_BROKEN_GAS_INST */ 77 78 /* 79 * Instructions for modifying PSTATE fields. 80 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints, 81 * barriers and CLREX, and PSTATE access", ARM DDI 0487 C.a, system instructions 82 * for accessing PSTATE fields have the following encoding: 83 * Op0 = 0, CRn = 4 84 * Op1, Op2 encodes the PSTATE field modified and defines the constraints. 85 * CRm = Imm4 for the instruction. 86 * Rt = 0x1f 87 */ 88 #define pstate_field(op1, op2) ((op1) << Op1_shift | (op2) << Op2_shift) 89 #define PSTATE_Imm_shift CRm_shift 90 91 #define PSTATE_PAN pstate_field(0, 4) 92 #define PSTATE_UAO pstate_field(0, 3) 93 #define PSTATE_SSBS pstate_field(3, 1) 94 95 #define SET_PSTATE_PAN(x) __emit_inst(0xd500401f | PSTATE_PAN | ((!!x) << PSTATE_Imm_shift)) 96 #define SET_PSTATE_UAO(x) __emit_inst(0xd500401f | PSTATE_UAO | ((!!x) << PSTATE_Imm_shift)) 97 #define SET_PSTATE_SSBS(x) __emit_inst(0xd500401f | PSTATE_SSBS | ((!!x) << PSTATE_Imm_shift)) 98 99 #define __SYS_BARRIER_INSN(CRm, op2, Rt) \ 100 __emit_inst(0xd5000000 | sys_insn(0, 3, 3, (CRm), (op2)) | ((Rt) & 0x1f)) 101 102 #define SB_BARRIER_INSN __SYS_BARRIER_INSN(0, 7, 31) 103 104 #define SYS_DC_ISW sys_insn(1, 0, 7, 6, 2) 105 #define SYS_DC_IGSW sys_insn(1, 0, 7, 6, 4) 106 #define SYS_DC_IGDSW sys_insn(1, 0, 7, 6, 6) 107 #define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2) 108 #define SYS_DC_CGSW sys_insn(1, 0, 7, 10, 4) 109 #define SYS_DC_CGDSW sys_insn(1, 0, 7, 10, 6) 110 #define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2) 111 #define SYS_DC_CIGSW sys_insn(1, 0, 7, 14, 4) 112 #define SYS_DC_CIGDSW sys_insn(1, 0, 7, 14, 6) 113 114 #define SYS_OSDTRRX_EL1 sys_reg(2, 0, 0, 0, 2) 115 #define SYS_MDCCINT_EL1 sys_reg(2, 0, 0, 2, 0) 116 #define SYS_MDSCR_EL1 sys_reg(2, 0, 0, 2, 2) 117 #define SYS_OSDTRTX_EL1 sys_reg(2, 0, 0, 3, 2) 118 #define SYS_OSECCR_EL1 sys_reg(2, 0, 0, 6, 2) 119 #define SYS_DBGBVRn_EL1(n) sys_reg(2, 0, 0, n, 4) 120 #define SYS_DBGBCRn_EL1(n) sys_reg(2, 0, 0, n, 5) 121 #define SYS_DBGWVRn_EL1(n) sys_reg(2, 0, 0, n, 6) 122 #define SYS_DBGWCRn_EL1(n) sys_reg(2, 0, 0, n, 7) 123 #define SYS_MDRAR_EL1 sys_reg(2, 0, 1, 0, 0) 124 #define SYS_OSLAR_EL1 sys_reg(2, 0, 1, 0, 4) 125 #define SYS_OSLSR_EL1 sys_reg(2, 0, 1, 1, 4) 126 #define SYS_OSDLR_EL1 sys_reg(2, 0, 1, 3, 4) 127 #define SYS_DBGPRCR_EL1 sys_reg(2, 0, 1, 4, 4) 128 #define SYS_DBGCLAIMSET_EL1 sys_reg(2, 0, 7, 8, 6) 129 #define SYS_DBGCLAIMCLR_EL1 sys_reg(2, 0, 7, 9, 6) 130 #define SYS_DBGAUTHSTATUS_EL1 sys_reg(2, 0, 7, 14, 6) 131 #define SYS_MDCCSR_EL0 sys_reg(2, 3, 0, 1, 0) 132 #define SYS_DBGDTR_EL0 sys_reg(2, 3, 0, 4, 0) 133 #define SYS_DBGDTRRX_EL0 sys_reg(2, 3, 0, 5, 0) 134 #define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0) 135 #define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0) 136 137 #define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0) 138 #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5) 139 #define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6) 140 141 #define SYS_ID_PFR0_EL1 sys_reg(3, 0, 0, 1, 0) 142 #define SYS_ID_PFR1_EL1 sys_reg(3, 0, 0, 1, 1) 143 #define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1, 2) 144 #define SYS_ID_AFR0_EL1 sys_reg(3, 0, 0, 1, 3) 145 #define SYS_ID_MMFR0_EL1 sys_reg(3, 0, 0, 1, 4) 146 #define SYS_ID_MMFR1_EL1 sys_reg(3, 0, 0, 1, 5) 147 #define SYS_ID_MMFR2_EL1 sys_reg(3, 0, 0, 1, 6) 148 #define SYS_ID_MMFR3_EL1 sys_reg(3, 0, 0, 1, 7) 149 150 #define SYS_ID_ISAR0_EL1 sys_reg(3, 0, 0, 2, 0) 151 #define SYS_ID_ISAR1_EL1 sys_reg(3, 0, 0, 2, 1) 152 #define SYS_ID_ISAR2_EL1 sys_reg(3, 0, 0, 2, 2) 153 #define SYS_ID_ISAR3_EL1 sys_reg(3, 0, 0, 2, 3) 154 #define SYS_ID_ISAR4_EL1 sys_reg(3, 0, 0, 2, 4) 155 #define SYS_ID_ISAR5_EL1 sys_reg(3, 0, 0, 2, 5) 156 #define SYS_ID_MMFR4_EL1 sys_reg(3, 0, 0, 2, 6) 157 158 #define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0) 159 #define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1) 160 #define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2) 161 162 #define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4, 0) 163 #define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4, 1) 164 #define SYS_ID_AA64ZFR0_EL1 sys_reg(3, 0, 0, 4, 4) 165 166 #define SYS_ID_AA64DFR0_EL1 sys_reg(3, 0, 0, 5, 0) 167 #define SYS_ID_AA64DFR1_EL1 sys_reg(3, 0, 0, 5, 1) 168 169 #define SYS_ID_AA64AFR0_EL1 sys_reg(3, 0, 0, 5, 4) 170 #define SYS_ID_AA64AFR1_EL1 sys_reg(3, 0, 0, 5, 5) 171 172 #define SYS_ID_AA64ISAR0_EL1 sys_reg(3, 0, 0, 6, 0) 173 #define SYS_ID_AA64ISAR1_EL1 sys_reg(3, 0, 0, 6, 1) 174 #define SYS_ID_AA64ISAR2_EL1 sys_reg(3, 0, 0, 6, 2) 175 176 #define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0) 177 #define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1) 178 #define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7, 2) 179 180 #define SYS_SCTLR_EL1 sys_reg(3, 0, 1, 0, 0) 181 #define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1) 182 #define SYS_CPACR_EL1 sys_reg(3, 0, 1, 0, 2) 183 184 #define SYS_ZCR_EL1 sys_reg(3, 0, 1, 2, 0) 185 186 #define SYS_TTBR0_EL1 sys_reg(3, 0, 2, 0, 0) 187 #define SYS_TTBR1_EL1 sys_reg(3, 0, 2, 0, 1) 188 #define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2) 189 190 #define SYS_APIAKEYLO_EL1 sys_reg(3, 0, 2, 1, 0) 191 #define SYS_APIAKEYHI_EL1 sys_reg(3, 0, 2, 1, 1) 192 #define SYS_APIBKEYLO_EL1 sys_reg(3, 0, 2, 1, 2) 193 #define SYS_APIBKEYHI_EL1 sys_reg(3, 0, 2, 1, 3) 194 195 #define SYS_APDAKEYLO_EL1 sys_reg(3, 0, 2, 2, 0) 196 #define SYS_APDAKEYHI_EL1 sys_reg(3, 0, 2, 2, 1) 197 #define SYS_APDBKEYLO_EL1 sys_reg(3, 0, 2, 2, 2) 198 #define SYS_APDBKEYHI_EL1 sys_reg(3, 0, 2, 2, 3) 199 200 #define SYS_APGAKEYLO_EL1 sys_reg(3, 0, 2, 3, 0) 201 #define SYS_APGAKEYHI_EL1 sys_reg(3, 0, 2, 3, 1) 202 203 #define SYS_SPSR_EL1 sys_reg(3, 0, 4, 0, 0) 204 #define SYS_ELR_EL1 sys_reg(3, 0, 4, 0, 1) 205 206 #define SYS_ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0) 207 208 #define SYS_AFSR0_EL1 sys_reg(3, 0, 5, 1, 0) 209 #define SYS_AFSR1_EL1 sys_reg(3, 0, 5, 1, 1) 210 #define SYS_ESR_EL1 sys_reg(3, 0, 5, 2, 0) 211 212 #define SYS_ERRIDR_EL1 sys_reg(3, 0, 5, 3, 0) 213 #define SYS_ERRSELR_EL1 sys_reg(3, 0, 5, 3, 1) 214 #define SYS_ERXFR_EL1 sys_reg(3, 0, 5, 4, 0) 215 #define SYS_ERXCTLR_EL1 sys_reg(3, 0, 5, 4, 1) 216 #define SYS_ERXSTATUS_EL1 sys_reg(3, 0, 5, 4, 2) 217 #define SYS_ERXADDR_EL1 sys_reg(3, 0, 5, 4, 3) 218 #define SYS_ERXMISC0_EL1 sys_reg(3, 0, 5, 5, 0) 219 #define SYS_ERXMISC1_EL1 sys_reg(3, 0, 5, 5, 1) 220 221 #define SYS_FAR_EL1 sys_reg(3, 0, 6, 0, 0) 222 #define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0) 223 224 #define SYS_PAR_EL1_F BIT(0) 225 #define SYS_PAR_EL1_FST GENMASK(6, 1) 226 227 /*** Statistical Profiling Extension ***/ 228 /* ID registers */ 229 #define SYS_PMSIDR_EL1 sys_reg(3, 0, 9, 9, 7) 230 #define SYS_PMSIDR_EL1_FE_SHIFT 0 231 #define SYS_PMSIDR_EL1_FT_SHIFT 1 232 #define SYS_PMSIDR_EL1_FL_SHIFT 2 233 #define SYS_PMSIDR_EL1_ARCHINST_SHIFT 3 234 #define SYS_PMSIDR_EL1_LDS_SHIFT 4 235 #define SYS_PMSIDR_EL1_ERND_SHIFT 5 236 #define SYS_PMSIDR_EL1_INTERVAL_SHIFT 8 237 #define SYS_PMSIDR_EL1_INTERVAL_MASK 0xfUL 238 #define SYS_PMSIDR_EL1_MAXSIZE_SHIFT 12 239 #define SYS_PMSIDR_EL1_MAXSIZE_MASK 0xfUL 240 #define SYS_PMSIDR_EL1_COUNTSIZE_SHIFT 16 241 #define SYS_PMSIDR_EL1_COUNTSIZE_MASK 0xfUL 242 243 #define SYS_PMBIDR_EL1 sys_reg(3, 0, 9, 10, 7) 244 #define SYS_PMBIDR_EL1_ALIGN_SHIFT 0 245 #define SYS_PMBIDR_EL1_ALIGN_MASK 0xfU 246 #define SYS_PMBIDR_EL1_P_SHIFT 4 247 #define SYS_PMBIDR_EL1_F_SHIFT 5 248 249 /* Sampling controls */ 250 #define SYS_PMSCR_EL1 sys_reg(3, 0, 9, 9, 0) 251 #define SYS_PMSCR_EL1_E0SPE_SHIFT 0 252 #define SYS_PMSCR_EL1_E1SPE_SHIFT 1 253 #define SYS_PMSCR_EL1_CX_SHIFT 3 254 #define SYS_PMSCR_EL1_PA_SHIFT 4 255 #define SYS_PMSCR_EL1_TS_SHIFT 5 256 #define SYS_PMSCR_EL1_PCT_SHIFT 6 257 258 #define SYS_PMSCR_EL2 sys_reg(3, 4, 9, 9, 0) 259 #define SYS_PMSCR_EL2_E0HSPE_SHIFT 0 260 #define SYS_PMSCR_EL2_E2SPE_SHIFT 1 261 #define SYS_PMSCR_EL2_CX_SHIFT 3 262 #define SYS_PMSCR_EL2_PA_SHIFT 4 263 #define SYS_PMSCR_EL2_TS_SHIFT 5 264 #define SYS_PMSCR_EL2_PCT_SHIFT 6 265 266 #define SYS_PMSICR_EL1 sys_reg(3, 0, 9, 9, 2) 267 268 #define SYS_PMSIRR_EL1 sys_reg(3, 0, 9, 9, 3) 269 #define SYS_PMSIRR_EL1_RND_SHIFT 0 270 #define SYS_PMSIRR_EL1_INTERVAL_SHIFT 8 271 #define SYS_PMSIRR_EL1_INTERVAL_MASK 0xffffffUL 272 273 /* Filtering controls */ 274 #define SYS_PMSFCR_EL1 sys_reg(3, 0, 9, 9, 4) 275 #define SYS_PMSFCR_EL1_FE_SHIFT 0 276 #define SYS_PMSFCR_EL1_FT_SHIFT 1 277 #define SYS_PMSFCR_EL1_FL_SHIFT 2 278 #define SYS_PMSFCR_EL1_B_SHIFT 16 279 #define SYS_PMSFCR_EL1_LD_SHIFT 17 280 #define SYS_PMSFCR_EL1_ST_SHIFT 18 281 282 #define SYS_PMSEVFR_EL1 sys_reg(3, 0, 9, 9, 5) 283 #define SYS_PMSEVFR_EL1_RES0 0x0000ffff00ff0f55UL 284 285 #define SYS_PMSLATFR_EL1 sys_reg(3, 0, 9, 9, 6) 286 #define SYS_PMSLATFR_EL1_MINLAT_SHIFT 0 287 288 /* Buffer controls */ 289 #define SYS_PMBLIMITR_EL1 sys_reg(3, 0, 9, 10, 0) 290 #define SYS_PMBLIMITR_EL1_E_SHIFT 0 291 #define SYS_PMBLIMITR_EL1_FM_SHIFT 1 292 #define SYS_PMBLIMITR_EL1_FM_MASK 0x3UL 293 #define SYS_PMBLIMITR_EL1_FM_STOP_IRQ (0 << SYS_PMBLIMITR_EL1_FM_SHIFT) 294 295 #define SYS_PMBPTR_EL1 sys_reg(3, 0, 9, 10, 1) 296 297 /* Buffer error reporting */ 298 #define SYS_PMBSR_EL1 sys_reg(3, 0, 9, 10, 3) 299 #define SYS_PMBSR_EL1_COLL_SHIFT 16 300 #define SYS_PMBSR_EL1_S_SHIFT 17 301 #define SYS_PMBSR_EL1_EA_SHIFT 18 302 #define SYS_PMBSR_EL1_DL_SHIFT 19 303 #define SYS_PMBSR_EL1_EC_SHIFT 26 304 #define SYS_PMBSR_EL1_EC_MASK 0x3fUL 305 306 #define SYS_PMBSR_EL1_EC_BUF (0x0UL << SYS_PMBSR_EL1_EC_SHIFT) 307 #define SYS_PMBSR_EL1_EC_FAULT_S1 (0x24UL << SYS_PMBSR_EL1_EC_SHIFT) 308 #define SYS_PMBSR_EL1_EC_FAULT_S2 (0x25UL << SYS_PMBSR_EL1_EC_SHIFT) 309 310 #define SYS_PMBSR_EL1_FAULT_FSC_SHIFT 0 311 #define SYS_PMBSR_EL1_FAULT_FSC_MASK 0x3fUL 312 313 #define SYS_PMBSR_EL1_BUF_BSC_SHIFT 0 314 #define SYS_PMBSR_EL1_BUF_BSC_MASK 0x3fUL 315 316 #define SYS_PMBSR_EL1_BUF_BSC_FULL (0x1UL << SYS_PMBSR_EL1_BUF_BSC_SHIFT) 317 318 /*** End of Statistical Profiling Extension ***/ 319 320 #define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1) 321 #define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2) 322 323 #define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0) 324 #define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0) 325 326 #define SYS_LORSA_EL1 sys_reg(3, 0, 10, 4, 0) 327 #define SYS_LOREA_EL1 sys_reg(3, 0, 10, 4, 1) 328 #define SYS_LORN_EL1 sys_reg(3, 0, 10, 4, 2) 329 #define SYS_LORC_EL1 sys_reg(3, 0, 10, 4, 3) 330 #define SYS_LORID_EL1 sys_reg(3, 0, 10, 4, 7) 331 332 #define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0) 333 #define SYS_DISR_EL1 sys_reg(3, 0, 12, 1, 1) 334 335 #define SYS_ICC_IAR0_EL1 sys_reg(3, 0, 12, 8, 0) 336 #define SYS_ICC_EOIR0_EL1 sys_reg(3, 0, 12, 8, 1) 337 #define SYS_ICC_HPPIR0_EL1 sys_reg(3, 0, 12, 8, 2) 338 #define SYS_ICC_BPR0_EL1 sys_reg(3, 0, 12, 8, 3) 339 #define SYS_ICC_AP0Rn_EL1(n) sys_reg(3, 0, 12, 8, 4 | n) 340 #define SYS_ICC_AP0R0_EL1 SYS_ICC_AP0Rn_EL1(0) 341 #define SYS_ICC_AP0R1_EL1 SYS_ICC_AP0Rn_EL1(1) 342 #define SYS_ICC_AP0R2_EL1 SYS_ICC_AP0Rn_EL1(2) 343 #define SYS_ICC_AP0R3_EL1 SYS_ICC_AP0Rn_EL1(3) 344 #define SYS_ICC_AP1Rn_EL1(n) sys_reg(3, 0, 12, 9, n) 345 #define SYS_ICC_AP1R0_EL1 SYS_ICC_AP1Rn_EL1(0) 346 #define SYS_ICC_AP1R1_EL1 SYS_ICC_AP1Rn_EL1(1) 347 #define SYS_ICC_AP1R2_EL1 SYS_ICC_AP1Rn_EL1(2) 348 #define SYS_ICC_AP1R3_EL1 SYS_ICC_AP1Rn_EL1(3) 349 #define SYS_ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1) 350 #define SYS_ICC_RPR_EL1 sys_reg(3, 0, 12, 11, 3) 351 #define SYS_ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5) 352 #define SYS_ICC_ASGI1R_EL1 sys_reg(3, 0, 12, 11, 6) 353 #define SYS_ICC_SGI0R_EL1 sys_reg(3, 0, 12, 11, 7) 354 #define SYS_ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0) 355 #define SYS_ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1) 356 #define SYS_ICC_HPPIR1_EL1 sys_reg(3, 0, 12, 12, 2) 357 #define SYS_ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3) 358 #define SYS_ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4) 359 #define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5) 360 #define SYS_ICC_IGRPEN0_EL1 sys_reg(3, 0, 12, 12, 6) 361 #define SYS_ICC_IGRPEN1_EL1 sys_reg(3, 0, 12, 12, 7) 362 363 #define SYS_CONTEXTIDR_EL1 sys_reg(3, 0, 13, 0, 1) 364 #define SYS_TPIDR_EL1 sys_reg(3, 0, 13, 0, 4) 365 366 #define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0) 367 368 #define SYS_CCSIDR_EL1 sys_reg(3, 1, 0, 0, 0) 369 #define SYS_CLIDR_EL1 sys_reg(3, 1, 0, 0, 1) 370 #define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7) 371 372 #define SYS_CSSELR_EL1 sys_reg(3, 2, 0, 0, 0) 373 374 #define SYS_CTR_EL0 sys_reg(3, 3, 0, 0, 1) 375 #define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7) 376 377 #define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0) 378 #define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1) 379 #define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2) 380 #define SYS_PMOVSCLR_EL0 sys_reg(3, 3, 9, 12, 3) 381 #define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4) 382 #define SYS_PMSELR_EL0 sys_reg(3, 3, 9, 12, 5) 383 #define SYS_PMCEID0_EL0 sys_reg(3, 3, 9, 12, 6) 384 #define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7) 385 #define SYS_PMCCNTR_EL0 sys_reg(3, 3, 9, 13, 0) 386 #define SYS_PMXEVTYPER_EL0 sys_reg(3, 3, 9, 13, 1) 387 #define SYS_PMXEVCNTR_EL0 sys_reg(3, 3, 9, 13, 2) 388 #define SYS_PMUSERENR_EL0 sys_reg(3, 3, 9, 14, 0) 389 #define SYS_PMOVSSET_EL0 sys_reg(3, 3, 9, 14, 3) 390 391 #define SYS_TPIDR_EL0 sys_reg(3, 3, 13, 0, 2) 392 #define SYS_TPIDRRO_EL0 sys_reg(3, 3, 13, 0, 3) 393 394 /* Definitions for system register interface to AMU for ARMv8.4 onwards */ 395 #define SYS_AM_EL0(crm, op2) sys_reg(3, 3, 13, (crm), (op2)) 396 #define SYS_AMCR_EL0 SYS_AM_EL0(2, 0) 397 #define SYS_AMCFGR_EL0 SYS_AM_EL0(2, 1) 398 #define SYS_AMCGCR_EL0 SYS_AM_EL0(2, 2) 399 #define SYS_AMUSERENR_EL0 SYS_AM_EL0(2, 3) 400 #define SYS_AMCNTENCLR0_EL0 SYS_AM_EL0(2, 4) 401 #define SYS_AMCNTENSET0_EL0 SYS_AM_EL0(2, 5) 402 #define SYS_AMCNTENCLR1_EL0 SYS_AM_EL0(3, 0) 403 #define SYS_AMCNTENSET1_EL0 SYS_AM_EL0(3, 1) 404 405 /* 406 * Group 0 of activity monitors (architected): 407 * op0 op1 CRn CRm op2 408 * Counter: 11 011 1101 010:n<3> n<2:0> 409 * Type: 11 011 1101 011:n<3> n<2:0> 410 * n: 0-15 411 * 412 * Group 1 of activity monitors (auxiliary): 413 * op0 op1 CRn CRm op2 414 * Counter: 11 011 1101 110:n<3> n<2:0> 415 * Type: 11 011 1101 111:n<3> n<2:0> 416 * n: 0-15 417 */ 418 419 #define SYS_AMEVCNTR0_EL0(n) SYS_AM_EL0(4 + ((n) >> 3), (n) & 7) 420 #define SYS_AMEVTYPE0_EL0(n) SYS_AM_EL0(6 + ((n) >> 3), (n) & 7) 421 #define SYS_AMEVCNTR1_EL0(n) SYS_AM_EL0(12 + ((n) >> 3), (n) & 7) 422 #define SYS_AMEVTYPE1_EL0(n) SYS_AM_EL0(14 + ((n) >> 3), (n) & 7) 423 424 /* AMU v1: Fixed (architecturally defined) activity monitors */ 425 #define SYS_AMEVCNTR0_CORE_EL0 SYS_AMEVCNTR0_EL0(0) 426 #define SYS_AMEVCNTR0_CONST_EL0 SYS_AMEVCNTR0_EL0(1) 427 #define SYS_AMEVCNTR0_INST_RET_EL0 SYS_AMEVCNTR0_EL0(2) 428 #define SYS_AMEVCNTR0_MEM_STALL SYS_AMEVCNTR0_EL0(3) 429 430 #define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0) 431 432 #define SYS_CNTP_TVAL_EL0 sys_reg(3, 3, 14, 2, 0) 433 #define SYS_CNTP_CTL_EL0 sys_reg(3, 3, 14, 2, 1) 434 #define SYS_CNTP_CVAL_EL0 sys_reg(3, 3, 14, 2, 2) 435 436 #define SYS_CNTV_CTL_EL0 sys_reg(3, 3, 14, 3, 1) 437 #define SYS_CNTV_CVAL_EL0 sys_reg(3, 3, 14, 3, 2) 438 439 #define SYS_AARCH32_CNTP_TVAL sys_reg(0, 0, 14, 2, 0) 440 #define SYS_AARCH32_CNTP_CTL sys_reg(0, 0, 14, 2, 1) 441 #define SYS_AARCH32_CNTP_CVAL sys_reg(0, 2, 0, 14, 0) 442 443 #define __PMEV_op2(n) ((n) & 0x7) 444 #define __CNTR_CRm(n) (0x8 | (((n) >> 3) & 0x3)) 445 #define SYS_PMEVCNTRn_EL0(n) sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n)) 446 #define __TYPER_CRm(n) (0xc | (((n) >> 3) & 0x3)) 447 #define SYS_PMEVTYPERn_EL0(n) sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n)) 448 449 #define SYS_PMCCFILTR_EL0 sys_reg(3, 3, 14, 15, 7) 450 451 #define SYS_ZCR_EL2 sys_reg(3, 4, 1, 2, 0) 452 #define SYS_DACR32_EL2 sys_reg(3, 4, 3, 0, 0) 453 #define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0) 454 #define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1) 455 #define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1) 456 #define SYS_ESR_EL2 sys_reg(3, 4, 5, 2, 0) 457 #define SYS_VSESR_EL2 sys_reg(3, 4, 5, 2, 3) 458 #define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0) 459 #define SYS_FAR_EL2 sys_reg(3, 4, 6, 0, 0) 460 461 #define SYS_VDISR_EL2 sys_reg(3, 4, 12, 1, 1) 462 #define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x) 463 #define SYS_ICH_AP0R0_EL2 __SYS__AP0Rx_EL2(0) 464 #define SYS_ICH_AP0R1_EL2 __SYS__AP0Rx_EL2(1) 465 #define SYS_ICH_AP0R2_EL2 __SYS__AP0Rx_EL2(2) 466 #define SYS_ICH_AP0R3_EL2 __SYS__AP0Rx_EL2(3) 467 468 #define __SYS__AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x) 469 #define SYS_ICH_AP1R0_EL2 __SYS__AP1Rx_EL2(0) 470 #define SYS_ICH_AP1R1_EL2 __SYS__AP1Rx_EL2(1) 471 #define SYS_ICH_AP1R2_EL2 __SYS__AP1Rx_EL2(2) 472 #define SYS_ICH_AP1R3_EL2 __SYS__AP1Rx_EL2(3) 473 474 #define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4) 475 #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5) 476 #define SYS_ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0) 477 #define SYS_ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1) 478 #define SYS_ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2) 479 #define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3) 480 #define SYS_ICH_ELRSR_EL2 sys_reg(3, 4, 12, 11, 5) 481 #define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7) 482 483 #define __SYS__LR0_EL2(x) sys_reg(3, 4, 12, 12, x) 484 #define SYS_ICH_LR0_EL2 __SYS__LR0_EL2(0) 485 #define SYS_ICH_LR1_EL2 __SYS__LR0_EL2(1) 486 #define SYS_ICH_LR2_EL2 __SYS__LR0_EL2(2) 487 #define SYS_ICH_LR3_EL2 __SYS__LR0_EL2(3) 488 #define SYS_ICH_LR4_EL2 __SYS__LR0_EL2(4) 489 #define SYS_ICH_LR5_EL2 __SYS__LR0_EL2(5) 490 #define SYS_ICH_LR6_EL2 __SYS__LR0_EL2(6) 491 #define SYS_ICH_LR7_EL2 __SYS__LR0_EL2(7) 492 493 #define __SYS__LR8_EL2(x) sys_reg(3, 4, 12, 13, x) 494 #define SYS_ICH_LR8_EL2 __SYS__LR8_EL2(0) 495 #define SYS_ICH_LR9_EL2 __SYS__LR8_EL2(1) 496 #define SYS_ICH_LR10_EL2 __SYS__LR8_EL2(2) 497 #define SYS_ICH_LR11_EL2 __SYS__LR8_EL2(3) 498 #define SYS_ICH_LR12_EL2 __SYS__LR8_EL2(4) 499 #define SYS_ICH_LR13_EL2 __SYS__LR8_EL2(5) 500 #define SYS_ICH_LR14_EL2 __SYS__LR8_EL2(6) 501 #define SYS_ICH_LR15_EL2 __SYS__LR8_EL2(7) 502 503 /* VHE encodings for architectural EL0/1 system registers */ 504 #define SYS_SCTLR_EL12 sys_reg(3, 5, 1, 0, 0) 505 #define SYS_CPACR_EL12 sys_reg(3, 5, 1, 0, 2) 506 #define SYS_ZCR_EL12 sys_reg(3, 5, 1, 2, 0) 507 #define SYS_TTBR0_EL12 sys_reg(3, 5, 2, 0, 0) 508 #define SYS_TTBR1_EL12 sys_reg(3, 5, 2, 0, 1) 509 #define SYS_TCR_EL12 sys_reg(3, 5, 2, 0, 2) 510 #define SYS_SPSR_EL12 sys_reg(3, 5, 4, 0, 0) 511 #define SYS_ELR_EL12 sys_reg(3, 5, 4, 0, 1) 512 #define SYS_AFSR0_EL12 sys_reg(3, 5, 5, 1, 0) 513 #define SYS_AFSR1_EL12 sys_reg(3, 5, 5, 1, 1) 514 #define SYS_ESR_EL12 sys_reg(3, 5, 5, 2, 0) 515 #define SYS_FAR_EL12 sys_reg(3, 5, 6, 0, 0) 516 #define SYS_MAIR_EL12 sys_reg(3, 5, 10, 2, 0) 517 #define SYS_AMAIR_EL12 sys_reg(3, 5, 10, 3, 0) 518 #define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0) 519 #define SYS_CONTEXTIDR_EL12 sys_reg(3, 5, 13, 0, 1) 520 #define SYS_CNTKCTL_EL12 sys_reg(3, 5, 14, 1, 0) 521 #define SYS_CNTP_TVAL_EL02 sys_reg(3, 5, 14, 2, 0) 522 #define SYS_CNTP_CTL_EL02 sys_reg(3, 5, 14, 2, 1) 523 #define SYS_CNTP_CVAL_EL02 sys_reg(3, 5, 14, 2, 2) 524 #define SYS_CNTV_TVAL_EL02 sys_reg(3, 5, 14, 3, 0) 525 #define SYS_CNTV_CTL_EL02 sys_reg(3, 5, 14, 3, 1) 526 #define SYS_CNTV_CVAL_EL02 sys_reg(3, 5, 14, 3, 2) 527 528 /* Common SCTLR_ELx flags. */ 529 #define SCTLR_ELx_DSSBS (BIT(44)) 530 #define SCTLR_ELx_ENIA (BIT(31)) 531 #define SCTLR_ELx_ENIB (BIT(30)) 532 #define SCTLR_ELx_ENDA (BIT(27)) 533 #define SCTLR_ELx_EE (BIT(25)) 534 #define SCTLR_ELx_IESB (BIT(21)) 535 #define SCTLR_ELx_WXN (BIT(19)) 536 #define SCTLR_ELx_ENDB (BIT(13)) 537 #define SCTLR_ELx_I (BIT(12)) 538 #define SCTLR_ELx_SA (BIT(3)) 539 #define SCTLR_ELx_C (BIT(2)) 540 #define SCTLR_ELx_A (BIT(1)) 541 #define SCTLR_ELx_M (BIT(0)) 542 543 #define SCTLR_ELx_FLAGS (SCTLR_ELx_M | SCTLR_ELx_A | SCTLR_ELx_C | \ 544 SCTLR_ELx_SA | SCTLR_ELx_I | SCTLR_ELx_IESB) 545 546 /* SCTLR_EL2 specific flags. */ 547 #define SCTLR_EL2_RES1 ((BIT(4)) | (BIT(5)) | (BIT(11)) | (BIT(16)) | \ 548 (BIT(18)) | (BIT(22)) | (BIT(23)) | (BIT(28)) | \ 549 (BIT(29))) 550 551 #ifdef CONFIG_CPU_BIG_ENDIAN 552 #define ENDIAN_SET_EL2 SCTLR_ELx_EE 553 #else 554 #define ENDIAN_SET_EL2 0 555 #endif 556 557 /* SCTLR_EL1 specific flags. */ 558 #define SCTLR_EL1_UCI (BIT(26)) 559 #define SCTLR_EL1_E0E (BIT(24)) 560 #define SCTLR_EL1_SPAN (BIT(23)) 561 #define SCTLR_EL1_NTWE (BIT(18)) 562 #define SCTLR_EL1_NTWI (BIT(16)) 563 #define SCTLR_EL1_UCT (BIT(15)) 564 #define SCTLR_EL1_DZE (BIT(14)) 565 #define SCTLR_EL1_UMA (BIT(9)) 566 #define SCTLR_EL1_SED (BIT(8)) 567 #define SCTLR_EL1_ITD (BIT(7)) 568 #define SCTLR_EL1_CP15BEN (BIT(5)) 569 #define SCTLR_EL1_SA0 (BIT(4)) 570 571 #define SCTLR_EL1_RES1 ((BIT(11)) | (BIT(20)) | (BIT(22)) | (BIT(28)) | \ 572 (BIT(29))) 573 574 #ifdef CONFIG_CPU_BIG_ENDIAN 575 #define ENDIAN_SET_EL1 (SCTLR_EL1_E0E | SCTLR_ELx_EE) 576 #else 577 #define ENDIAN_SET_EL1 0 578 #endif 579 580 #define SCTLR_EL1_SET (SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA |\ 581 SCTLR_EL1_SA0 | SCTLR_EL1_SED | SCTLR_ELx_I |\ 582 SCTLR_EL1_DZE | SCTLR_EL1_UCT |\ 583 SCTLR_EL1_NTWE | SCTLR_ELx_IESB | SCTLR_EL1_SPAN |\ 584 ENDIAN_SET_EL1 | SCTLR_EL1_UCI | SCTLR_EL1_RES1) 585 586 /* id_aa64isar0 */ 587 #define ID_AA64ISAR0_TS_SHIFT 52 588 #define ID_AA64ISAR0_FHM_SHIFT 48 589 #define ID_AA64ISAR0_DP_SHIFT 44 590 #define ID_AA64ISAR0_SM4_SHIFT 40 591 #define ID_AA64ISAR0_SM3_SHIFT 36 592 #define ID_AA64ISAR0_SHA3_SHIFT 32 593 #define ID_AA64ISAR0_RDM_SHIFT 28 594 #define ID_AA64ISAR0_ATOMICS_SHIFT 20 595 #define ID_AA64ISAR0_CRC32_SHIFT 16 596 #define ID_AA64ISAR0_SHA2_SHIFT 12 597 #define ID_AA64ISAR0_SHA1_SHIFT 8 598 #define ID_AA64ISAR0_AES_SHIFT 4 599 600 /* id_aa64isar1 */ 601 #define ID_AA64ISAR1_SB_SHIFT 36 602 #define ID_AA64ISAR1_FRINTTS_SHIFT 32 603 #define ID_AA64ISAR1_GPI_SHIFT 28 604 #define ID_AA64ISAR1_GPA_SHIFT 24 605 #define ID_AA64ISAR1_LRCPC_SHIFT 20 606 #define ID_AA64ISAR1_FCMA_SHIFT 16 607 #define ID_AA64ISAR1_JSCVT_SHIFT 12 608 #define ID_AA64ISAR1_API_SHIFT 8 609 #define ID_AA64ISAR1_APA_SHIFT 4 610 #define ID_AA64ISAR1_DPB_SHIFT 0 611 612 #define ID_AA64ISAR1_APA_NI 0x0 613 #define ID_AA64ISAR1_APA_ARCHITECTED 0x1 614 #define ID_AA64ISAR1_API_NI 0x0 615 #define ID_AA64ISAR1_API_IMP_DEF 0x1 616 #define ID_AA64ISAR1_GPA_NI 0x0 617 #define ID_AA64ISAR1_GPA_ARCHITECTED 0x1 618 #define ID_AA64ISAR1_GPI_NI 0x0 619 #define ID_AA64ISAR1_GPI_IMP_DEF 0x1 620 621 /* id_aa64isar2 */ 622 #define ID_AA64ISAR2_CLEARBHB_SHIFT 28 623 #define ID_AA64ISAR2_RPRES_SHIFT 4 624 #define ID_AA64ISAR2_WFXT_SHIFT 0 625 626 #define ID_AA64ISAR2_RPRES_8BIT 0x0 627 #define ID_AA64ISAR2_RPRES_12BIT 0x1 628 /* 629 * Value 0x1 has been removed from the architecture, and is 630 * reserved, but has not yet been removed from the ARM ARM 631 * as of ARM DDI 0487G.b. 632 */ 633 #define ID_AA64ISAR2_WFXT_NI 0x0 634 #define ID_AA64ISAR2_WFXT_SUPPORTED 0x2 635 636 /* id_aa64pfr0 */ 637 #define ID_AA64PFR0_CSV3_SHIFT 60 638 #define ID_AA64PFR0_CSV2_SHIFT 56 639 #define ID_AA64PFR0_DIT_SHIFT 48 640 #define ID_AA64PFR0_AMU_SHIFT 44 641 #define ID_AA64PFR0_SVE_SHIFT 32 642 #define ID_AA64PFR0_RAS_SHIFT 28 643 #define ID_AA64PFR0_GIC_SHIFT 24 644 #define ID_AA64PFR0_ASIMD_SHIFT 20 645 #define ID_AA64PFR0_FP_SHIFT 16 646 #define ID_AA64PFR0_EL3_SHIFT 12 647 #define ID_AA64PFR0_EL2_SHIFT 8 648 #define ID_AA64PFR0_EL1_SHIFT 4 649 #define ID_AA64PFR0_EL0_SHIFT 0 650 651 #define ID_AA64PFR0_AMU 0x1 652 #define ID_AA64PFR0_SVE 0x1 653 #define ID_AA64PFR0_RAS_V1 0x1 654 #define ID_AA64PFR0_FP_NI 0xf 655 #define ID_AA64PFR0_FP_SUPPORTED 0x0 656 #define ID_AA64PFR0_ASIMD_NI 0xf 657 #define ID_AA64PFR0_ASIMD_SUPPORTED 0x0 658 #define ID_AA64PFR0_EL1_64BIT_ONLY 0x1 659 #define ID_AA64PFR0_EL0_64BIT_ONLY 0x1 660 #define ID_AA64PFR0_EL0_32BIT_64BIT 0x2 661 662 /* id_aa64pfr1 */ 663 #define ID_AA64PFR1_SSBS_SHIFT 4 664 665 #define ID_AA64PFR1_SSBS_PSTATE_NI 0 666 #define ID_AA64PFR1_SSBS_PSTATE_ONLY 1 667 #define ID_AA64PFR1_SSBS_PSTATE_INSNS 2 668 669 /* id_aa64zfr0 */ 670 #define ID_AA64ZFR0_SM4_SHIFT 40 671 #define ID_AA64ZFR0_SHA3_SHIFT 32 672 #define ID_AA64ZFR0_BITPERM_SHIFT 16 673 #define ID_AA64ZFR0_AES_SHIFT 4 674 #define ID_AA64ZFR0_SVEVER_SHIFT 0 675 676 #define ID_AA64ZFR0_SM4 0x1 677 #define ID_AA64ZFR0_SHA3 0x1 678 #define ID_AA64ZFR0_BITPERM 0x1 679 #define ID_AA64ZFR0_AES 0x1 680 #define ID_AA64ZFR0_AES_PMULL 0x2 681 #define ID_AA64ZFR0_SVEVER_SVE2 0x1 682 683 /* id_aa64mmfr0 */ 684 #define ID_AA64MMFR0_TGRAN4_SHIFT 28 685 #define ID_AA64MMFR0_TGRAN64_SHIFT 24 686 #define ID_AA64MMFR0_TGRAN16_SHIFT 20 687 #define ID_AA64MMFR0_BIGENDEL0_SHIFT 16 688 #define ID_AA64MMFR0_SNSMEM_SHIFT 12 689 #define ID_AA64MMFR0_BIGENDEL_SHIFT 8 690 #define ID_AA64MMFR0_ASID_SHIFT 4 691 #define ID_AA64MMFR0_PARANGE_SHIFT 0 692 693 #define ID_AA64MMFR0_TGRAN4_NI 0xf 694 #define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0 695 #define ID_AA64MMFR0_TGRAN64_NI 0xf 696 #define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0 697 #define ID_AA64MMFR0_TGRAN16_NI 0x0 698 #define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1 699 #define ID_AA64MMFR0_PARANGE_48 0x5 700 #define ID_AA64MMFR0_PARANGE_52 0x6 701 702 #ifdef CONFIG_ARM64_PA_BITS_52 703 #define ID_AA64MMFR0_PARANGE_MAX ID_AA64MMFR0_PARANGE_52 704 #else 705 #define ID_AA64MMFR0_PARANGE_MAX ID_AA64MMFR0_PARANGE_48 706 #endif 707 708 /* id_aa64mmfr1 */ 709 #define ID_AA64MMFR1_ECBHB_SHIFT 60 710 #define ID_AA64MMFR1_PAN_SHIFT 20 711 #define ID_AA64MMFR1_LOR_SHIFT 16 712 #define ID_AA64MMFR1_HPD_SHIFT 12 713 #define ID_AA64MMFR1_VHE_SHIFT 8 714 #define ID_AA64MMFR1_VMIDBITS_SHIFT 4 715 #define ID_AA64MMFR1_HADBS_SHIFT 0 716 717 #define ID_AA64MMFR1_VMIDBITS_8 0 718 #define ID_AA64MMFR1_VMIDBITS_16 2 719 720 /* id_aa64mmfr2 */ 721 #define ID_AA64MMFR2_FWB_SHIFT 40 722 #define ID_AA64MMFR2_AT_SHIFT 32 723 #define ID_AA64MMFR2_LVA_SHIFT 16 724 #define ID_AA64MMFR2_IESB_SHIFT 12 725 #define ID_AA64MMFR2_LSM_SHIFT 8 726 #define ID_AA64MMFR2_UAO_SHIFT 4 727 #define ID_AA64MMFR2_CNP_SHIFT 0 728 729 /* id_aa64dfr0 */ 730 #define ID_AA64DFR0_PMSVER_SHIFT 32 731 #define ID_AA64DFR0_CTX_CMPS_SHIFT 28 732 #define ID_AA64DFR0_WRPS_SHIFT 20 733 #define ID_AA64DFR0_BRPS_SHIFT 12 734 #define ID_AA64DFR0_PMUVER_SHIFT 8 735 #define ID_AA64DFR0_TRACEVER_SHIFT 4 736 #define ID_AA64DFR0_DEBUGVER_SHIFT 0 737 738 #define ID_AA64DFR0_PMUVER_8_1 0x4 739 740 #define ID_DFR0_PERFMON_SHIFT 24 741 742 #define ID_DFR0_PERFMON_8_1 0x4 743 744 #define ID_ISAR5_RDM_SHIFT 24 745 #define ID_ISAR5_CRC32_SHIFT 16 746 #define ID_ISAR5_SHA2_SHIFT 12 747 #define ID_ISAR5_SHA1_SHIFT 8 748 #define ID_ISAR5_AES_SHIFT 4 749 #define ID_ISAR5_SEVL_SHIFT 0 750 751 #define MVFR0_FPROUND_SHIFT 28 752 #define MVFR0_FPSHVEC_SHIFT 24 753 #define MVFR0_FPSQRT_SHIFT 20 754 #define MVFR0_FPDIVIDE_SHIFT 16 755 #define MVFR0_FPTRAP_SHIFT 12 756 #define MVFR0_FPDP_SHIFT 8 757 #define MVFR0_FPSP_SHIFT 4 758 #define MVFR0_SIMD_SHIFT 0 759 760 #define MVFR1_SIMDFMAC_SHIFT 28 761 #define MVFR1_FPHP_SHIFT 24 762 #define MVFR1_SIMDHP_SHIFT 20 763 #define MVFR1_SIMDSP_SHIFT 16 764 #define MVFR1_SIMDINT_SHIFT 12 765 #define MVFR1_SIMDLS_SHIFT 8 766 #define MVFR1_FPDNAN_SHIFT 4 767 #define MVFR1_FPFTZ_SHIFT 0 768 769 770 #define ID_AA64MMFR0_TGRAN4_SHIFT 28 771 #define ID_AA64MMFR0_TGRAN64_SHIFT 24 772 #define ID_AA64MMFR0_TGRAN16_SHIFT 20 773 774 #define ID_AA64MMFR0_TGRAN4_NI 0xf 775 #define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0 776 #define ID_AA64MMFR0_TGRAN64_NI 0xf 777 #define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0 778 #define ID_AA64MMFR0_TGRAN16_NI 0x0 779 #define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1 780 781 #if defined(CONFIG_ARM64_4K_PAGES) 782 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN4_SHIFT 783 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN4_SUPPORTED 784 #elif defined(CONFIG_ARM64_16K_PAGES) 785 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN16_SHIFT 786 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN16_SUPPORTED 787 #elif defined(CONFIG_ARM64_64K_PAGES) 788 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN64_SHIFT 789 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN64_SUPPORTED 790 #endif 791 792 793 /* 794 * The ZCR_ELx_LEN_* definitions intentionally include bits [8:4] which 795 * are reserved by the SVE architecture for future expansion of the LEN 796 * field, with compatible semantics. 797 */ 798 #define ZCR_ELx_LEN_SHIFT 0 799 #define ZCR_ELx_LEN_SIZE 9 800 #define ZCR_ELx_LEN_MASK 0x1ff 801 802 #define CPACR_EL1_ZEN_EL1EN (BIT(16)) /* enable EL1 access */ 803 #define CPACR_EL1_ZEN_EL0EN (BIT(17)) /* enable EL0 access, if EL1EN set */ 804 #define CPACR_EL1_ZEN (CPACR_EL1_ZEN_EL1EN | CPACR_EL1_ZEN_EL0EN) 805 806 807 /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */ 808 #define SYS_MPIDR_SAFE_VAL (BIT(31)) 809 810 #ifdef __ASSEMBLY__ 811 812 .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30 813 .equ .L__reg_num_x\num, \num 814 .endr 815 .equ .L__reg_num_xzr, 31 816 817 .macro mrs_s, rt, sreg 818 __emit_inst(0xd5200000|(\sreg)|(.L__reg_num_\rt)) 819 .endm 820 821 .macro msr_s, sreg, rt 822 __emit_inst(0xd5000000|(\sreg)|(.L__reg_num_\rt)) 823 .endm 824 825 #else 826 827 #include <linux/build_bug.h> 828 #include <linux/types.h> 829 830 #define __DEFINE_MRS_MSR_S_REGNUM \ 831 " .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n" \ 832 " .equ .L__reg_num_x\\num, \\num\n" \ 833 " .endr\n" \ 834 " .equ .L__reg_num_xzr, 31\n" 835 836 #define DEFINE_MRS_S \ 837 __DEFINE_MRS_MSR_S_REGNUM \ 838 " .macro mrs_s, rt, sreg\n" \ 839 __emit_inst(0xd5200000|(\\sreg)|(.L__reg_num_\\rt)) \ 840 " .endm\n" 841 842 #define DEFINE_MSR_S \ 843 __DEFINE_MRS_MSR_S_REGNUM \ 844 " .macro msr_s, sreg, rt\n" \ 845 __emit_inst(0xd5000000|(\\sreg)|(.L__reg_num_\\rt)) \ 846 " .endm\n" 847 848 #define UNDEFINE_MRS_S \ 849 " .purgem mrs_s\n" 850 851 #define UNDEFINE_MSR_S \ 852 " .purgem msr_s\n" 853 854 #define __mrs_s(v, r) \ 855 DEFINE_MRS_S \ 856 " mrs_s " v ", " __stringify(r) "\n" \ 857 UNDEFINE_MRS_S 858 859 #define __msr_s(r, v) \ 860 DEFINE_MSR_S \ 861 " msr_s " __stringify(r) ", " v "\n" \ 862 UNDEFINE_MSR_S 863 864 /* 865 * Unlike read_cpuid, calls to read_sysreg are never expected to be 866 * optimized away or replaced with synthetic values. 867 */ 868 #define read_sysreg(r) ({ \ 869 u64 __val; \ 870 asm volatile("mrs %0, " __stringify(r) : "=r" (__val)); \ 871 __val; \ 872 }) 873 874 /* 875 * The "Z" constraint normally means a zero immediate, but when combined with 876 * the "%x0" template means XZR. 877 */ 878 #define write_sysreg(v, r) do { \ 879 u64 __val = (u64)(v); \ 880 asm volatile("msr " __stringify(r) ", %x0" \ 881 : : "rZ" (__val)); \ 882 } while (0) 883 884 /* 885 * For registers without architectural names, or simply unsupported by 886 * GAS. 887 */ 888 #define read_sysreg_s(r) ({ \ 889 u64 __val; \ 890 asm volatile(__mrs_s("%0", r) : "=r" (__val)); \ 891 __val; \ 892 }) 893 894 #define write_sysreg_s(v, r) do { \ 895 u64 __val = (u64)(v); \ 896 asm volatile(__msr_s(r, "%x0") : : "rZ" (__val)); \ 897 } while (0) 898 899 /* 900 * Modify bits in a sysreg. Bits in the clear mask are zeroed, then bits in the 901 * set mask are set. Other bits are left as-is. 902 */ 903 #define sysreg_clear_set(sysreg, clear, set) do { \ 904 u64 __scs_val = read_sysreg(sysreg); \ 905 u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set); \ 906 if (__scs_new != __scs_val) \ 907 write_sysreg(__scs_new, sysreg); \ 908 } while (0) 909 910 #endif 911 912 #endif /* __ASM_SYSREG_H */ 913