Searched refs:clidr (Results 1 – 6 of 6) sorted by relevance
| /arch/arm64/include/asm/ |
| D | cache.h | 38 #define CLIDR_LOUU(clidr) (((clidr) >> CLIDR_LOUU_SHIFT) & 0x7) argument
39 #define CLIDR_LOC(clidr) (((clidr) >> CLIDR_LOC_SHIFT) & 0x7) argument
40 #define CLIDR_LOUIS(clidr) (((clidr) >> CLIDR_LOUIS_SHIFT) & 0x7) argument
114 u64 clidr = read_sysreg(clidr_el1); in read_cpuid_effective_cachetype() local
116 if (CLIDR_LOC(clidr) == 0 || in read_cpuid_effective_cachetype()
117 (CLIDR_LOUIS(clidr) == 0 && CLIDR_LOUU(clidr) == 0)) in read_cpuid_effective_cachetype()
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| /arch/arm64/kernel/ |
| D | cacheinfo.c | 17 #define CLIDR_CTYPE(clidr, level) \ argument
18 (((clidr) & CLIDR_CTYPE_MASK(level)) >> CLIDR_CTYPE_SHIFT(level))
31 u64 clidr; in get_cache_type() local
35 clidr = read_sysreg(clidr_el1); in get_cache_type()
36 return CLIDR_CTYPE(clidr, level); in get_cache_type()
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| /arch/arm/mm/ |
| D | cache-v7.S | 98 mrc p15, 1, r0, c0, c0, 1 @ read clidr, r0 = clidr
101 ands r3, r3, #7 << 1 @ extract LoU*2 field from clidr
126 mrc p15, 1, r0, c0, c0, 1 @ read clidr
128 ands r3, r3, #7 << 1 @ extract LoC*2 from clidr
134 mov r1, r0, lsr r2 @ extract cache type bits from clidr
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| D | cache-v7m.S | 176 ands r3, r3, #7 << 1 @ extract LoC*2 from clidr
182 mov r1, r0, lsr r2 @ extract cache type bits from clidr
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| /arch/arm/boot/compressed/ |
| D | head.S | 1219 mrc p15, 1, r0, c0, c0, 1 @ read clidr
1220 ands r3, r0, #0x7000000 @ extract loc from clidr
1226 mov r1, r0, lsr r2 @ extract cache type bits from clidr
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| /arch/arm64/kvm/ |
| D | sys_regs.c | 2840 struct sys_reg_desc clidr; in kvm_sys_reg_table_init() local
2864 get_clidr_el1(NULL, &clidr); /* Ugly... */ in kvm_sys_reg_table_init()
2865 cache_levels = clidr.val; in kvm_sys_reg_table_init()
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