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Searched refs:cr (Results 1 – 25 of 63) sorted by relevance

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/arch/s390/include/asm/
Dctl_reg.h58 static __always_inline void __ctl_set_bit(unsigned int cr, unsigned int bit) in __ctl_set_bit() argument
62 __ctl_store(reg, cr, cr); in __ctl_set_bit()
64 __ctl_load(reg, cr, cr); in __ctl_set_bit()
67 static __always_inline void __ctl_clear_bit(unsigned int cr, unsigned int bit) in __ctl_clear_bit() argument
71 __ctl_store(reg, cr, cr); in __ctl_clear_bit()
73 __ctl_load(reg, cr, cr); in __ctl_clear_bit()
76 void smp_ctl_set_bit(int cr, int bit);
77 void smp_ctl_clear_bit(int cr, int bit);
115 #define ctl_set_bit(cr, bit) smp_ctl_set_bit(cr, bit) argument
116 #define ctl_clear_bit(cr, bit) smp_ctl_clear_bit(cr, bit) argument
/arch/parisc/include/asm/
Dspecial_insns.h30 unsigned long cr; \
33 "=r" (cr) \
35 cr; \
38 #define mtctl(gr, cr) \ argument
41 : "r" (gr), "i" (cr) : "memory")
52 unsigned long cr; \
55 "=r" (cr) \
57 cr; \
60 #define mtsp(val, cr) \ argument
62 __asm__ __volatile__("mtsp %%r0,%0" : : "i" (cr) : "memory"); \
[all …]
/arch/ia64/include/asm/native/
Dinst.h12 mov reg = cr.ifa
15 mov reg = cr.itir
18 mov reg = cr.isr
21 mov reg = cr.iha
24 (pred) mov reg = cr.ipsr
27 mov reg = cr.iim
30 mov reg = cr.iip
33 mov reg = cr.ivr
42 mov cr.ifa = reg
45 (pred) mov cr.itir = reg
[all …]
/arch/csky/abiv2/inc/abi/
Dentry.h22 #define usp cr<14, 1>
151 mfcr \rx, cr<0, 15>
155 mfcr \rx, cr<4, 15>
159 mfcr \rx, cr<8, 15>
163 mfcr \rx, cr<29, 15>
167 mfcr \rx, cr<28, 15>
171 mtcr \rx, cr<4, 15>
175 mtcr \rx, cr<8, 15>
192 mtcr r6, cr<8, 15> /* Set MCIR */
201 mtcr r6, cr<6, 15> /* Set MPR with 4K page size */
[all …]
/arch/arm/mm/
Dcache-feroceon-l2.c243 u32 cr; in flush_and_disable_dcache() local
245 cr = get_cr(); in flush_and_disable_dcache()
246 if (cr & CR_C) { in flush_and_disable_dcache()
251 set_cr(cr & ~CR_C); in flush_and_disable_dcache()
260 u32 cr; in enable_dcache() local
262 cr = get_cr(); in enable_dcache()
263 set_cr(cr | CR_C); in enable_dcache()
273 u32 cr; in invalidate_and_disable_icache() local
275 cr = get_cr(); in invalidate_and_disable_icache()
276 if (cr & CR_I) { in invalidate_and_disable_icache()
[all …]
/arch/powerpc/platforms/powernv/
Dcopy-paste.h31 u32 cr; in vas_paste() local
33 cr = 0; in vas_paste()
36 : "=r" (cr) in vas_paste()
41 return (cr >> CR0_SHIFT) & 0xE; in vas_paste()
/arch/mips/kernel/
Dirq_txx9.c24 u32 cr[2]; member
45 #define TXx9_IRCR_EDGE(cr) ((cr) & 0x00000002) argument
115 u32 cr; in txx9_irq_set_type() local
130 crp = &txx9_ircptr->cr[(unsigned int)irq_nr / 8]; in txx9_irq_set_type()
131 cr = __raw_readl(crp); in txx9_irq_set_type()
133 cr &= ~(0x3 << ofs); in txx9_irq_set_type()
134 cr |= (mode & 0x3) << ofs; in txx9_irq_set_type()
135 __raw_writel(cr, crp); in txx9_irq_set_type()
167 __raw_writel(0, &txx9_ircptr->cr[i]); in txx9_irq_init()
/arch/mips/txx9/generic/
Dirq_tx4939.c36 #define TXx9_IRCR_EDGE(cr) ((cr) & 0x00000002) argument
107 u32 cr; in tx4939_irq_set_type() local
138 cr = __raw_readl(crp); in tx4939_irq_set_type()
139 cr &= ~(0x3 << ofs); in tx4939_irq_set_type()
140 cr |= (mode & 0x3) << ofs; in tx4939_irq_set_type()
141 __raw_writel(cr, crp); in tx4939_irq_set_type()
Dmem_tx4927.c72 for (i = 0; i < ARRAY_SIZE(tx4927_sdramcptr->cr); i++) in tx4927_get_mem_size()
73 total += tx4927_process_sdccr(&tx4927_sdramcptr->cr[i]); in tx4927_get_mem_size()
Dsetup_tx4938.c208 __u64 cr = TX4938_SDRAMC_CR(i); in tx4938_setup() local
210 if (!((__u32)cr & 0x00000400)) in tx4938_setup()
212 base = (unsigned long)(cr >> 49) << 21; in tx4938_setup()
213 size = (((unsigned long)(cr >> 33) & 0x7fff) + 1) << 21; in tx4938_setup()
214 pr_cont(" CR%d:%016llx", i, cr); in tx4938_setup()
224 if (txx9_pcode == 0x4938 && ____raw_readq(&tx4938_sramcptr->cr) & 1) { in tx4938_setup()
228 (____raw_readq(&tx4938_sramcptr->cr) >> (39-11)) in tx4938_setup()
362 ebccr = __raw_readq(&tx4938_ebuscptr->cr[i]); in tx4938_ata_init()
Dsetup_tx4927.c195 __u64 cr = TX4927_SDRAMC_CR(i); in tx4927_setup() local
197 if (!((__u32)cr & 0x00000400)) in tx4927_setup()
199 base = (unsigned long)(cr >> 49) << 21; in tx4927_setup()
200 size = (((unsigned long)(cr >> 33) & 0x7fff) + 1) << 21; in tx4927_setup()
201 pr_cont(" CR%d:%016llx", i, cr); in tx4927_setup()
/arch/powerpc/kvm/
Dbook3s_paired_singles.c630 u32 cr; in kvmppc_emulate_paired_single() local
651 cr = kvmppc_get_cr(vcpu); in kvmppc_emulate_paired_single()
1099 fpd_fadds(&vcpu->arch.fp.fpscr, &cr, fpr_d, fpr_a, fpr_b); in kvmppc_emulate_paired_single()
1103 fpd_fsubs(&vcpu->arch.fp.fpscr, &cr, fpr_d, fpr_a, fpr_b); in kvmppc_emulate_paired_single()
1107 fpd_fdivs(&vcpu->arch.fp.fpscr, &cr, fpr_d, fpr_a, fpr_b); in kvmppc_emulate_paired_single()
1111 fpd_fres(&vcpu->arch.fp.fpscr, &cr, fpr_d, fpr_b); in kvmppc_emulate_paired_single()
1115 fpd_frsqrtes(&vcpu->arch.fp.fpscr, &cr, fpr_d, fpr_b); in kvmppc_emulate_paired_single()
1121 fpd_fmuls(&vcpu->arch.fp.fpscr, &cr, fpr_d, fpr_a, fpr_c); in kvmppc_emulate_paired_single()
1125 fpd_fmsubs(&vcpu->arch.fp.fpscr, &cr, fpr_d, fpr_a, fpr_c, fpr_b); in kvmppc_emulate_paired_single()
1129 fpd_fmadds(&vcpu->arch.fp.fpscr, &cr, fpr_d, fpr_a, fpr_c, fpr_b); in kvmppc_emulate_paired_single()
[all …]
/arch/powerpc/include/asm/
Dkvm_fpu.h34 #define FPD_ONE_IN(name) extern void fpd_ ## name(u64 *fpscr, u32 *cr, \
36 #define FPD_TWO_IN(name) extern void fpd_ ## name(u64 *fpscr, u32 *cr, \
38 #define FPD_THREE_IN(name) extern void fpd_ ## name(u64 *fpscr, u32 *cr, \
41 extern void fpd_fcmpu(u64 *fpscr, u32 *cr, u64 *src1, u64 *src2);
42 extern void fpd_fcmpo(u64 *fpscr, u32 *cr, u64 *src1, u64 *src2);
Dicswx.h171 u32 cr; in icswx() local
176 : "=r" (cr) in icswx()
180 return (int)((cr >> 28) & 0xf); in icswx()
/arch/sh/include/asm/
Dmmu_context.h175 unsigned long cr; in disable_mmu() local
177 cr = __raw_readl(MMUCR); in disable_mmu()
178 cr &= ~MMU_CONTROL_INIT; in disable_mmu()
179 __raw_writel(cr, MMUCR); in disable_mmu()
/arch/ia64/include/asm/
Dmca_asm.h123 mov cr.ipsr = temp1; \
127 mov cr.iip = temp2; \
128 mov cr.ifs = r0; \
200 mov cr.ipsr = temp1; \
203 mov cr.iip = temp2; \
/arch/ia64/kernel/
Dmca_asm.S172 mov cr.itir=r18
173 mov cr.ifa=r17
199 mov cr.itir=r19
200 mov cr.ifa=r16
219 mov cr.itir=r19
220 mov cr.ifa=r18
473 mov r11=cr.iipa
483 mov r12=cr.isr
491 mov r6=cr.ifa
495 mov r12=cr.itir
[all …]
Dhead.S123 SAVE_FROM_REG(cr.dcr,_reg1,_reg2);; \
124 SAVE_FROM_REG(cr.iva,_reg1,_reg2);; \
125 SAVE_FROM_REG(cr.pta,_reg1,_reg2);; \
126 SAVE_FROM_REG(cr.itv,_reg1,_reg2);; \
127 SAVE_FROM_REG(cr.pmv,_reg1,_reg2);; \
128 SAVE_FROM_REG(cr.cmcv,_reg1,_reg2);; \
129 SAVE_FROM_REG(cr.lrr0,_reg1,_reg2);; \
130 SAVE_FROM_REG(cr.lrr1,_reg1,_reg2);; \
242 mov cr.itir=r18
243 mov cr.ifa=r17
[all …]
/arch/parisc/kernel/
Dtraps.c352 regs->gr[0] = pim_wide->cr[22]; in transfer_pim_to_trap_frame()
363 regs->iasq[0] = pim_wide->cr[17]; in transfer_pim_to_trap_frame()
365 regs->iaoq[0] = pim_wide->cr[18]; in transfer_pim_to_trap_frame()
368 regs->sar = pim_wide->cr[11]; in transfer_pim_to_trap_frame()
369 regs->iir = pim_wide->cr[19]; in transfer_pim_to_trap_frame()
370 regs->isr = pim_wide->cr[20]; in transfer_pim_to_trap_frame()
371 regs->ior = pim_wide->cr[21]; in transfer_pim_to_trap_frame()
376 regs->gr[0] = pim_narrow->cr[22]; in transfer_pim_to_trap_frame()
387 regs->iasq[0] = pim_narrow->cr[17]; in transfer_pim_to_trap_frame()
389 regs->iaoq[0] = pim_narrow->cr[18]; in transfer_pim_to_trap_frame()
[all …]
/arch/mips/txx9/jmr3927/
Dsetup.c130 tx3927_romcptr->cr[1] = JMR3927_ROMCE1 | 0x00030048; in jmr3927_board_init()
131 tx3927_romcptr->cr[2] = JMR3927_ROMCE2 | 0x000064c8; in jmr3927_board_init()
132 tx3927_romcptr->cr[3] = JMR3927_ROMCE3 | 0x0003f698; in jmr3927_board_init()
133 tx3927_romcptr->cr[5] = JMR3927_ROMCE5 | 0x0000f218; in jmr3927_board_init()
/arch/powerpc/boot/
Dugecon.c43 u32 csr, data, cr; in ug_io_transaction() local
52 cr = EXI_CR_TLEN(2) | EXI_CR_READ_WRITE | EXI_CR_TSTART; in ug_io_transaction()
53 out_be32(cr_reg, cr); in ug_io_transaction()
/arch/mips/include/asm/txx9/
Dtx3927.h26 volatile unsigned long cr[8]; member
33 volatile unsigned long cr[8]; member
325 #define TX3927_ROMC_BA(ch) (tx3927_romcptr->cr[(ch)] & 0xfff00000)
327 (0x00100000 << ((tx3927_romcptr->cr[(ch)] >> 8) & 0xf))
328 #define TX3927_ROMC_WIDTH(ch) (32 >> ((tx3927_romcptr->cr[(ch)] >> 7) & 0x1))
Dtx4927.h79 u64 cr[4]; member
87 u64 cr[8]; member
203 #define TX4927_SDRAMC_CR(ch) __raw_readq(&tx4927_sdramcptr->cr[(ch)])
208 #define TX4927_EBUSC_CR(ch) __raw_readq(&tx4927_ebuscptr->cr[(ch)])
/arch/powerpc/xmon/
Dppc-dis.c242 int cr; in print_insn_powerpc() local
245 cr = value >> 2; in print_insn_powerpc()
246 if (cr != 0) in print_insn_powerpc()
247 printf("4*cr%d+", cr); in print_insn_powerpc()
/arch/powerpc/platforms/embedded6xx/
Dusbgecko_udbg.c50 u32 csr, data, cr; in ug_io_transaction() local
59 cr = EXI_CR_TLEN(2) | EXI_CR_READ_WRITE | EXI_CR_TSTART; in ug_io_transaction()
60 out_be32(cr_reg, cr); in ug_io_transaction()

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