| /arch/arm64/include/asm/vdso/ |
| D | compat_barrier.h | 17 #ifdef dmb
18 #undef dmb
21 #define dmb(option) __asm__ __volatile__ ("dmb " #option : : : "memory") macro
24 #define aarch32_smp_mb() dmb(ish)
25 #define aarch32_smp_rmb() dmb(ishld)
26 #define aarch32_smp_wmb() dmb(ishst)
28 #define aarch32_smp_mb() dmb(ish)
30 #define aarch32_smp_wmb() dmb(ishst)
|
| /arch/arm/include/asm/ |
| D | barrier.h | 21 #define dmb(option) __asm__ __volatile__ ("dmb " #option : : : "memory") macro
33 #define dmb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \ macro
40 #define dmb(x) __asm__ __volatile__ ("" : : : "memory") macro
45 #define dmb(x) __asm__ __volatile__ ("" : : : "memory") macro
67 #define dma_rmb() dmb(osh)
68 #define dma_wmb() dmb(oshst)
77 #define __smp_mb() dmb(ish)
79 #define __smp_wmb() dmb(ishst)
|
| D | assembler.h | 310 ALT_SMP(dmb ish)
312 ALT_SMP(W(dmb) ish)
315 ALT_SMP(mcr p15, 0, r0, c7, c10, 5) @ dmb
|
| /arch/arm64/include/asm/ |
| D | barrier.h | 22 #define dmb(opt) asm volatile("dmb " #opt : : : "memory") macro
36 #define dma_rmb() dmb(oshld)
37 #define dma_wmb() dmb(oshst)
79 #define __smp_mb() dmb(ish)
80 #define __smp_rmb() dmb(ishld)
81 #define __smp_wmb() dmb(ishst)
|
| D | atomic_ll_sc.h | 86 ATOMIC_OP_RETURN( , dmb ish, , l, "memory", __VA_ARGS__)\
90 ATOMIC_FETCH_OP ( , dmb ish, , l, "memory", __VA_ARGS__)\
101 ATOMIC_FETCH_OP ( , dmb ish, , l, "memory", __VA_ARGS__)\ in ATOMIC_OPS()
182 ATOMIC64_OP_RETURN(, dmb ish, , l, "memory", __VA_ARGS__) \
186 ATOMIC64_FETCH_OP (, dmb ish, , l, "memory", __VA_ARGS__) \
197 ATOMIC64_FETCH_OP (, dmb ish, , l, "memory", __VA_ARGS__) \
290 __CMPXCHG_CASE(w, b, mb_, 8, dmb ish, , l, "memory", K)
291 __CMPXCHG_CASE(w, h, mb_, 16, dmb ish, , l, "memory", K)
292 __CMPXCHG_CASE(w, , mb_, 32, dmb ish, , l, "memory", K)
293 __CMPXCHG_CASE( , , mb_, 64, dmb ish, , l, "memory", L)
[all …]
|
| D | cmpxchg.h | 57 __XCHG_CASE(w, b, mb_, 8, dmb ish, nop, , a, l, "memory")
58 __XCHG_CASE(w, h, mb_, 16, dmb ish, nop, , a, l, "memory")
59 __XCHG_CASE(w, , mb_, 32, dmb ish, nop, , a, l, "memory")
60 __XCHG_CASE( , , mb_, 64, dmb ish, nop, , a, l, "memory")
|
| /arch/arm/common/ |
| D | vlock.S | 29 dmb
33 dmb
80 dmb
93 dmb
|
| D | mcpm_head.S | 121 dmb
136 dmb
148 dmb
152 dmb
173 dmb
182 dmb
196 dmb
|
| D | mcpm_entry.c | 49 dmb(); in __mcpm_cpu_down()
65 dmb(); in __mcpm_outbound_leave_critical()
|
| /arch/unicore32/include/asm/ |
| D | barrier.h | 12 #define dmb() __asm__ __volatile__ ("" : : : "memory") macro
|
| /arch/arm/mm/ |
| D | cache-b15-rac.c | 66 dmb(); in __b15_rac_disable()
80 dmb(); in __b15_rac_flush()
|
| D | cache-v7.S | 97 dmb @ ensure ordering with previous memory accesses
125 dmb @ ensure ordering with previous memory accesses
|
| /arch/arm64/mm/ |
| D | flush.c | 84 dmb(osh); in arch_wb_cache_pmem()
|
| D | proc.S | 220 dmb sy // lines are written back before
229 dmb sy // that it is visible to all
|
| /arch/arm/mach-omap2/ |
| D | sleep34xx.S | 97 dmb @ data memory barrier
213 dmb
418 dmb @ data memory barrier
429 dmb @ data memory barrier
444 dmb @ data memory barrier
|
| D | omap-smc.S | 52 dmb
|
| D | sleep33xx.S | 133 dmb
|
| D | sleep44xx.S | 350 dmb
|
| D | sleep43xx.S | 263 dmb
|
| /arch/arm64/kernel/ |
| D | head.S | 136 dmb sy // needed before dc ivac with
325 dmb sy
347 dmb sy
401 dmb sy
663 dmb sy
775 dmb sy
|
| /arch/arm/mach-socfpga/ |
| D | self-refresh.S | 85 dmb
|
| /arch/arm/mach-tegra/ |
| D | sleep.S | 35 dmb @ ensure ordering
|
| /arch/arm/kernel/ |
| D | smp_tlb.c | 153 dmb(); in ipi_flush_tlb_a15_erratum()
|
| /arch/arm/mach-bcm/ |
| D | platsmp-brcmstb.c | 75 dmb(); in per_cpu_sw_state_wr()
|
| /arch/arm64/kernel/vdso32/ |
| D | Makefile | 113 dmbinstr := $(call cc32-as-instr,dmb ishld,-DCONFIG_AS_DMB_ISHLD=1)
|