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Searched refs:enable_reg (Results 1 – 6 of 6) sorted by relevance

/arch/arm/mach-ep93xx/
Dclock.c32 void __iomem *enable_reg; member
53 .enable_reg = EP93XX_SYSCON_DEVCFG,
60 .enable_reg = EP93XX_SYSCON_DEVCFG,
67 .enable_reg = EP93XX_SYSCON_DEVCFG,
88 .enable_reg = EP93XX_SYSCON_PWRCNT,
94 .enable_reg = EP93XX_SYSCON_KEYTCHCLKDIV,
101 .enable_reg = EP93XX_SYSCON_KEYTCHCLKDIV,
116 .enable_reg = EP93XX_SYSCON_VIDCLKDIV,
123 .enable_reg = EP93XX_SYSCON_I2SCLKDIV,
131 .enable_reg = EP93XX_SYSCON_I2SCLKDIV,
[all …]
/arch/arm/mach-omap1/
Dclock_data.c98 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
110 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1),
132 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
151 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
162 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
175 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
188 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
212 .enable_reg = OMAP1_IO_ADDRESS(ARM_CKCTL),
234 .enable_reg = DSP_IDLECT2,
246 .enable_reg = DSP_IDLECT2,
[all …]
Dclock.c43 unsigned int val = __raw_readl(clk->enable_reg); in omap1_uart_recalc()
331 val = __raw_readl(clk->enable_reg); in omap1_set_uart_rate()
338 __raw_writel(val, clk->enable_reg); in omap1_set_uart_rate()
357 ratio_bits |= __raw_readw(clk->enable_reg) & ~0xfd; in omap1_set_ext_clk_rate()
358 __raw_writew(ratio_bits, clk->enable_reg); in omap1_set_ext_clk_rate()
397 ratio_bits = __raw_readw(clk->enable_reg) & ~1; in omap1_init_ext_clk()
398 __raw_writew(ratio_bits, clk->enable_reg); in omap1_init_ext_clk()
454 if (unlikely(clk->enable_reg == NULL)) { in omap1_clk_enable_generic()
461 regval32 = __raw_readl(clk->enable_reg); in omap1_clk_enable_generic()
463 __raw_writel(regval32, clk->enable_reg); in omap1_clk_enable_generic()
[all …]
Dclock.h146 void __iomem *enable_reg; member
/arch/arm/plat-omap/
Ddma.c1211 u32 val, enable_reg; in omap2_dma_irq_handler() local
1220 enable_reg = p->dma_read(IRQENABLE_L0, 0); in omap2_dma_irq_handler()
1221 val &= enable_reg; /* Dispatch only relevant interrupts */ in omap2_dma_irq_handler()
/arch/sh/drivers/pci/
Dpcie-sh7786.c238 clk->enable_reg = (void __iomem *)(chan->reg_base + SH4A_PCIEPHYCTLR); in pcie_clk_init()