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Searched refs:imx_readl (Results 1 – 14 of 14) sorted by relevance

/arch/arm/mach-imx/
Dtzic.c61 value = imx_readl(tzic_base + TZIC_INTSEC0(index)) | mask; in tzic_set_irq_fiq()
85 imx_writel(imx_readl(tzic_base + TZIC_ENSET0(idx)), in tzic_irq_resume()
131 stat = imx_readl(tzic_base + TZIC_HIPND(i)) & in tzic_handle_irq()
132 imx_readl(tzic_base + TZIC_INTSEC0(i)); in tzic_handle_irq()
160 i = imx_readl(tzic_base + TZIC_INTCNTL); in tzic_init_dt()
212 if (unlikely(imx_readl(tzic_base + TZIC_DSMINT) == 0)) in tzic_enable_wake()
216 imx_writel(imx_readl(tzic_base + TZIC_ENSET0(i)), in tzic_enable_wake()
Davic.c59 irqt = imx_readl(avic_base + AVIC_INTTYPEL) & ~(1 << hwirq); in avic_set_irq_fiq()
63 irqt = imx_readl(avic_base + AVIC_INTTYPEH) & ~(1 << hwirq); in avic_set_irq_fiq()
87 avic_saved_mask_reg[idx] = imx_readl(avic_base + ct->regs.mask); in avic_irq_suspend()
152 nivector = imx_readl(avic_base + AVIC_NIVECSR) >> 16; in avic_handle_irq()
Diomux-imx31.c47 l = imx_readl(reg); in mxc_iomux_mode()
72 l = imx_readl(reg); in mxc_iomux_set_pad()
153 l = imx_readl(IOMUXGPR); in mxc_iomux_set_gpr()
Dpm-imx5.c150 plat_lpc = imx_readl(cortex_base + MXC_CORTEXA8_PLAT_LPC) & in mx5_cpu_lp_set()
152 ccm_clpcr = imx_readl(ccm_base + MXC_CCM_CLPCR) & in mx5_cpu_lp_set()
154 arm_srpgcr = imx_readl(gpc_base + MXC_SRPG_ARM_SRPGCR) & in mx5_cpu_lp_set()
156 empgc0 = imx_readl(gpc_base + MXC_SRPG_EMPGC0_SRPGCR) & in mx5_cpu_lp_set()
158 empgc1 = imx_readl(gpc_base + MXC_SRPG_EMPGC1_SRPGCR) & in mx5_cpu_lp_set()
Dpm-imx27.c22 cscr = imx_readl(MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR)); in mx27_suspend_enter()
Dcpu-imx35.c27 rev = imx_readl(iim_base + MXC_IIMSREV); in mx35_read_cpu_rev()
Dcpu-imx27.c38 val = imx_readl(ccm_base + SYSCTRL_OFFSET + SYS_CHIP_ID); in mx27_read_cpu_rev()
Dmxc.h102 #define imx_readl readl_relaxed macro
Dmach-imx51.c41 imx_writel(imx_readl(hsc_addr + 0x800) | 0x30ff, hsc_addr + 0x800); in imx51_ipu_mipi_setup()
Dcpu-imx31.c46 srev = imx_readl(iim_base + MXC_IIMSREV); in mx31_read_cpu_rev()
Dmm-imx3.c130 int reg = imx_readl(mx3_ccm_base + MXC_CCM_CCMR); in imx31_idle()
222 int reg = imx_readl(mx3_ccm_base + MXC_CCM_CCMR); in imx35_idle()
Dcpu.c59 reg = imx_readl(base + 0x50) & 0x00FFFFFF; in imx_set_aips()
Diomux-v1.c28 return imx_readl(imx_iomuxv1_baseaddr + offset); in imx_iomuxv1_readl()
Dmach-armadillo5x0.c502 imx_writel(imx_readl(mx3_ccm_base + MXC_CCM_RCSR) | (1 << 30), in armadillo5x0_init()