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Searched refs:imx_writel (Results 1 – 13 of 13) sorted by relevance

/arch/arm/mach-imx/
Davic.c60 imx_writel(irqt | (!!type << hwirq), avic_base + AVIC_INTTYPEL); in avic_set_irq_fiq()
64 imx_writel(irqt | (!!type << hwirq), avic_base + AVIC_INTTYPEH); in avic_set_irq_fiq()
88 imx_writel(gc->wake_active, avic_base + ct->regs.mask); in avic_irq_suspend()
99 imx_writel(~gc->wake_active, mx25_ccm_base + offs); in avic_irq_suspend()
109 imx_writel(avic_saved_mask_reg[idx], avic_base + ct->regs.mask); in avic_irq_resume()
115 imx_writel(0xffffffff, mx25_ccm_base + offs); in avic_irq_resume()
181 imx_writel(0xffffffff, mx25_ccm_base + MX25_CCM_LPIMR0); in mxc_init_irq()
182 imx_writel(0xffffffff, mx25_ccm_base + MX25_CCM_LPIMR1); in mxc_init_irq()
188 imx_writel(0, avic_base + AVIC_INTCNTL); in mxc_init_irq()
189 imx_writel(0x1f, avic_base + AVIC_NIMASK); in mxc_init_irq()
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Dcpu.c47 imx_writel(0x77777777, base + 0x0); in imx_set_aips()
48 imx_writel(0x77777777, base + 0x4); in imx_set_aips()
55 imx_writel(0x0, base + 0x40); in imx_set_aips()
56 imx_writel(0x0, base + 0x44); in imx_set_aips()
57 imx_writel(0x0, base + 0x48); in imx_set_aips()
58 imx_writel(0x0, base + 0x4C); in imx_set_aips()
60 imx_writel(reg, base + 0x50); in imx_set_aips()
Dtzic.c64 imx_writel(value, tzic_base + TZIC_INTSEC0(index)); in tzic_set_irq_fiq()
78 imx_writel(gc->wake_active, tzic_base + TZIC_WAKEUP0(idx)); in tzic_irq_suspend()
85 imx_writel(imx_readl(tzic_base + TZIC_ENSET0(idx)), in tzic_irq_resume()
162 imx_writel(0x80010001, tzic_base + TZIC_INTCNTL); in tzic_init_dt()
163 imx_writel(0x1f, tzic_base + TZIC_PRIOMASK); in tzic_init_dt()
164 imx_writel(0x02, tzic_base + TZIC_SYNCCTRL); in tzic_init_dt()
167 imx_writel(0xFFFFFFFF, tzic_base + TZIC_INTSEC0(i)); in tzic_init_dt()
171 imx_writel(0xFFFFFFFF, tzic_base + TZIC_ENCLEAR0(i)); in tzic_init_dt()
211 imx_writel(1, tzic_base + TZIC_DSMINT); in tzic_enable_wake()
216 imx_writel(imx_readl(tzic_base + TZIC_ENSET0(i)), in tzic_enable_wake()
Diomux-v3.c35 imx_writel(mux_mode, base + mux_ctrl_ofs); in mxc_iomux_v3_setup_pad()
38 imx_writel(sel_input, base + sel_input_ofs); in mxc_iomux_v3_setup_pad()
41 imx_writel(pad_ctrl, base + pad_ctrl_ofs); in mxc_iomux_v3_setup_pad()
Dpm-imx5.c193 imx_writel(plat_lpc, cortex_base + MXC_CORTEXA8_PLAT_LPC); in mx5_cpu_lp_set()
194 imx_writel(ccm_clpcr, ccm_base + MXC_CCM_CLPCR); in mx5_cpu_lp_set()
195 imx_writel(arm_srpgcr, gpc_base + MXC_SRPG_ARM_SRPGCR); in mx5_cpu_lp_set()
196 imx_writel(arm_srpgcr, gpc_base + MXC_SRPG_NEON_SRPGCR); in mx5_cpu_lp_set()
202 imx_writel(empgc0, gpc_base + MXC_SRPG_EMPGC0_SRPGCR); in mx5_cpu_lp_set()
203 imx_writel(empgc1, gpc_base + MXC_SRPG_EMPGC1_SRPGCR); in mx5_cpu_lp_set()
225 imx_writel(0, gpc_base + MXC_SRPG_EMPGC0_SRPGCR); in mx5_suspend_enter()
226 imx_writel(0, gpc_base + MXC_SRPG_EMPGC1_SRPGCR); in mx5_suspend_enter()
Dmach-imx51.c38 imx_writel(0xf00, hsc_addr); in imx51_ipu_mipi_setup()
41 imx_writel(imx_readl(hsc_addr + 0x800) | 0x30ff, hsc_addr + 0x800); in imx51_ipu_mipi_setup()
Diomux-imx31.c50 imx_writel(l, reg); in mxc_iomux_mode()
75 imx_writel(l, reg); in mxc_iomux_set_pad()
159 imx_writel(l, IOMUXGPR); in mxc_iomux_set_gpr()
Dmach-qong.c183 imx_writel(0x00004f00, MX31_IO_ADDRESS(MX31_WEIM_CSCRxU(3))); in qong_init_nand_mtd()
184 imx_writel(0x20013b31, MX31_IO_ADDRESS(MX31_WEIM_CSCRxL(3))); in qong_init_nand_mtd()
185 imx_writel(0x00020800, MX31_IO_ADDRESS(MX31_WEIM_CSCRxA(3))); in qong_init_nand_mtd()
Dpm-imx27.c24 imx_writel(cscr, MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR)); in mx27_suspend_enter()
Dmxc.h104 #define imx_writel writel_relaxed macro
Dmm-imx3.c132 imx_writel(reg, mx3_ccm_base + MXC_CCM_CCMR); in imx31_idle()
225 imx_writel(reg, mx3_ccm_base + MXC_CCM_CCMR); in imx35_idle()
Diomux-v1.c33 imx_writel(val, imx_iomuxv1_baseaddr + offset); in imx_iomuxv1_writel()
Dmach-armadillo5x0.c502 imx_writel(imx_readl(mx3_ccm_base + MXC_CCM_RCSR) | (1 << 30), in armadillo5x0_init()