| /arch/sparc/kernel/ |
| D | iommu.c | 52 struct iommu *iommu = container_of(iommu_map_table, struct iommu, tbl); in iommu_flushall() local
53 if (iommu->iommu_flushinv) { in iommu_flushall()
54 iommu_write(iommu->iommu_flushinv, ~(u64)0); in iommu_flushall()
59 tag = iommu->iommu_tags; in iommu_flushall()
66 (void) iommu_read(iommu->write_complete_reg); in iommu_flushall()
80 #define IOPTE_IS_DUMMY(iommu, iopte) \ argument
81 ((iopte_val(*iopte) & IOPTE_PAGE) == (iommu)->dummy_page_pa)
83 static inline void iopte_make_dummy(struct iommu *iommu, iopte_t *iopte) in iopte_make_dummy() argument
88 val |= iommu->dummy_page_pa; in iopte_make_dummy()
93 int iommu_table_init(struct iommu *iommu, int tsbsize, in iommu_table_init() argument
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| D | iommu-common.c | 19 static inline bool need_flush(struct iommu_map_table *iommu) in need_flush() argument
21 return ((iommu->flags & IOMMU_NEED_FLUSH) != 0); in need_flush()
24 static inline void set_flush(struct iommu_map_table *iommu) in set_flush() argument
26 iommu->flags |= IOMMU_NEED_FLUSH; in set_flush()
29 static inline void clear_flush(struct iommu_map_table *iommu) in clear_flush() argument
31 iommu->flags &= ~IOMMU_NEED_FLUSH; in clear_flush()
52 void iommu_tbl_pool_init(struct iommu_map_table *iommu, in iommu_tbl_pool_init() argument
60 struct iommu_pool *p = &(iommu->large_pool); in iommu_tbl_pool_init()
64 iommu->nr_pools = IOMMU_NR_POOLS; in iommu_tbl_pool_init()
66 iommu->nr_pools = npools; in iommu_tbl_pool_init()
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| D | sbus.c | 62 struct iommu *iommu = dev->archdata.iommu; in sbus_set_sbus64() local
77 cfg_reg = iommu->write_complete_reg; in sbus_set_sbus64()
212 struct iommu *iommu = op->dev.archdata.iommu; in sbus_build_irq() local
213 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL; in sbus_build_irq()
274 struct iommu *iommu = op->dev.archdata.iommu; in sysio_ue_handler() local
275 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL; in sysio_ue_handler()
348 struct iommu *iommu = op->dev.archdata.iommu; in sysio_ce_handler() local
349 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL; in sysio_ce_handler()
427 struct iommu *iommu = op->dev.archdata.iommu; in sysio_sbus_error_handler() local
432 reg_base = iommu->write_complete_reg - 0x2000UL; in sysio_sbus_error_handler()
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| D | pci_sun4v.c | 76 static inline bool iommu_use_atu(struct iommu *iommu, u64 mask) in iommu_use_atu() argument
78 return iommu->atu && mask > DMA_BIT_MASK(32); in iommu_use_atu()
100 if (!iommu_use_atu(pbm->iommu, mask)) { in iommu_batch_flush()
117 iotsb_num = pbm->iommu->atu->iotsb->iotsb_num; in iommu_batch_flush()
186 struct iommu *iommu; in dma_4v_alloc_coherent() local
211 iommu = dev->archdata.iommu; in dma_4v_alloc_coherent()
213 if (!iommu_use_atu(iommu, mask)) in dma_4v_alloc_coherent()
214 tbl = &iommu->tbl; in dma_4v_alloc_coherent()
216 tbl = &iommu->atu->tbl; in dma_4v_alloc_coherent()
325 struct iommu *iommu; in dma_4v_free_coherent() local
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| D | psycho_common.c | 208 struct iommu *iommu = pbm->iommu; in psycho_check_iommu_error() local
211 spin_lock_irqsave(&iommu->lock, flags); in psycho_check_iommu_error()
212 control = upa_readq(iommu->iommu_control); in psycho_check_iommu_error()
217 upa_writeq(control, iommu->iommu_control); in psycho_check_iommu_error()
247 spin_unlock_irqrestore(&iommu->lock, flags); in psycho_check_iommu_error()
404 struct iommu *iommu = pbm->iommu; in psycho_iommu_init() local
408 iommu->iommu_control = pbm->controller_regs + PSYCHO_IOMMU_CONTROL; in psycho_iommu_init()
409 iommu->iommu_tsbbase = pbm->controller_regs + PSYCHO_IOMMU_TSBBASE; in psycho_iommu_init()
410 iommu->iommu_flush = pbm->controller_regs + PSYCHO_IOMMU_FLUSH; in psycho_iommu_init()
411 iommu->iommu_tags = pbm->controller_regs + PSYCHO_IOMMU_TAG; in psycho_iommu_init()
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| D | pci_fire.c | 32 struct iommu *iommu = pbm->iommu; in pci_fire_pbm_iommu_init() local
44 iommu->iommu_control = pbm->pbm_regs + FIRE_IOMMU_CONTROL; in pci_fire_pbm_iommu_init()
45 iommu->iommu_tsbbase = pbm->pbm_regs + FIRE_IOMMU_TSBBASE; in pci_fire_pbm_iommu_init()
46 iommu->iommu_flush = pbm->pbm_regs + FIRE_IOMMU_FLUSH; in pci_fire_pbm_iommu_init()
47 iommu->iommu_flushinv = pbm->pbm_regs + FIRE_IOMMU_FLUSHINV; in pci_fire_pbm_iommu_init()
52 iommu->write_complete_reg = pbm->controller_regs + 0x410000UL; in pci_fire_pbm_iommu_init()
57 upa_writeq(~(u64)0, iommu->iommu_flushinv); in pci_fire_pbm_iommu_init()
59 err = iommu_table_init(iommu, tsbsize * 8 * 1024, vdma[0], dma_mask, in pci_fire_pbm_iommu_init()
64 upa_writeq(__pa(iommu->page_table) | 0x7UL, iommu->iommu_tsbbase); in pci_fire_pbm_iommu_init()
66 control = upa_readq(iommu->iommu_control); in pci_fire_pbm_iommu_init()
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| D | pci_schizo.c | 239 struct iommu *iommu = pbm->iommu; in schizo_check_iommu_error_pbm() local
246 spin_lock_irqsave(&iommu->lock, flags); in schizo_check_iommu_error_pbm()
247 control = upa_readq(iommu->iommu_control); in schizo_check_iommu_error_pbm()
254 upa_writeq(control, iommu->iommu_control); in schizo_check_iommu_error_pbm()
285 iommu->iommu_control); in schizo_check_iommu_error_pbm()
301 upa_writeq(control, iommu->iommu_control); in schizo_check_iommu_error_pbm()
343 spin_unlock_irqrestore(&iommu->lock, flags); in schizo_check_iommu_error_pbm()
1137 struct iommu *iommu = pbm->iommu; in schizo_pbm_iommu_init() local
1170 iommu->iommu_control = pbm->pbm_regs + SCHIZO_IOMMU_CONTROL; in schizo_pbm_iommu_init()
1171 iommu->iommu_tsbbase = pbm->pbm_regs + SCHIZO_IOMMU_TSBBASE; in schizo_pbm_iommu_init()
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| D | pci_psycho.c | 513 struct iommu *iommu; in psycho_probe() local
528 iommu = pbm->sibling->iommu; in psycho_probe()
530 iommu = kzalloc(sizeof(struct iommu), GFP_KERNEL); in psycho_probe()
531 if (!iommu) { in psycho_probe()
537 pbm->iommu = iommu; in psycho_probe()
588 kfree(pbm->iommu); in psycho_probe()
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| D | ldc.c | 146 struct ldc_iommu iommu; member
1022 static void ldc_demap(struct ldc_iommu *iommu, unsigned long id, u64 cookie, in ldc_demap() argument
1029 base = iommu->page_table + entry; in ldc_demap()
1044 struct ldc_iommu *ldc_iommu = &lp->iommu; in ldc_iommu_init()
1045 struct iommu_map_table *iommu = &ldc_iommu->iommu_map_table; in ldc_iommu_init() local
1056 iommu->map = kzalloc(sz, GFP_KERNEL); in ldc_iommu_init()
1057 if (!iommu->map) { in ldc_iommu_init()
1061 iommu_tbl_pool_init(iommu, num_tsb_entries, PAGE_SHIFT, in ldc_iommu_init()
1094 kfree(iommu->map); in ldc_iommu_init()
1095 iommu->map = NULL; in ldc_iommu_init()
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| D | pci_sabre.c | 464 struct iommu *iommu; in sabre_probe() local
490 iommu = kzalloc(sizeof(*iommu), GFP_KERNEL); in sabre_probe()
491 if (!iommu) { in sabre_probe()
496 pbm->iommu = iommu; in sabre_probe()
579 kfree(pbm->iommu); in sabre_probe()
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| /arch/powerpc/platforms/cell/ |
| D | iommu.c | 102 struct cbe_iommu *iommu; member
129 static void invalidate_tce_cache(struct cbe_iommu *iommu, unsigned long *pte, in invalidate_tce_cache() argument
136 reg = iommu->xlate_regs + IOC_IOPT_CacheInvd; in invalidate_tce_cache()
193 invalidate_tce_cache(window->iommu, io_pte, npages); in tce_build_cell()
216 __pa(window->iommu->pad_page) | in tce_free_cell()
227 invalidate_tce_cache(window->iommu, io_pte, npages); in tce_free_cell()
233 struct cbe_iommu *iommu = data; in ioc_interrupt() local
235 stat = in_be64(iommu->xlate_regs + IOC_IO_ExcpStat); in ioc_interrupt()
251 out_be64(iommu->xlate_regs + IOC_IO_ExcpStat, stat); in ioc_interrupt()
296 static void cell_iommu_setup_stab(struct cbe_iommu *iommu, in cell_iommu_setup_stab() argument
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| /arch/sparc/mm/ |
| D | iommu.c | 59 struct iommu_struct *iommu; in sbus_iommu_init() local
66 iommu = kmalloc(sizeof(struct iommu_struct), GFP_KERNEL); in sbus_iommu_init()
67 if (!iommu) { in sbus_iommu_init()
72 iommu->regs = of_ioremap(&op->resource[0], 0, PAGE_SIZE * 3, in sbus_iommu_init()
74 if (!iommu->regs) { in sbus_iommu_init()
79 control = sbus_readl(&iommu->regs->control); in sbus_iommu_init()
84 sbus_writel(control, &iommu->regs->control); in sbus_iommu_init()
86 iommu_invalidate(iommu->regs); in sbus_iommu_init()
87 iommu->start = IOMMU_START; in sbus_iommu_init()
88 iommu->end = 0xffffffff; in sbus_iommu_init()
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| D | io-unit.c | 66 op->dev.archdata.iommu = iounit; in iounit_iommu_init()
148 struct iounit_struct *iounit = dev->archdata.iommu; in iounit_map_page()
164 struct iounit_struct *iounit = dev->archdata.iommu; in iounit_map_sg()
182 struct iounit_struct *iounit = dev->archdata.iommu; in iounit_unmap_page()
197 struct iounit_struct *iounit = dev->archdata.iommu; in iounit_unmap_sg()
217 struct iounit_struct *iounit = dev->archdata.iommu; in iounit_alloc()
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| /arch/x86/events/amd/ |
| D | iommu.c | 37 struct amd_iommu *iommu; member
233 return (container_of(ev->pmu, struct perf_amd_iommu, pmu))->iommu; in perf_event_2_iommu()
238 struct amd_iommu *iommu = perf_event_2_iommu(ev); in perf_iommu_enable_event() local
245 amd_iommu_pc_set_reg(iommu, bank, cntr, IOMMU_PC_COUNTER_SRC_REG, ®); in perf_iommu_enable_event()
251 amd_iommu_pc_set_reg(iommu, bank, cntr, IOMMU_PC_DEVID_MATCH_REG, ®); in perf_iommu_enable_event()
257 amd_iommu_pc_set_reg(iommu, bank, cntr, IOMMU_PC_PASID_MATCH_REG, ®); in perf_iommu_enable_event()
263 amd_iommu_pc_set_reg(iommu, bank, cntr, IOMMU_PC_DOMID_MATCH_REG, ®); in perf_iommu_enable_event()
268 struct amd_iommu *iommu = perf_event_2_iommu(event); in perf_iommu_disable_event() local
272 amd_iommu_pc_set_reg(iommu, hwc->iommu_bank, hwc->iommu_cntr, in perf_iommu_disable_event()
295 struct amd_iommu *iommu = perf_event_2_iommu(event); in perf_iommu_start() local
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| D | iommu.h | 35 extern int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
38 extern int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
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| /arch/sparc/include/asm/ |
| D | iommu-common.h | 35 extern void iommu_tbl_pool_init(struct iommu_map_table *iommu,
43 struct iommu_map_table *iommu,
49 extern void iommu_tbl_range_free(struct iommu_map_table *iommu,
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| D | iommu_64.h | 55 struct iommu { struct
89 int iommu_table_init(struct iommu *iommu, int tsbsize, argument
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| /arch/arm64/boot/dts/mediatek/ |
| D | mt8173.dtsi | 501 iommu: iommu@10205000 { label
509 #iommu-cells = <1>;
923 iommus = <&iommu M4U_PORT_MDP_RDMA0>;
934 iommus = <&iommu M4U_PORT_MDP_RDMA1>;
964 iommus = <&iommu M4U_PORT_MDP_WDMA>;
973 iommus = <&iommu M4U_PORT_MDP_WROT0>;
982 iommus = <&iommu M4U_PORT_MDP_WROT1>;
992 iommus = <&iommu M4U_PORT_DISP_OVL0>;
1002 iommus = <&iommu M4U_PORT_DISP_OVL1>;
1012 iommus = <&iommu M4U_PORT_DISP_RDMA0>;
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| /arch/x86/include/asm/ |
| D | pci_64.h | 11 return sd->iommu; in pci_iommu()
17 sd->iommu = val; in set_pci_iommu()
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| /arch/powerpc/boot/dts/fsl/ |
| D | p5020si-post.dtsi | 66 fsl,iommu-parent = <&pamu0>;
95 fsl,iommu-parent = <&pamu0>;
124 fsl,iommu-parent = <&pamu0>;
153 fsl,iommu-parent = <&pamu0>;
178 fsl,iommu-parent = <&pamu0>;
307 iommu@20000 {
382 fsl,iommu-parent = <&pamu0>;
388 fsl,iommu-parent = <&pamu0>;
400 fsl,iommu-parent = <&pamu1>;
413 fsl,iommu-parent = <&pamu1>;
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| D | p3041si-post.dtsi | 66 fsl,iommu-parent = <&pamu0>;
95 fsl,iommu-parent = <&pamu0>;
124 fsl,iommu-parent = <&pamu0>;
176 fsl,iommu-parent = <&pamu0>;
302 iommu@20000 {
377 fsl,iommu-parent = <&pamu0>;
383 fsl,iommu-parent = <&pamu0>;
395 fsl,iommu-parent = <&pamu1>;
409 fsl,iommu-parent = <&pamu1>;
417 fsl,iommu-parent = <&pamu1>;
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| D | p2041si-post.dtsi | 66 fsl,iommu-parent = <&pamu0>;
95 fsl,iommu-parent = <&pamu0>;
124 fsl,iommu-parent = <&pamu0>;
149 fsl,iommu-parent = <&pamu0>;
275 iommu@20000 {
350 fsl,iommu-parent = <&pamu0>;
356 fsl,iommu-parent = <&pamu0>;
368 fsl,iommu-parent = <&pamu1>;
398 fsl,iommu-parent = <&pamu1>;
406 fsl,iommu-parent = <&pamu1>;
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| D | p5040si-post.dtsi | 66 fsl,iommu-parent = <&pamu0>;
94 fsl,iommu-parent = <&pamu0>;
122 fsl,iommu-parent = <&pamu0>;
262 iommu@20000 {
342 fsl,iommu-parent = <&pamu0>;
348 fsl,iommu-parent = <&pamu0>;
360 fsl,iommu-parent = <&pamu2>;
373 fsl,iommu-parent = <&pamu4>;
382 fsl,iommu-parent = <&pamu4>;
390 fsl,iommu-parent = <&pamu4>;
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| /arch/arm64/mm/ |
| D | dma-mapping.c | 41 const struct iommu_ops *iommu, bool coherent) in arch_setup_dma_ops() argument
52 if (iommu) in arch_setup_dma_ops()
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| /arch/arm/boot/dts/ |
| D | dra74x.dtsi | 70 compatible = "ti,dra7-dsp-iommu";
74 #iommu-cells = <0>;
80 compatible = "ti,dra7-dsp-iommu";
84 #iommu-cells = <0>;
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