| /arch/parisc/lib/ |
| D | io.c | 169 unsigned int l = 0, l2; in insw() local
221 l2 = cpu_to_le16(inw(port)); in insw()
222 *(unsigned short *)p = (l & 0xff) << 8 | (l2 >> 8); in insw()
224 l = l2; in insw()
241 unsigned int l = 0, l2; in insl() local
268 l2 = cpu_to_le32(inl(port)); in insl()
269 *(unsigned int *)p = (l & 0xffff) << 16 | (l2 >> 16); in insl()
271 l = l2; in insl()
285 l2 = cpu_to_le32(inl(port)); in insl()
286 *(unsigned int *)p = (l & 0xff) << 24 | (l2 >> 8); in insl()
[all …]
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| /arch/sparc/lib/ |
| D | PeeCeeI.c | 37 u32 l, l2; in outsl() local
65 l2 = *(u32 *)src; in outsl()
66 l |= (l2 >> 24); in outsl()
68 l = l2 << 8; in outsl()
77 l2 = *(u32 *)src; in outsl()
78 l |= (l2 >> 8); in outsl()
80 l = l2 << 24; in outsl()
154 u32 l = 0, l2, *pi; in insl() local
166 l2 = __raw_readl(addr); in insl()
167 *pi++ = (l << 16) | (l2 >> 16); in insl()
[all …]
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| D | muldi3.S | 51 add %g1, %g2, %l2
62 mov %l2, %i0
63 add %l2, %l0, %i0
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| D | xor.S | 375 ldda [%i0 + 0x30] %asi, %l2 /* %l2/%l3 = dest + 0x30 */
389 xor %l2, %l0, %l2
391 stxa %l2, [%i0 + 0x30] %asi
568 ldda [%i0 + 0x00] %asi, %l2 /* %l2/%l3 = dest + 0x00 */
578 xor %l2, %l0, %l2
580 stxa %l2, [%i0 + 0x00] %asi
583 ldda [%i0 + 0x10] %asi, %l2 /* %l2/%l3 = dest + 0x10 */
594 xor %l2, %l0, %l2
596 stxa %l2, [%i0 + 0x10] %asi
599 ldda [%i0 + 0x20] %asi, %l2 /* %l2/%l3 = dest + 0x20 */
[all …]
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| /arch/c6x/lib/ |
| D | strasgi.S | 24 || cmpltu .l2 B2, B7, B0
30 || mv .l2 B7, B6
34 || cmpltu .l2 B1, B6, B0
39 || cmpltu .l2 12, B6, B0
44 || cmpltu .l2 8, B6, B0
49 || cmpltu .l2 4, B6, B0
54 || cmpltu .l2 0, B6, B0
59 || cmpltu .l2 B2, B7, B0
63 cmpltu .l2 B1, B6, B0
67 || cmpltu .l2 12, B6, B0
[all …]
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| D | divi.S | 30 || cmpgt .l2 0, B4, B1
33 || [B1] neg .l2 B4, B4
38 || mv .l2 B3,B5
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| D | divremi.S | 12 || cmpgt .l2 0, B4, B2
17 || [B2] neg .l2 B4, B4
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| /arch/arm64/boot/dts/amlogic/ |
| D | meson-g12b.dtsi | 52 next-level-cache = <&l2>;
60 next-level-cache = <&l2>;
68 next-level-cache = <&l2>;
76 next-level-cache = <&l2>;
84 next-level-cache = <&l2>;
92 next-level-cache = <&l2>;
95 l2: l2-cache0 { label
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| D | meson-g12a.dtsi | 21 next-level-cache = <&l2>;
29 next-level-cache = <&l2>;
37 next-level-cache = <&l2>;
45 next-level-cache = <&l2>;
48 l2: l2-cache0 { label
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| D | meson-sm1.dtsi | 22 next-level-cache = <&l2>;
30 next-level-cache = <&l2>;
38 next-level-cache = <&l2>;
46 next-level-cache = <&l2>;
49 l2: l2-cache0 { label
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| D | meson-gxm.dtsi | 50 next-level-cache = <&l2>;
59 next-level-cache = <&l2>;
68 next-level-cache = <&l2>;
77 next-level-cache = <&l2>;
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| /arch/arm64/boot/dts/realtek/ |
| D | rtd1295.dtsi | 22 next-level-cache = <&l2>;
29 next-level-cache = <&l2>;
36 next-level-cache = <&l2>;
43 next-level-cache = <&l2>;
46 l2: l2-cache { label
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| /arch/sparc/prom/ |
| D | cif.S | 18 ldx [%o1 + 0x0008], %l2 ! prom_cif_handler
22 call %l2
40 ldx [%i1 + 0x000], %l2
41 call %l2
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| /arch/s390/lib/ |
| D | string.c | 261 const char *s2, unsigned long l2) in clcle() argument
266 register unsigned long r5 asm("5") = (unsigned long) l2; in clcle()
286 int l1, l2; in strstr() local
288 l2 = __strend(s2) - s2; in strstr()
289 if (!l2) in strstr()
292 while (l1-- >= l2) { in strstr()
295 cc = clcle(s1, l2, s2, l2); in strstr()
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| /arch/csky/mm/ |
| D | cachev1.c | 32 static void cache_op_all(unsigned int value, unsigned int l2) in cache_op_all() argument
37 if (l2 && (mfcr_ccr2() & CCR2_L2E)) { in cache_op_all()
47 unsigned int l2) in cache_op_range() argument
56 cache_op_all(value, l2); in cache_op_range()
60 if ((mfcr_ccr2() & CCR2_L2E) && l2) in cache_op_range()
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| /arch/sparc/include/asm/ |
| D | head_32.h | 25 jmpl %l2, %g0; rett %l2 + 4; nop; nop;
67 rd %psr, %i0; jmp %l2; rett %l2 + 4; nop;
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| /arch/microblaze/lib/ |
| D | mulsi3.S | 28 l2: label
33 beqi r7, l2
34 bneid r6, l2
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| /arch/sparc/kernel/ |
| D | head_64.S | 171 mov 0, %l2
178 stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1, 0
189 mov (1b - prom_compatible_name), %l2
192 sub %l0, %l2, %l2
204 stx %l2, [%sp + 2047 + 128 + 0x20] ! arg2, "compatible"
213 mov (1b - prom_chosen_path), %l2
216 sub %l0, %l2, %l2
226 stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1, "/chosen"
234 mov (1b - prom_mmu_name), %l2
237 sub %l0, %l2, %l2
[all …]
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| D | rtrap_64.S | 192 mov %g6, %l2
209 mov %l2, %g6
220 ldx [%sp + PTREGS_OFF + PT_V9_TPC], %l2
229 wrpr %l2, %g0, %tpc
254 rdpr %otherwin, %l2
257 661: wrpr %l2, %g0, %canrestore
264 brnz,pt %l2, user_rtt_restore
331 ldub [%l6 + %o0], %l2
335 andcc %l2, (FPRS_FEF|FPRS_DU), %g0
337 and %l2, FPRS_DL, %l6
[all …]
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| /arch/arm/boot/dts/ |
| D | bcm2837.dtsi | 60 next-level-cache = <&l2>;
75 next-level-cache = <&l2>;
90 next-level-cache = <&l2>;
105 next-level-cache = <&l2>;
110 * /e/level-2-memory-system/about-the-l2-memory-system?lang=en
114 l2: l2-cache0 { label
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| D | nuvoton-npcm750.dtsi | 23 next-level-cache = <&l2>;
32 next-level-cache = <&l2>;
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| /arch/powerpc/boot/dts/fsl/ |
| D | p4080si-pre.dtsi | 100 L2_0: l2-cache {
110 L2_1: l2-cache {
120 L2_2: l2-cache {
130 L2_3: l2-cache {
140 L2_4: l2-cache {
150 L2_5: l2-cache {
160 L2_6: l2-cache {
170 L2_7: l2-cache {
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| /arch/x86/boot/ |
| D | string.c | 174 size_t l1, l2; in strstr() local
176 l2 = strlen(s2); in strstr()
177 if (!l2) in strstr()
180 while (l1 >= l2) { in strstr()
182 if (!memcmp(s1, s2, l2)) in strstr()
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| /arch/sparc/power/ |
| D | hibernate_asm.S | 76 ldxa [%l0 + 8] %asi, %l2 /* orig_address */
80 sub %l2, %g7, %l2
85 stxa %g2, [%l2 + %l3] ASI_PHYS_USE_EC
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| /arch/arm64/boot/dts/synaptics/ |
| D | as370.dtsi | 30 next-level-cache = <&l2>;
39 next-level-cache = <&l2>;
48 next-level-cache = <&l2>;
57 next-level-cache = <&l2>;
61 l2: cache { label
|