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Searched refs:l2x0_base (Results 1 – 6 of 6) sorted by relevance

/arch/arm/mach-imx/
Dsystem.c88 void __iomem *l2x0_base; in imx_init_l2cache() local
96 l2x0_base = of_iomap(np, 0); in imx_init_l2cache()
97 if (!l2x0_base) in imx_init_l2cache()
100 if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) { in imx_init_l2cache()
102 val = readl_relaxed(l2x0_base + L310_PREFETCH_CTRL); in imx_init_l2cache()
111 writel_relaxed(val, l2x0_base + L310_PREFETCH_CTRL); in imx_init_l2cache()
114 iounmap(l2x0_base); in imx_init_l2cache()
Dmm-imx3.c78 void __iomem *l2x0_base; in imx3_init_l2x0() local
99 l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096); in imx3_init_l2x0()
100 if (!l2x0_base) { in imx3_init_l2x0()
105 l2x0_init(l2x0_base, 0x00030024, 0x00000000); in imx3_init_l2x0()
/arch/arm/mach-ux500/
Dcpu-db8500.c36 void __iomem *l2x0_base; in ux500_l2x0_unlock() local
39 l2x0_base = of_iomap(np, 0); in ux500_l2x0_unlock()
41 if (!l2x0_base) in ux500_l2x0_unlock()
52 writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE + in ux500_l2x0_unlock()
54 writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I_BASE + in ux500_l2x0_unlock()
57 iounmap(l2x0_base); in ux500_l2x0_unlock()
/arch/arm/mm/
Dcache-l2x0.c39 static void __iomem *l2x0_base; variable
134 void __iomem *base = l2x0_base; in l2c_disable()
145 l2x0_saved_regs.aux_ctrl = readl_relaxed(l2x0_base + L2X0_AUX_CTRL); in l2c_save()
150 void __iomem *base = l2x0_base; in l2c_resume()
189 void __iomem *base = l2x0_base; in l2c210_inv_range()
208 void __iomem *base = l2x0_base; in l2c210_clean_range()
217 void __iomem *base = l2x0_base; in l2c210_flush_range()
226 void __iomem *base = l2x0_base; in l2c210_flush_all()
236 __l2c210_cache_sync(l2x0_base); in l2c210_sync()
309 void __iomem *base = l2x0_base; in l2c220_inv_range()
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Dcache-l2x0-pmu.c20 static void __iomem *l2x0_base; variable
66 writel_relaxed(val, l2x0_base + L2X0_EVENT_CNT0_CFG - 4 * idx); in l2x0_pmu_counter_config_write()
71 return readl_relaxed(l2x0_base + L2X0_EVENT_CNT0_VAL - 4 * idx); in l2x0_pmu_counter_read()
76 writel_relaxed(val, l2x0_base + L2X0_EVENT_CNT0_VAL - 4 * idx); in l2x0_pmu_counter_write()
81 u32 val = readl_relaxed(l2x0_base + L2X0_EVENT_CNT_CTRL); in __l2x0_pmu_enable()
83 writel_relaxed(val, l2x0_base + L2X0_EVENT_CNT_CTRL); in __l2x0_pmu_enable()
88 u32 val = readl_relaxed(l2x0_base + L2X0_EVENT_CNT_CTRL); in __l2x0_pmu_disable()
90 writel_relaxed(val, l2x0_base + L2X0_EVENT_CNT_CTRL); in __l2x0_pmu_disable()
500 l2x0_base = base; in l2x0_pmu_register()
507 if (!l2x0_base) in l2x0_pmu_init()
/arch/arm/mach-omap2/
Domap-mpuss-lowpower.c198 void __iomem *l2x0_base = omap4_get_l2cache_base(); in save_l2x0_context() local
200 if (l2x0_base && sar_base) { in save_l2x0_context()